JPS58103151A - Inspection of semiconductor substrate - Google Patents

Abstract

PURPOSE:To provide the inspection method of the semiconductor substrate enabled to enlarge the throughput at the inspection process of semiconductor device by a method wherein the inspection process is performed jumping over a semiconductor chip having pattern inferiority. CONSTITUTION:After a pattern inspection is finished, the semiconductor substrate is advanced to the next progress of semiconductor process of etching, oxidation, etc. The mask positioning process and the pattern inspection are repeated for plural times thereafter, and the semiconductor devices are formed on respective chips on the semiconductor substrate. The semiconductor substrate formed with the semiconductor devices of the plural number is advanced next to the inspection process of the semiconductor devices of the respective chips. At this time, the semiconductor substrate formed with the semiconductor devices is set in a tester 4, and discrimination of quality of the first chip is performed at first comparing with address output of an inferior chip read from a memory unit. When the chip thereof is inferior, discrimination is advanced to the next chip without performing the inspection of electric characteristic. When the chip thereof is the article of good quality, and the inspection of electric characteristic results in good, discrimination is advanced to the next chip, and when the result of inspection is inferior, after the address of the chip thereof is inputted to the memory unit mentioned above to be stored as an inferior article, discrimination proceeds to the next chip.

Description

[Detailed description of the invention] The present invention relates to a method for inspecting a semiconductor substrate.

BACKGROUND OF THE INVENTION With the large-scale integration of semiconductor devices, efforts are being made to increase chip dimensions and miniaturize pattern dimensions. Due to the increase in chip size and the miniaturization of pattern dimensions, the pattern failure rate of the conventionally used -2° block exposure method mask aligners increases rapidly.Recently, reduction projection exposure method mask aligners have been put into practical use. Consideration is underway to change the In the reduction projection exposure method, a mask is manufactured with a size several times larger than the desired pattern, so pattern defects caused by mask manufacturing are reduced, and it is also possible to form a finer pattern. Furthermore, even if foreign matter adheres to the mask during the mask alignment process, pattern defects due to foreign matter are reduced compared to the batch exposure method because of reduced projection.

Furthermore, since the pattern on the mask is formed several times the size of the desired pattern, the mask manufacturing cost is low, mask inspection is easy, and the inspection cost is also low.

Although the reduction projection exposure method has many other features in addition to those mentioned above, its drawback is that the throughput is small because each chip is sequentially exposed.

Furthermore, with the large-scale integration of semiconductor devices, the number of built-in functions has increased, and the throughput in the testing process for semiconductor devices has become significantly smaller.

The present invention has been made in view of the above-mentioned conventional drawbacks,
An object of the present invention is to provide a semiconductor substrate inspection method that enables the inspection process to be performed over semiconductor chips having pattern defects, thereby increasing the throughput in the semiconductor device inspection process.

The present invention will be explained in detail below using examples.

1, 2, and 3 are diagrams showing a first embodiment of the semiconductor substrate inspection method according to the present invention, in which FIG. 1 shows a mask alignment process, FIG. 2 shows an inspection process, FIG. 3 shows the assembly process.

First, the mask alignment process shown in FIG. 1 will be explained. After applying a resist to a semiconductor substrate that has been subjected to semiconductor processing such as oxidation, the process proceeds to a mask alignment process using a reduction projection exposure type mask aligner 1. In the mask alignment process, the first chip is determined to be good or bad. The determination of whether the chip is good or bad is stored in a storage device 2 connected to the mask aligner 1 as the address of the chip. If the judgment of good/bad read out from the storage device 2 is good, the mask aligner 1 performs an alignment operation and an exposure process on that chip, and the process moves to the next chip. On the other hand, if that chip is defective, the process skips over that chip and moves on to the next chip without performing alignment or exposure processing. If the mask alignment process is the first mask alignment process, since the memory device 2 does not store (input) the determination of good/bad, all chips are judged as good and the exposure process is performed. In this case, since the alignment key is not formed on the semiconductor substrate, no alignment operation is required. Thereafter, the above-described determination of good/bad, alignment operation, and exposure processing are sequentially performed on each chip, and the mask alignment process is completed.

After the mask alignment process is completed, the semiconductor substrate is subjected to a development process to form a pattern. The semiconductor substrate on which the pattern has been formed is then subjected to pattern inspection by a pattern inspection device 3. In the pattern inspection, first of all, it is determined whether the chip is good or bad based on the output from the storage device. If the chip is determined to be defective, proceed to the next chip without identifying whether it is good or defective; on the other hand, if it is good, the pattern formed in the mask alignment process is compared with the mask pattern,
The pattern of the chip is determined to be good or bad. If the pattern of the chip is determined to be defective in pattern formation, the address of the chip is input to the storage device 2 and stored as defective. If the chip is judged to be good, proceed to the next chip.

Thereafter, similarly, the above-described determination of good/bad, identification of good/bad, and recognition of defect are sequentially performed on each chip, and the pattern inspection is completed.

After pattern inspection, the semiconductor substrate is etched.

Proceed to the next semiconductor processing step such as oxidation. Thereafter, a semiconductor device is formed on each chip on a semiconductor substrate by repeating the mask alignment process and turn inspection shown in FIG. 1 a plurality of times.

The semiconductor substrate on which a plurality of semiconductor devices are formed next proceeds to a step of testing the semiconductor devices of each chip. As shown in the inspection process in Figure 2, a semiconductor substrate on which a semiconductor device is formed is placed on the tester 4, and the address of the defective chip read out from the memory device is output to determine whether the first chip is good or bad. Do this in light of. If that chip is defective, the process proceeds to the next chip without testing its electrical characteristics. If the chip is good, the electrical characteristics are inspected, and if the test result is good, move on to the next chip; if the test result is bad, the address of the chip is input into the storage device and stored as defective, and then Proceed to next chip.

Thereafter, a similar inspection process is sequentially performed on each chip, and the inspection process is completed.

After the inspection process is completed, the semiconductor substrate proceeds to the assembly process.

As shown in the assembly process of FIG. Only the chips having the following values are sequentially extracted and assembled by the assembly device 6.

In the above embodiments, mask aligner-1 degree pattern inspection device 3. The same storage device was used as the storage device 2 connected to the tester 4 and the assembly device 6, but 7-2 separate storage devices were used for each device, and only the magnetic tape was shared. Data can also be used.

Furthermore, although a reduction projection exposure type mask aligner is used as the mask aligner, the present invention is not limited to the reduction projection exposure type, and may be a method of exposing one chip at a time or a plurality of chips at a time.

Next, a second embodiment of the semiconductor substrate inspection method according to the present invention will be described. In this second embodiment, inkjet marking was used in place of the storage device of the first embodiment. In other words, before performing an alignment operation using a mask aligner, the presence or absence of inkjet markings on the chip is checked using the reflected light image, and if markings are present, it means that the chip has a pattern defect. Proceed to the next chip without performing alignment operation or exposure processing. If there is no marking, the process proceeds to the next chip that has been subjected to alignment and exposure processing, and thereafter the same processing is sequentially applied to each chip to complete the mask alignment process.

After the semiconductor substrate is developed, each chip is sequentially pattern-inspected using a pattern inspection device.

Chips with pattern defects are marked using inkjet.

In the inspection process, markings are detected prior to testing the electrical characteristics of the semiconductor device of each chip, and if there is a marking, the next chip is moved on, and if not, the electrical characteristics of the semiconductor device are tested. Thereafter, markings are detected and the electrical characteristics of the semiconductor device are inspected on each chip in turn in the same manner, and if the electrical characteristics are poor, a new marking is applied.

In the assembly process, defective markings made on each chip of the semiconductor substrate during the mask alignment process and inspection process are detected, and only good chips are assembled.

As described in the second embodiment above, in the second embodiment, the memory device used for determining and recognizing defective chips in the first embodiment is replaced with inkjet marking. Inkje,? By using the marking method, workers can directly visually confirm the distribution of defective chips within the semiconductor substrate in each process, and the results can be quickly fed back to the semiconductor device manufacturing process.

Note that laser marking may be used instead of the inkjet marking in the second embodiment. Using a laser makes it possible to make the marking smaller, so for example, by marking the alignment key with a laser, alignment operation and marking detection can be performed at the same time, and it can also be applied even if the dimensions of each chip are small. New features such as:

In the above first embodiment and second embodiment,
Operations such as defect determination, identification, and defect recognition can all be automated, and an automated semiconductor substrate manufacturing and inspection line can be configured in the mask alignment process, inspection process, and assembly process. In addition, during the pattern inspection or electrical characteristic inspection process, the semiconductor substrate inspection method of the present invention is applied only to areas where defective chips, which are known from experience, are abundant, and the throughput is further improved as shown in FIG.
- It is also possible. It is also possible to perform the above-mentioned inspection on the most defective pattern within the chip, or to conduct the electrical characteristic inspection only on a specific semiconductor device within the chip, or only on a test transistor.

As described above, in the semiconductor substrate inspection method according to the present invention, a pattern formed on a semiconductor substrate and a mask pattern are compared to detect a defective pattern, and the defective pattern is detected in the next mask alignment process or inspection process. The purpose is to increase the throughput in the mask alignment process or inspection process by skipping over semiconductor chips having The effect will be extremely noticeable.

[Brief explanation of drawings]

FIG. 1 is a mask alignment process diagram showing a semiconductor substrate manufacturing method according to an embodiment of the present invention, FIG. 2 is an inspection process diagram in the same method, and FIG. 3 is an assembly process diagram in the same method. 1...Mask aligner-12...Storage device, 3...Pattern inspection device, 4...
・Tester, 6... Assembly equipment. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 25A aS diagram

Claims (1)

[Claims] A step of transferring a mask pattern to each semiconductor chip on a semiconductor substrate, and a step of comparing the pattern transferred to the semiconductor chip and the mask pattern to inspect whether the pattern of the semiconductor chip is good or bad, A defective semiconductor chip is identified based on the inspection result of whether the pattern is good or bad, and the characteristic inspection process is sequentially performed on the semiconductor devices, skipping the characteristic inspection process of the semiconductor device in the defective semiconductor chip. A method for inspecting semiconductor substrates.