WO2021184526A1

WO2021184526A1 - Priority ranking device and method for detection object defect pattern, and storage medium

Info

Publication number: WO2021184526A1
Application number: PCT/CN2020/090995
Authority: WO
Inventors: 小林尚弘; 卢意飞; 赵宇航; 李铭; 黄寅
Original assignee: 上海集成电路研发中心有限公司; 上海先综检测有限公司
Priority date: 2020-03-20
Filing date: 2020-05-19
Publication date: 2021-09-23
Also published as: CN111429427B; JP7422893B2; CN111429427A; JP2023516781A

Abstract

A priority ranking device and method for a detection object defect pattern, and a storage medium. The priority ranking device comprises a defect detection result reading module, a defect detection result analysis module, a layout data reading module, a layout data analysis module, a layout data unit analysis module, a data processing analysis module, a defect position importance determination module, a picture display control module connected between the data processing analysis module and a display, and a keyboard control module connected between the data processing analysis module and a keyboard. A detection object defect pattern output by a detection device is compared with hierarchical construction information of original design layout data of a semiconductor device so as to obtain the priority ranking of the detection object defect pattern.

Description

Priority sorting device, sorting method and storage medium for detecting object defect patterns

cross reference

This application claims the priority of the Chinese patent application with the application number 202010202830.8 filed on March 20, 2020. The content of the above application is included here by reference.

Technical field

The present invention relates to the technical field of semiconductor manufacturing, in particular to a data processing device and a processing method thereof, and more specifically, to a priority ranking method, a ranking device and a storage medium for detecting object defect patterns.

technical background

When performing defect inspection on the fine patterns on semiconductor wafers or masks, the industry usually adopts two methods: implementing comprehensive inspection and narrowing the inspection scope. The comprehensive detection method is to detect all candidate positions, but there is a problem of huge detection time. The method of narrowing the detection range is to detect the selected position, and not to detect the position that is not selected. Although the method of narrowing the detection range can shorten the detection time, there is a problem that it is necessary to determine in advance which position (that is, the position with detection significance) to perform the detection.

The method of narrowing the detection range (that is, the location selection method with detection significance), the detection can identify the nuisance defect on the wafer from the defect pattern output by the inspection device, that is, by removing it from the inspection object Exclude and reduce the number of detections. Nuisance defects (nuisance defects) refer to defects that are judged to be allowable. In the prior art (for example, Japanese Patent Publication No. 5628656, etc.), it is possible to use design intent data (Designer Intent Data) to select a method for detecting positions that are truly meaningful when designing wafers and masks.

Please refer to FIG. 1, which is a schematic diagram of a pattern defect extraction mode of a detection object based on a method of narrowing the detection range used in the prior art. As shown in Figure 1, the number 10 indicates the data to be inspected determined by the reticle, the number 20 indicates the design intent data, the number 22 indicates the allowable defects in the defined reticle, and the number 24 indicates that the coordinates of the reticle are converted to The coordinates of the wafer, the reference number 26 indicates the use of a reticle to form a pattern on the wafer, the reference number 28 indicates the inspection of the wafer, the reference number 30 indicates the identification of harmful defects on the wafer, and the reference number 32 indicates the actual defect from the wafer The nuisance defect is separated in the middle, the reference number 34 indicates the processing of the actual defect data, the reference number 36 indicates the two-dimensional map of the generated wafer, and the reference number 38 indicates whether the nuisance defect has an impact on the yield rate of the semiconductor device, the reference number 40 indicates whether the allowable defect is correctly classified, and the reference number 42 indicates that the defect of the detection target pattern in the reticle is analyzed to determine whether the wafer needs to be redone or discarded.

In addition, in the above-mentioned prior art, in addition to the design intent data, the results of the printing process of the simulated reticle and the results of the electrical characteristics simulation are used as the basis for judging the nuisance defect, that is, from the design intent data and the simulated reticle The results of the printing process and the simulation results of electrical characteristics, etc., to determine whether a defect is a problem.

However, the above method needs to analyze the positions of all defect patterns using design intent data for determination. There is a problem in that since the number of defect patterns output from the inspection device and the amount of data on their positions are huge, it takes a lot of time for analysis. As described above, in the prior art, there is a problem that it is difficult to effectively detect a position with detection significance in a short time. In addition, there is no prioritization of the defect patterns that need to be detected other than nuisance defects. Therefore, it is impossible to start inspection from important defect patterns.

Summary of the invention

The object of the present invention is to provide a method for prioritizing wafer defect patterns, a ranking device, and a storage medium with the function of analyzing original design layout data. The unit hierarchical structure information extracted from the layout data is compared to obtain the priority ranking of the defect patterns of the inspection object.

In order to achieve the above objective, the technical solution of the present invention is as follows:

A device for prioritizing defect patterns of a detection object, the detection object being composed of at least one basic unit or at least one pseudo unit; comprising:

A defect detection result reading module for reading the defect pattern of the detection object;

The defect detection result analysis module receives the defect pattern sent by the defect detection result reading module, and reads the defect pattern information. The defect pattern information includes at least the defect coordinates of the defect pattern, the defect target layer, and the defect type ；

The layout data reading module receives the original design layout data of the inspection object;

The layout data analysis module reads the structure and layout coordinates of the defect object layer in the original design layout data;

The layout data unit analysis module, for the original design layout data with a multi-level structure, extracts the types of basic units of the basic functions and specific functions included in each object layer and the number of configurations of each basic unit; The original design layout data constructed by extracting the configuration number of the basic function and the specific function pseudo unit included in the single object layer and the configuration number of the repeated layout pattern combination, wherein the repeated layout pattern combination includes at least two coordinates The unit combination formed by the pseudo units with the same positional relationship, and the repeated layout pattern combination constitutes a new pseudo unit, obtains the configuration number of all the pseudo units in the original design layout data, and records all the basic units and The configuration number of pseudo-units;

The data processing analysis module, based on the defect pattern of the inspection object, for the original design layout data of the multi-level structure, sequentially determines whether each of the basic unit location areas is affected by the corresponding defect pattern, if so, then Identify the basic unit as a basic unit affected by a defective pattern; for the original design layout data that does not have a hierarchical structure, determine in turn whether each dummy unit location area has the corresponding defective pattern influence, if so, Identifying the dummy unit as a dummy unit affected by the defective pattern, and determining the basic unit and the dummy unit affected by the defect as a defect risk unit;

The defect location importance determination module, based on the defect risk unit output from the data processing analysis module and the configuration number of the basic unit and the number of pseudo units output from the corresponding layout data unit analysis module, from the defect risk unit The defect patterns corresponding to the cells with a large number of configurations start to be ranked in importance, wherein the more the number of configurations, the higher the ranking of the importance.

Further, in the defect position importance determination module, according to the ranking result of the importance degree, the higher importance degree is determined as the higher detection priority, and the detection is performed sequentially starting from the defect pattern with the higher priority.

Further, the device for sorting the priority of the defect pattern of the detection target further includes a storage module connected to the data processing analysis module for storing all the defect patterns, the defect risk unit and the importance degree.

Further, the device for prioritizing the defect pattern of the detection target further includes a correction alarm module. For each basic unit and pseudo unit constituting the defect risk unit, when it is configured in the original design layout data, the configuration number When the predetermined number is reached or exceeds the predetermined number, the correction alarm module gives an alarm.

In order to achieve the above objective, another technical solution of the present invention is as follows:

A method for prioritizing the defect patterns of a detection object, the detection object being composed of at least one basic unit or at least one pseudo unit; it includes the following steps:

Step S1: receiving the original design layout data of the inspection object when it is designed;

Step S2: Read the object layer information in the original design layout data, the object layer information includes at least an object layer structure and object layer layout coordinates; the object layer structure includes a multi-level structure and does not have a hierarchical structure;

Step S3: For the original design layout data with a multi-level structure, extract the types of basic units of basic functions and specific functions included in each layer and the number of configurations of each basic unit; for the original design without a hierarchical structure Design layout data, extract the configuration number of basic functions and specific function pseudo-units included in a single object layer and the configuration number of repeated layout pattern combinations, where the repeated layout pattern combination includes at least two pseudo-units with the same coordinate positional relationship The formed unit combination is formed into a new pseudo unit with a repeating pattern combination, the configuration number of all pseudo units configured in the original design layout data is extracted, and the configuration number of all basic units and pseudo units is recorded;

Step S4: receiving the defect pattern from the defect inspection result of the inspection object, and reading the defect pattern information, the defect pattern information including at least the defect coordinates of the defect pattern, the defect target layer, and the defect type;

Step S5: According to the defect pattern output from the semiconductor inspection device, for the original design layout data of the multilayer structure, sequentially determine whether each of the basic unit location areas is affected by the corresponding defect pattern, if so, Identify the basic unit as a basic unit affected by the defective pattern; for the original design layout data that does not have a hierarchical structure, determine in turn whether the corresponding defective pattern affects each of the pseudo-unit location areas, and if so , Mark the dummy unit as a dummy unit affected by the defective pattern, and determine the basic unit and the dummy unit affected by the defective pattern as a defect risk unit; and

Step S6: According to the arrangement number of the defect risk unit and the basic unit and the arrangement number of the dummy unit, sort the defect patterns corresponding to the unit with a larger number of arrangements in the defect risk unit, wherein the The more the number of configurations, the higher the importance ranking.

Further, the priority ranking method of the defect patterns of the detection target further includes step S7, according to the ranking result of the importance degree, determining the higher importance degree as higher priority, starting from the defect pattern with higher priority degree Tests are carried out in sequence.

Further, the method for prioritizing the defect pattern of the detection target further includes step S8, when the number of configurations of the basic unit and the dummy unit affected by the defect pattern that are configured in the original design layout data reaches a predetermined value. When the quantity or exceeds the predetermined quantity, a correction alarm will be output.

A computer-readable medium used for a computer-executable prioritization program for detecting object defect patterns, which is installed and run on a computer to execute the following programs:

Receive the original design layout data made during the design of the inspection object;

Receiving the original design layout data, and reading the object layer structure and layout coordinates;

For the original design layout data with a multi-level structure, extract the types of basic units of basic functions and specific functions included in each layer and the number of configurations of each basic unit; for the original design layout data without a hierarchical structure Data, extracting the number of configurations of basic and specific functional pseudo-units included in a single object layer and the number of configurations of repeated layout pattern combinations, where the repeated layout pattern combination is formed by including at least two pseudo-units with the same coordinate positional relationship Unit combination, and repeat the pattern combination to form a new pseudo unit, obtain the configuration number of all pseudo units configured in the original design layout data, and record the configuration number of all basic units and pseudo units;

Receiving the defect pattern from the defect inspection result of the inspection object, and reading the defect coordinates, the target layer and the defect type of the defect pattern;

According to the defect pattern output from the semiconductor inspection device, for the original design layout data of the multi-level structure, it is determined in turn whether the corresponding defect pattern is affected by the location area of each basic unit, and if so, the corresponding defect pattern is identified. The basic unit is a basic unit affected by a defective pattern; for the original design layout data that does not have a hierarchical structure, it is determined in turn whether each dummy unit location area has the corresponding defective pattern influence, and if so, it is marked The dummy unit is a dummy unit affected by a defective pattern, and the basic unit and the dummy unit affected by the defective pattern are determined as defect risk units; and

According to the configuration number of the defect risk unit and the corresponding basic unit and the configuration number of the pseudo unit, the defect patterns corresponding to the unit with the larger configuration number in the defect risk unit are ranked in importance, wherein the more the configuration number is , The higher the importance ranking.

Further, the computer-readable medium storing the priority ranking program of the defect pattern of the detection target further includes executing the following program, according to the ranking result of the importance degree, the higher priority is determined as the higher priority, from The defect patterns with higher priority will be inspected sequentially.

Further, the computer-readable medium storing the priority ranking program of the defect pattern of the detection target further includes executing the following program, when the basic unit and the dummy unit affected by the defect pattern are configured in the original design layout When the number of configurations in the data reaches the predetermined number or exceeds the predetermined number, a correction alarm is output.

It can be seen from the above technical solutions that the present invention proposes a prioritization method, a sorting device and a storage medium for the defect patterns of the inspection object, which is based on the inspection object defect pattern output by the inspection device and the original design layout data of the inspection object. The hierarchical structure information is compared, and the detection priority ranking of the defect pattern of the detection object is obtained.

In addition, in the design process of the same or different semiconductor devices, it is possible to avoid making the same defects in the same basic unit in the subsequent original design layout data, thereby reducing the number of inspection objects; furthermore, in the original design layout data In the design method, the basic unit and dummy unit with the same problem can be modified to reduce the potential defects generated later.

Description of the drawings

Figure 1 shows a schematic diagram of a defect extraction mode based on narrowing the detection range to realize the detection object pattern used in the prior art

FIG. 2 is a schematic structural diagram of a preferred embodiment of the prioritization device for detecting object defect patterns of the present invention

FIG. 3 is a schematic diagram showing the layout data of a chip's original design based on a cell library in an embodiment of the present invention

4 is a schematic diagram of the layout of the basic units and pseudo-units included in the chip based on the analysis of the unit library in an embodiment of the present invention

FIG. 5 is a schematic diagram showing the comparison and importance judgment of the defect patterns of the basic unit and the dummy unit chip included in the embodiment of the present invention

Fig. 6 is a schematic flow chart of the prioritization method for detecting object defect patterns of the present invention

Summary of the invention

The specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

In the embodiment of the present invention, please refer to FIG. 2. FIG. 2 is a schematic structural diagram of a preferred embodiment of the prioritization apparatus for detecting object defect patterns of the present invention. As shown in the figure, the priority ranking device includes a defect detection result reading module, a defect detection result analysis module, a layout data reading module, a layout data analysis module, a layout data unit analysis module, a data processing analysis module, and a defect The position importance determination module, the screen display control module connected between the data processing analysis module and the display, and the keyboard control module connected between the data processing analysis module and the keyboard.

In an embodiment of the present invention, the defect detection result analysis module receives the defect pattern sent by the defect detection result reading module, and reads the defect pattern information, and the defect pattern information includes at least the defect coordinates of the defect pattern , Defect object layer and defect type.

As shown in the figure, the layout data reading module receives the original design layout data of the inspection object; the layout data analysis module reads the structure and layout coordinates of the defective object layer in the original layout data; layout data unit analysis For the original design layout data with a multi-level structure, the module extracts the types of basic units of basic functions and specific functions included in each object layer and the number of configurations of each basic unit; for the original design without a hierarchical structure Layout data, which extracts the number of configurations of pseudo-units of basic functions and specific functions included in the single object layer and the number of combinations of repeated layout patterns, wherein the combination of repeated layout patterns includes at least two pseudo units with the same coordinate positional relationship. The unit combination formed by the unit, and the repeated layout pattern combination constitutes a new pseudo unit, obtains the configuration number of all pseudo units configured in the original design layout data, and records the configuration number of all basic units and the number of pseudo units Configuration number.

It should be noted that the detection object is composed of at least one basic unit and/or at least one dummy unit, and the basic unit and dummy unit are stored in the semiconductor layout design unit library. Here, for the original design layout data that does not have a hierarchical structure, the repeated layout pattern combination can be used as a new pseudo unit, and the process of forming the new pseudo unit will be described below.

For example, when the input original design layout data is an original design layout without a hierarchical structure, there are 4 graphic patterns under the top cell (TOP cell) of the original design layout data.

TOP unit: pattern (polygon) A in position 1

Pattern (polygon) B at position 2

Pattern (polygon) A at position 3

Pattern (polygon) B at position 4

Focusing on the combination of "polygon A + polygon B", the relationship between the coordinate positions of "Position 1 and Position 2" and "Position 3 and Position 4" is exactly the same. At this time, “polygon A+polygon B” can be recognized as a unit (CELLα) and rewritten in the structure with the next hierarchical structure.

TOP unit CELLα(polygon A+polygon B)

At position a

At position b

At this point, it can be considered that the recombined cell CELLα (polygon A + polygon B) is a new pseudo cell.

It is clear to those skilled in the art that the integrated circuit (Application Specific Integrated Circuit, ASIC) chip technology for specialized applications requires high-integration, high-performance microprocessors or application-specific standard parts (ASSP) and other large-scale technologies. Integrated circuit (Large-scale integrated circuit, LSI for short). As the basic unit to realize the basic functions and specific function design of large-scale integrated circuits, the cell library provided by the semiconductor manufacturer is usually used. The cell library includes the basic unit that realizes the basic circuit performance and the macro cell with macro functions such as CPU and memory. Wait. The above-mentioned basic units and macro units are arranged on the chip by wiring tools, and each unit is wired to complete the design of specific circuit functions. In addition, the layout of the CPU, etc. can also be directly assembled as a macro unit. Therefore, the above-mentioned design based on the cell library can reduce design time and design cost, and facilitate the production of LSI. The present invention exerts an effect on the original design layout with such a cell structure.

Please refer to FIG. 3, which is a schematic diagram of an original design layout of a chip based on a cell library in an embodiment of the present invention. As shown in the figure, the chip's original design layout data includes a number of basic units and pseudo-units of different sizes and shapes. The chip's original design layout data has I/O interfaces arranged all around.

In the embodiment of the present invention, for the original design layout data of the multi-level structure, the layout data unit analysis module extracts the number of basic units of each layer of the multi-level structure, and configures each type of basic unit Count the number of configurations in the original design layout data; for the original design layout data that does not have a hierarchical structure, the layout data analysis module extracts the number of configurations and repeated layout patterns of basic functions and specific functional pseudo-units included in a single object layer The number of combination configurations, where the repeated layout pattern combination is a combination of at least two pseudo-units with the same coordinate position relationship, and the repeated pattern combination is used to form a new pseudo-unit, so that all pseudo-units are configured in the original Design the number of configurations in the layout data, and record the number of configurations of all basic units and pseudo-units. For example, the pseudo unit can be a storage component such as a micro memory RAM, or a combination of a micro central processing unit CPU and a micro memory RAM. Finally, determine and record the configuration numbers of all basic units and pseudo-units that are configured in the original design layout data.

Please refer to FIG. 4, which is a schematic diagram of the layout of the basic cells and pseudo cells included in the chip based on cell library analysis in an embodiment of the present invention. As shown in the figure, the chip contains 100 basic units A, 10 basic units B, and 1 basic unit C, as well as one macro unit (CPU) and one macro unit (SRAM).

Please refer to FIG. 2 again. As shown in the figure, the data processing and analysis module determines whether the original design layout data of the multi-level structure is in turn based on the defect pattern output by the semiconductor inspection device. The corresponding defect pattern influence, if there is, the basic unit is identified as the basic unit affected by the defective pattern; for the original design layout data that does not have a hierarchical structure, it is determined in turn whether each pseudo-cell position area has the corresponding defect pattern influence, If yes, the dummy unit is identified as a dummy unit affected by the defective pattern, and the basic unit and dummy unit affected by the defective pattern are determined as a defect risk unit.

In the embodiment of the present invention, the storage module connected to the data processing analysis module may be used to store all the defect patterns, defect risk units, and importance.

In the embodiment of the present invention, the defect location importance determination module receives the defect pattern output from the semiconductor inspection device, and based on the defect pattern, determines whether the same defect pattern affects each of the basic unit and the dummy unit. When it appears, it is extracted as a defect risk unit. In addition, the importance is sorted according to the number of arrangements in the defect risk unit and arranged in the original design layout data, as a reference for the detection priority of the defect pattern corresponding to the defect risk unit.

Preferably, the more the defect risk unit is configured in the original layout design data, the higher the priority ranking is determined.

Please refer to FIG. 5. FIG. 5 is a schematic diagram showing the defect comparison and importance judgment of the basic unit and the dummy unit chip included in the embodiment of the present invention. As shown in the figure, the black dots represent the defect pattern. If the original layout design data with a multi-level structure includes a basic unit (such as CELL A), and the basic unit is reused to form the overall original design layout data.

In the embodiment of the present invention, the basic units and pseudo-units that have defective patterns and are arranged in the original design layout data are judged as the ranking basis with high importance. As shown in the figure, the basic cell CELLA (shown by the white rectangle in the figure) is used in large quantities. 43 are used in Figure 5. The defect pattern is found on the basic cell CELLA, and on the other two basic cells or pseudo cells. A defective pattern was also found. At this time, the risk of the defect pattern on the basic cell CELLA with a large number of configurations is the highest, and it is the basic cell with important defects.

In addition, in the process of repeatedly calling other original design layout data of the basic units and pseudo-units in the unit library, it can feed back and correct the design of the previous defect risk unit to avoid loading the same basic unit. And a problem occurred in the subsequent design layout data of the pseudo unit.

Specifically, for each basic unit and pseudo unit constituting the defect risk unit, when the number of configurations in the original design layout data reaches a predetermined number or exceeds a predetermined number, a correction alarm is output. For example, when the number of the defect risk unit CELLA arranged in the original design layout data is more than 40, it is defined as establishing a correction alarm, and the correction alarm module outputs an alarm to the CELLA.

The following is a summary and detailed description of a method for extracting a defect pattern of a detection object in an embodiment of the present invention. Please refer to FIG. 6, which is a schematic flowchart of the prioritization method for detecting object defect patterns of the present invention.

Including the following steps:

Step S1: receiving the original design layout data produced during the design of the inspection object;

Step S2: Read the object layer information of the original design layout data, where the object layer information includes at least an object layer structure and object layer layout coordinates; the object layer structure includes a multi-level structure and does not have a hierarchical structure;

Step S3: For the original design layout data with a multi-level structure, extract the types of basic units of basic functions and specific functions included in each layer and the number of configurations of each basic unit; for the original design without a hierarchical structure Design the layout data, extract the configuration number of the basic function and the specific function pseudo unit and the repeated layout pattern combination configuration number of the single object layer, wherein the repeated layout pattern combination includes at least two pseudo unit locations with the same coordinate position relationship. The formed unit combination is formed into a new pseudo unit with a repeating pattern combination, the configuration number of all pseudo units configured in the original design layout data is obtained, and the configuration number of all basic units and pseudo units is recorded;

Step S4: receiving the defect pattern from the defect detection result of the inspection object, and reading the defect coordinates, object layer, defect type and other information of the defect pattern;

Step S6: According to the configuration number of the defect risk unit and the corresponding basic unit and the configuration number of the dummy unit, the defect patterns corresponding to the unit with a large number of configurations in the defect risk unit are ranked by importance, wherein the configuration The higher the number, the higher the ranking of importance.

Further, the priority ranking method of the defect pattern of the detection target further includes step S7, according to the ranking result of the importance degree, determining the higher importance degree as the higher detection priority as the candidate defect pattern The priority detection pattern in the, and then, the priority detection pattern is sequentially detected.

Further, the method for prioritizing the candidate defect patterns of the detection target further includes step S8, when the number of configurations of the basic unit and the dummy unit affected by the defect pattern that are configured in the original design layout data reaches a predetermined value. When the quantity or exceeds the predetermined quantity, a correction alarm will be output.

In addition, in the embodiment of the present invention, a computer-readable medium is also provided for a computer-executable prioritization program for detecting object defect patterns, which is installed and run on a computer, and the computer executes the following programs:

Receiving the original design layout data and reading the object layer information, where the object layer information includes at least the object layer structure and the object layer layout coordinates;

For the original design layout data with a multi-level structure, extract the types of basic units of basic functions and specific functions included in each layer and the number of configurations of each basic unit; for the original design layout data without a hierarchical structure Data, extracting the number of configurations of basic and specific functional pseudo-units included in a single object layer and the number of configurations of repeated layout pattern combinations, where the repeated layout pattern combination is formed by including at least two pseudo-units with the same coordinate positional relationship Unit combination, and repeat the pattern combination to form a new pseudo unit, obtain the configuration number of the pseudo unit in the original design layout data, and record the configuration number of the basic unit and the pseudo unit;

Receiving the defect pattern from the defect inspection result of the inspection object, and reading the defect coordinates, object layer, defect type and other information of the defect pattern;

According to the defect pattern output from the semiconductor inspection device, for the original design layout data of the multi-level structure, it is determined in turn whether the corresponding defect pattern is affected by each of the basic unit location areas, and if so, the corresponding defect pattern is identified. The basic unit is a basic unit affected by a defective pattern; for the original design layout data that does not have a hierarchical structure, it is determined in turn whether each dummy unit location area has the corresponding defective pattern influence, and if so, it is marked The dummy cell is a dummy cell affected by the defect pattern, and the cell existing at the position where the defect overlaps is determined as a defect risk cell; and

In the embodiment of the present invention, the computer-readable medium used to store the priority ranking program of the defect pattern of the detection target determines the higher priority as the higher priority according to the priority ranking result. Higher defect patterns start to be detected sequentially, where the more the number of configurations, the higher the priority ranking.

In the embodiment of the present invention, the computer-readable medium used to store the priority ranking program of the defect pattern of the detection target also executes the following program. When the basic unit and the dummy unit affected by the defect pattern are configured When the number of configurations in the original design layout data reaches the predetermined number or exceeds the predetermined number, a correction alarm is output.

The above are only the preferred embodiments of the present invention, and the described embodiments are not used to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the same reasoning. Within the protection scope of the appended claims of the present invention.

Claims

A device for prioritizing defect patterns of a detection object, the detection object being composed of at least one basic unit or at least one pseudo unit; characterized by comprising:

Defect inspection result reading module, used to read the defect pattern of the inspection object;

The defect detection result analysis module receives the defect pattern sent by the defect detection result reading module, and reads the defect pattern information. The defect pattern information includes at least the defect coordinates of the defect pattern, the defect target layer, and the defect type ；

The layout data reading module receives the original design layout data of the inspection object;

The layout data analysis module reads the structure and layout coordinates of the defect object layer in the original layout data;

The layout data unit analysis module, for the original design layout data with a multi-level structure, extracts the types of basic units of the basic functions and specific functions included in each object layer and the number of configurations of each basic unit; The constructed original design layout data extracts the number of configurations of basic functions and specific function pseudo-units included in a single object layer and the number of combinations of repeated layout patterns, wherein the combination of repeated layout patterns includes at least two coordinate positional relationships The unit combination formed by the same pseudo unit is combined into a new pseudo unit with a repeating pattern combination, the number of configurations of all pseudo units configured in the original design layout data is obtained, and the configuration of all basic units and pseudo units is recorded number;

The data processing analysis module, based on the defect pattern of the inspection object, for the original design layout data of the multi-level structure, sequentially determines whether each of the basic unit location areas has a corresponding defect pattern influence, and if so, then mark The basic unit is a basic unit affected by a defective pattern; for the original design layout data that does not have a hierarchical structure, it is determined in turn whether there is a corresponding defective pattern influence in each of the pseudo-unit location areas, and if so, it is marked The dummy unit is a dummy unit affected by a defective pattern; and the basic unit and the dummy unit affected by the defective pattern are determined as a defect risk unit;

The defect location importance determination module, according to the defect risk unit output by the data processing analysis module and the configuration number of the basic unit and the configuration number of the pseudo unit output by the corresponding layout data unit analysis module, divide the and The defect patterns corresponding to the cells with a large number of configurations are ranked in importance, wherein the more the number of configurations, the higher the ranking of the importance.
The device for prioritizing detection target defect patterns according to claim 1, characterized in that, according to the ranking result of the importance degree, the higher degree of importance is determined as the higher detection priority, and the defect with higher priority is selected from the higher priority. The patterns begin to be tested in sequence.
The prioritizing device for detecting object defect patterns according to claim 1, further comprising a storage module, connected to the data processing analysis module, for storing all the defect patterns and the defect risk unit And the importance.
The device for prioritizing the defect pattern of a detection target according to claim 1, further comprising a correction alarm module, for each basic unit and pseudo unit constituting the defect risk unit, when it is configured in the original design When the number of configurations in the layout data reaches a predetermined number or exceeds a predetermined number, the correction alarm module gives an alarm.
A method for prioritizing defect patterns of a detection object, the detection object being composed of at least one basic unit or at least one pseudo unit; characterized in that it comprises the following steps:

Receive the original design layout data of the test object when designing;

Reading the object layer information of the original design layout data, the object layer information includes at least an object layer structure and object layer layout coordinates; the object layer structure includes a multi-level structure and a structure that does not have a hierarchical structure;

For the original design layout data with a multi-level structure, extract the types of basic units of basic functions and specific functions included in each layer and the number of configurations of each basic unit; for the original design layout data without a hierarchical structure Data, extracting the number of configurations of basic and specific functional pseudo-units included in a single object layer and the number of configurations of repeated layout pattern combinations, where the repeated layout pattern combination is formed by including at least two pseudo-units with the same coordinate positional relationship Unit combination, and repeat pattern combination to form a new pseudo unit, obtain the configuration number of all pseudo units configured in the original design layout data, and record the configuration number of all basic units and pseudo units;

Receiving the defect pattern from the defect inspection result of the inspection object, and reading the defect coordinates, the target layer and the defect type of the defect pattern;

According to the defect pattern output from the semiconductor inspection device, for the original design layout data of the multi-level structure, it is determined in turn whether there is a corresponding defect pattern influence in each of the basic unit location areas, and if so, the The basic unit is the basic unit affected by the defective pattern; for the original design layout data that does not have a hierarchical structure, it is determined in turn whether there is a corresponding defective pattern influence in each of the pseudo-unit location areas, and if so, it is marked The dummy unit is a dummy unit affected by a defective pattern; and the basic unit and the dummy unit affected by the defective pattern are determined as defect risk units; and

According to the configuration number of the defect risk unit and the corresponding basic unit and the configuration number of the pseudo unit, the defect patterns corresponding to the unit with the larger configuration number in the defect risk unit are ranked in importance, wherein the more the configuration number is , The higher the importance ranking.
The method for prioritizing detection object defect patterns according to claim 5, characterized in that it further comprises determining, according to the ranking result of the importance degree, the higher importance degree as the higher detection priority, and the higher priority The defect patterns start to be inspected one after the other.
The method for prioritizing the defect pattern of a detection target according to claim 6, further comprising, for each basic unit and pseudo unit constituting the defect risk unit, when it is configured in the original design layout data When the number of configurations in the file reaches the predetermined number or exceeds the predetermined number, a correction alarm is output.
A computer-readable medium for storing a computer-executable priority ranking program for detecting object defect patterns, which is installed and run in a computer, and is characterized in that the computer executes the following programs:

Receive the original design layout data made during the design of the inspection object;

Receiving the original design layout data and reading the object layer information of the original design layout data, where the object layer information includes at least the object layer structure and the object layer layout coordinates;

For the original design layout data with a multi-level structure, extract the types of basic units of basic functions and specific functions included in each layer and the number of configurations of each basic unit; for the original design layout data without a hierarchical structure Data, extracting the number of configurations of basic and specific functional pseudo-units included in a single object layer and the number of configurations of repeated layout pattern combinations, where the repeated layout pattern combination is formed by including at least two pseudo-units with the same coordinate positional relationship Unit combination, and repeat the pattern combination to form a new pseudo unit, extract the configuration number of all pseudo units in the original design layout data, and record the configuration number of all basic units and pseudo units;

Receiving the defect pattern from the defect inspection result of the inspection object, and reading the defect coordinates, the defect object layer and the defect type of the defect pattern;

According to the defect pattern output from the semiconductor inspection device, for the original design layout data of the multi-level structure, it is determined in turn whether the corresponding defect pattern is affected by each of the basic unit location areas, and if so, it is marked The basic unit is a basic unit affected by defect information; for the original design layout data that does not have a hierarchical structure, it is determined in turn whether each dummy unit location area has the corresponding defect pattern influence, if so, Identify the dummy unit as a dummy unit affected by defect information; and determine the basic unit and the dummy unit affected by the defective pattern as defect risk units;

According to the configuration number of the defect risk unit and the corresponding basic unit and the configuration number of the pseudo unit, the defect patterns corresponding to the unit with the larger configuration number in the defect risk unit are ranked in importance, wherein the more the configuration number is , The higher the importance ranking.
The computer-readable medium according to claim 8, wherein the program executed by the computer further comprises: according to the corresponding defect pattern affecting the detection importance ranking result, judging the higher detection importance as the higher priority. High, starting from the defect pattern with higher priority to detect in sequence.
The computer-readable medium according to claim 9, wherein the program executed by the computer further comprises: for each basic unit and pseudo unit constituting the defect risk unit, when it is configured in the original design layout When the number of configurations in the data reaches the predetermined number or exceeds the predetermined number, a correction alarm is output.