CN109616426A - Intelligent defect correcting system and its implementation method - Google Patents
Intelligent defect correcting system and its implementation method Download PDFInfo
- Publication number
- CN109616426A CN109616426A CN201711086885.1A CN201711086885A CN109616426A CN 109616426 A CN109616426 A CN 109616426A CN 201711086885 A CN201711086885 A CN 201711086885A CN 109616426 A CN109616426 A CN 109616426A
- Authority
- CN
- China
- Prior art keywords
- defect
- coordinate
- image
- data processing
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007547 defect Effects 0.000 title claims abstract description 1336
- 238000000034 method Methods 0.000 title claims abstract description 75
- 238000013461 design Methods 0.000 claims abstract description 315
- 238000012937 correction Methods 0.000 claims abstract description 176
- 238000004458 analytical method Methods 0.000 claims abstract description 100
- 230000002950 deficient Effects 0.000 claims abstract description 70
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 claims abstract description 48
- 241001269238 Data Species 0.000 claims abstract description 16
- 238000012545 processing Methods 0.000 claims description 250
- 238000003860 storage Methods 0.000 claims description 133
- 239000013078 crystal Substances 0.000 claims description 49
- 238000006243 chemical reaction Methods 0.000 claims description 44
- 238000005070 sampling Methods 0.000 claims description 40
- 238000001514 detection method Methods 0.000 claims description 32
- 230000009471 action Effects 0.000 claims description 14
- 239000004744 fabric Substances 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 10
- 238000007619 statistical method Methods 0.000 claims description 5
- 241000208340 Araliaceae Species 0.000 claims description 3
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims description 3
- 235000003140 Panax quinquefolius Nutrition 0.000 claims description 3
- 235000008434 ginseng Nutrition 0.000 claims description 3
- 238000001878 scanning electron micrograph Methods 0.000 claims 1
- 230000009885 systemic effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 abstract description 13
- 230000004069 differentiation Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 60
- 230000008569 process Effects 0.000 description 25
- 230000009395 genetic defect Effects 0.000 description 22
- 230000003287 optical effect Effects 0.000 description 20
- 231100001160 nonlethal Toxicity 0.000 description 13
- 238000011160 research Methods 0.000 description 10
- 230000009897 systematic effect Effects 0.000 description 10
- 239000003550 marker Substances 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000009466 transformation Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000013507 mapping Methods 0.000 description 3
- 238000013179 statistical model Methods 0.000 description 3
- 241000196324 Embryophyta Species 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 238000000399 optical microscopy Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- GJJFMKBJSRMPLA-HIFRSBDPSA-N (1R,2S)-2-(aminomethyl)-N,N-diethyl-1-phenyl-1-cyclopropanecarboxamide Chemical compound C=1C=CC=CC=1[C@@]1(C(=O)N(CC)CC)C[C@@H]1CN GJJFMKBJSRMPLA-HIFRSBDPSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 etching Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 231100000640 hair analysis Toxicity 0.000 description 1
- 238000003703 image analysis method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
- 238000000386 microscopy Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000010223 real-time analysis Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The present invention provides the system and its implementation method of a kind of intelligent semiconductor defect correction, its method includes: the multiple defective datas for receiving manufacturing works and sending out, receive the ic design layout diagram data of an IC design company, and after carrying out defect coordinate translational correction and defect adjustment of image to multiple defective datas, with key area analysis come the defective data and design layout figure after analysis correction, to promote the accuracy of key area analysis and use the critical defect index for precisely judging that each defect image causes open circuit or short circuit type failure；Further according to critical defect index and defect signal parameter, differentiation critical defect is high risk defect, risk defect and low-risk defect etc., reaches and promotes intelligent defect correcting system and its implementation method accuracy and the accurate purpose for differentiating critical defect.
Description
Technical field
System of the present invention is related to a kind of intelligent semiconductor defect correction, classification and the system and its implementation method sampled；
It is applied to semiconductor fabrication factory, semiconductor packages manufactory, flat-panel screens manufacturing works, solar energy more particularly to one kind
Plate manufacturing works, printed circuit manufacturing works, light shield manufacturing works, LED manufacture or assembly plant intelligent defect correction,
The system and its implementation method of classification and sampling.
Background technique
In general, being produced in factory, manufacturing integrated circuit (Integrated Circuit；It IC), is through light
Equipment and the processing procedures such as cover, photolithography in semiconductor, etching, film deposition, copper wiring, chemical mechanical grinding and multiple-exposure and formed.
Therefore, during entire manufacture, the particle that may be generated due to the accuracy error, abnormal failure, processing procedure of equipment itself is set
The drawing flaw and yellow light process window (window) of meter layout are insufficient and generate randomness defect and systematic defect
(Random and systematic defect), these defects cause product breaking (open) or short-circuit (short) type failure,
Reduce wafer yield.These randomness defects and systematic defect, as manufacture of semiconductor size is miniature down, defects count is also
It is increased significantly because of size reduction, so that defects detection obtains thousands of, tens of thousands of a defects every time, it is aobvious because being limited to scanning electron
The photographic speed , Only of micro mirror (Scanning Electron Microscope, SEM) can be chosen tens of to hundreds of with sampling mode
A defect goes to take a picture, and causes to be sampled to the really defect degree of difficulty of meeting open circuit or short circuit type failure and greatly improves, thus can not be quasi-
Really and in real time providing these causes the defect SEM photograph of yield consume to process engineers, and then is difficult to be shone according to the SEM of defect
Piece leads to the source of defect to analyze in processing procedure, therefore the effect for improving defect yield is bad, increases the cost of semiconductor factory.
In the practice running of semiconductor factory (such as: wafer foundry, Foundry), in the past with real-time (real-time)
Defect and image pattern classification data analysis, be to promote the important method of yield in the past, but this method is in nanometer grade half
The defect analysis of conductor processing procedure has been difficult to find the critical defect of failure；The core part of the innovation introduces ic design layout figure
Data, key area analyze (Critical Area Analysis, CAA) method, defect pattern overlapping design layout, coordinate
Translational correction system and flaw size correct system, are the important breakthrough method and system for solving sampling critical defect.
Furthermore the defective data generated by the image graph outline metric data and detection board of SEM and optical microscopy,
It makes comparisons with key area analysis data, detects flaw size, area data and the SEM of board and the striograph of optical microscopy
It is variant that shape profile measures size, area data, thus causes key area analysis result variant, to solve key area point
Analyse deviation, it is necessary to solve flaw size offset issue.Such as: the flaw size of defect checking machine platform measures unit when higher than layout
Figure minimum dimension causes the offset issue of the size of defect data and the actual defects size of SEM photograph.
In addition, in complicated miniature semiconductor advanced process, especially as optical effect process window (process
Window) more and more narrow, but when ic design layout figure is increased and complicated with more multiples, cause some related with figure
Defect be detected, wherein belonging to, to will affect the defect of yield be " systematic defect ", it will cause extremely low yield,
But if this figure be do not influence IC designed lines, such as: monitoring pattern because not influencing yield, be belong to " it is false lack
Fall into " (False defect), but because of spurious defects figure and signal it is obvious that often occupying most defect sampling number ratio
Example can not really find the defective patterns of open circuit or short circuit type failure to 90% or more instead.
Finally, defect sample part, in addition to same inventor 2012 check and approve patent No. US8312401B2,
The design layout in its flaw size size of each defect and its grid deviation range areas is obtained with key area analysis method
The key area of pattern calculates the probit value of the defect of open circuit or short circuit type failure, is critical defect index (Killer
Defect Index, KDI), that is, CAA value；However, when calculating critical defect index (KDI), not by defect inspection machine
The control motor precision of platform carrying wafer is taken into account, such as: the coordinate when the mobile wafer of a defect checking machine platform is accurate
Spend unit control be positive and negative W, such as W be equal to 0.05 micron when, therefore, can be detected out having a size of positive and negative 0.05 micron
Multiple；Therefore the size value that may cause the defect image detected is greater than actual size, and it is inclined to may cause critical defect index
The problems such as high.
Therefore, based on the consideration in above-mentioned multiple technologies level, above-mentioned many restrictions how are overcome, to be promoted and be improved
The volume production efficiency of manufacturing works is the target that one skilled in the art makes great efforts.
Summary of the invention
Present invention is primarily aimed at ic design layout figure and key area analysis method is used, for defect checking machine platform
Caused deviation, input coordinate corrects the correction factor (Calibration factor) of threshold values and flaw size, real
When corrective pitting detection board defective data content coordinate and flaw size deviation, in conjunction with ic design layout number
According to, multiple defective patterns are overlapped one by one to multiple defect layout patterns of correspondence, reuse key area analysis method acquirement
Critical defect index (KDI).The present invention is using the coordinate and defect layout graph of accurate adjustment and in conjunction with more high accuracy
Flaw size value, therefore can produce more accurately critical defect index, so that in analysis open circuit or the probability of short circuit type failure defect
When, more accurately and erroneous judgement can be reduced, become and differentiate that each defect belongs to non-lethal defect (Non-killer defect)
Or the important tool of critical defect (Killer defect).
According to above-mentioned purpose, the present invention provides a kind of defect correcting system of semiconductor crystal wafer, including storage device, brilliant
Circle manufacture board group, wafer defect detect board and data processing equipment, and wherein storage device is to store IC design
Map file case, and plurality of lines is configured in IC design map file case, wafer manufactures board group, to set integrated circuit
Those line configurings in map file case are counted on wafer, wafer defect detection board obtains Defect Scanning number to scanning wafer
According to, data processing equipment by Defect Scanning data conversion at defect text and image data file and being stored in storage dress
It sets, it is characterised in that: data processing equipment captures an amendment threshold values, is that amendment threshold values is captured from storage device, wherein repair
Positive threshold values is to convert each defect image coordinate to the relative coordinate position on the deviation range region of defect layout patterns
Amendment statistical value, amendment threshold values include the average coordinates accuracy value of X-axis and Y-axis and the standard deviation value of coordinate precision；Data
Processing unit executes a correction program, is according to amendment threshold values, by the inclined of each defect video conversion to defect layout patterns
On the amendment threshold values coordinate of poor range areas, and store into storage device.
According to above-mentioned purpose, the present invention then provides a kind of defect correcting system of semiconductor crystal wafer, including storage dress
It sets, wafer manufactures board group, and wafer defect detects board and data processing equipment, and wherein storage device is to store integrated circuit
Design drawing archives, and plurality of lines is configured in IC design map file case, wafer manufactures board group to by integrated electricity
For those line configurings in the design drawing archives of road on wafer, wafer defect detects board to scan the wafer to obtain defect
Scan data, data processing equipment deposit Defect Scanning data conversion at defect text and image data file and being stored in
Storage device, it is characterised in that: data processing equipment captures an amendment threshold values, is stored in storage device, wherein amendment valve
Value is that semiconductor factory converts to the relative coordinate on the deviation range region of defect layout patterns each defect image coordinate
The amendment statistical value of position, and correcting threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation of coordinate precision
Value；Data processing equipment executes a correction program, is according to amendment threshold values, by each defect video conversion to defect layout
On the amendment threshold values coordinate in the deviation range region of case, and store into storage device；Data processing equipment obtains a correction
The factor is that in defect image and lteral data file while will have flaw size and defect area and SEM flaw size and lack
These defects for falling into area are compared, and use and count correction factor；Data processing equipment executes flaw size correction, is
After each of defect image data file flaw size is multiplied by correction factor, the flaw size after correction is stored to depositing
In storage device；Data processing equipment executes the first overlapping program, is the defect ruler after the correction of acquisition defect image pattern one by one
Very little and defect area, and the flaw size after correction is overlapped with defect area to the offset of the IC design layout pattern
On the amendment threshold values coordinate of range areas；Execute key area analysis, be by data processing equipment according to the flaw size and lack
It falls into area to overlap on IC design layout pattern, obtains each defect in grid deviation using key area analysis method
The key area of design layout pattern in range areas judges a fatal defect index value.
Another object of the present invention is coordinate translational correction system of the invention, flaw size correction system and embodiment party
Method promotes key area accuracy of analysis and precisely differentiates critical defect.Applied defect detect board genetic defects data and
Ic design layout data input grid deviation corrected value by coordinate translational correction system, it can reduce silicon wafer process light
Effect is learned rectangular figures are exposed figure in the arc-shaped and convert defect coordinate to coordinate produced by practical layout figure coordinate
Deviation；The correction system, statistical method and measurement analysis on Uncertainty for importing flaw size simultaneously, by the original of defect checking machine platform
Beginning defective data is corrected to approximate defect image contour size, is solved because the measurement unit of defect checking machine platform is higher than layout
Shape minimum dimension, the size of caused defect data, the actual defects size of area and SEM photograph, the deviation of area are promoted and are closed
Key range accuracy of analysis and the accuracy for differentiating critical defect analysis.
According to above-mentioned purpose, the present invention provides a kind of defect correcting system of semiconductor crystal wafer, including storage device, brilliant
Circle manufacture board group, wafer defect detect board and data processing equipment, and wherein storage device is to store IC design
Map file case, and plurality of lines is configured in IC design map file case, wafer manufactures board group, to set integrated circuit
Those line configurings in map file case are counted on wafer, wafer defect detection board obtains Defect Scanning number to scanning wafer
According to, data processing equipment by Defect Scanning data conversion at defect text and image data file and being stored in storage dress
It sets, it is characterised in that: data processing equipment obtains IC design map file case, to pick out in IC design map file
The opposite coordinate position of each route in case, the distance between a line width of each route and every two lines road；Number
According to processing unit by capturing an at least defect coordinate in defect text and image data file one by one, an at least flaw size with extremely
A few defect area, and it is every to IC design map file case according to defect coordinate flaw size and defect area to be overlapped
On the opposite coordinate position of one route；Data processing equipment overlaps according to flaw size and defect area and sets in integrated circuit
It counts in map file case, obtains design layout pattern of each defect in grid deviation range areas using key area analysis method
Key area, judge at least one critical defect index value；Data processing equipment selects at least one fatal defect index value,
And each defective locations where the critical defect index value being chosen to are rescaned to obtain using scanning means
The new defect area after new flaw size and scanning after scanning and being somebody's turn to do by those new flaw sizes after scanning and after scanning
A little defect areas are separately stored in storage device；And after data processing equipment is to judge flaw size and scanning after scanning
Defect area whether be an open type or a short circuit type system defect.
According to above-mentioned purpose, the present invention provides a kind of defect correcting system of semiconductor crystal wafer, including storage device again,
Wafer manufactures board group, and wafer defect detects board and data processing equipment, and wherein storage device is set to store integrated circuit
Map file case is counted, and is configured with plurality of lines in the IC design map file case, which manufactures board group, will integrate
For those line configurings in circuit design drawing archives on wafer, wafer defect detects board to scanning wafer to obtain defect
Scan data, data processing equipment deposit Defect Scanning data conversion at defect text and image data file and being stored in
Storage device, it is characterised in that: data processing equipment obtain IC design layout map file case, to pick out coordinate origin,
Each route is with respect to the distance between the position of a coordinate, line width and route；Data processing equipment executes the first coordinate and turns
Program is changed, is the defect coordinate (X for obtaining defect image pattern from defect text and image data file1,Y1), and according to scarce
Sunken coordinate is converted to the opposite first coordinate (X of IC design layout pattern2,Y2)；Data processing equipment executes the first coordinate
Correction program a, comprising: indicator screen is provided, is to obtain one according to the coordinate position of defect image by data processing equipment
The image file of defect image near zone, while defect image is obtained in the IC design cloth by data processing equipment again
Office schemes the route archives of corresponding coordinate position near zone, and by defect image near zone image file and associated disadvantages shadow
As the route archives of the coordinate position near zone in IC design layout figure are shown on indicator screen together；Mark
One second coordinate is by the defect image position on defect image near zone image file in IC design layout figure phase
It answers and indicates the second coordinate (X on the route archives of defect image coordinate position near zone2’,Y2')；Seat after obtaining a correction
Mark is as the first coordinate (X on IC design layout figure2,Y2) and the second coordinate (X2’,Y2') not in same coordinate bit
Coordinate (X when setting, after the correction can be obtained2’-X2,Y2’-Y2)。
Another object of the present invention is that the defect provided based on design layout data and key area analysis method takes
Quadrat method.This system and method combination key area analysis method obtain the selection that critical defect index is the sampling of main defect
Judge parameter, plus defect intensity value/reduced value/polarity check value in image analysis methods analyzing defect image figure for
Method judges the selection that third defect samples whether the selection of two defects sampling judges parameter and judges spurious defects
Parameter, to provide the most effective method for choosing open circuit or short circuit type failure defect sampling.
According to above-mentioned purpose, the present invention provides a kind of defect correcting system of semiconductor crystal wafer, including storage device again,
Wafer manufactures board group, and wafer defect detects board and data processing equipment, and wherein storage device is set to store integrated circuit
Map file case is counted, and is configured with plurality of lines in the IC design map file case, which manufactures board group, will integrate
For those line configurings in circuit design drawing archives on wafer, wafer defect detects board to scanning wafer to obtain defect
Scan data, data processing equipment deposit Defect Scanning data conversion at defect text and image data file and being stored in
Storage device, it is characterised in that: data processing equipment obtains the IC design layout map file case, to pick out coordinate original
Point, each route are with respect to the distance between the position of a coordinate, line width and route；Data processing equipment executes the first coordinate
Conversion program is to obtain the defect coordinate (X of defect image pattern from defect text and image data file1,Y1), and according to
Defect coordinate is converted to an opposite first coordinate (X of IC design layout pattern2,Y2)；Data processing equipment executes first
Coordinates correction program a, comprising: indicator screen is provided, is to be obtained by data processing equipment according to the coordinate position of defect image
The image file of one defect image near zone, while defect image is obtained in IC design by data processing centre again
The route archives of the corresponding coordinate position near zone of layout, and by defect image near zone image file and associated disadvantages
Image is shown on indicator screen together in the route archives of the coordinate position near zone of IC design layout figure；Mark
Show one second coordinate, is by the defect image position on defect image near zone image file in IC design layout figure
Mutually second coordinate (X should be indicated on the route archives of defect image coordinate position near zone2’,Y2')；After obtaining correction
Coordinate is as the first coordinate (X on IC design layout figure2,Y2) and the second coordinate (X2’,Y2') not in same coordinate
Coordinate (X when position, after correction can be obtained2’-X2,Y2’-Y2)；Data processing equipment executes the first overlapping program, is from scarce
It falls into text and image data file, captures the flaw size and defect area of defect image pattern one by one, and by flaw size
It overlaps with defect area to the coordinate (X after the correction of IC design layout pattern2’-X2,Y2’-Y2)；Data processing equipment
The analysis of the first key area is executed, is to be overlapped on IC design layout pattern according to flaw size and defect area, makes
The key area of design layout pattern of each defect in grid deviation range areas is obtained with key area analysis method, is sentenced
A disconnected fatal defect index value out；Data processing equipment executes a correction program, comprising: selects at least one critical defect index
Value；One SEM scanning machine is provided, and each defective locations where the critical defect index value selected are rescaned, with
Accurately flaw size and a defect area relatively is obtained, and is stored into storage device；The second overlapping program is executed, is by counting
Accurately flaw size and defect area relatively are captured according to processing unit, and will accurately defect area relatively according to defect coordinate
It overlaps to a relative coordinate of IC design layout pattern；The analysis of the second key area is executed, is filled by data processing
It sets that accurately flaw size and defect area overlap on the IC design layout pattern relatively according to this, uses key area
Domain analysis method obtains the key area of design layout pattern of each defect in grid deviation range areas, judges a school
Critical defect index value after just, wherein the critical defect index value distinguishes multiple and different numerical value.
Detailed description of the invention
Fig. 1 is the operational architecture schematic diagram of intelligent defect correction of the invention, classification and sampling system.
Fig. 2 is the flow chart of " intelligence system " of the invention.
Fig. 3 A is the schematic diagram that " intelligence system " of the invention obtains design layout figure.
Fig. 3 B is the schematic diagram that " intelligence system " of the invention obtains defective data.
Fig. 3 C is the schematic diagram of " intelligence system " design layout figure and defective data coordinate conversion of the invention.
Fig. 4 is defect of the invention to the coordinate conversion of design layout figure and the correcting process figure of drift correction.
Fig. 5 is the coordinate flow path switch figure of size adjusting of the invention.
Fig. 6 A, Fig. 6 B, Fig. 6 C to Fig. 6 D are that the present invention provides multiple embodiments signal of accurate coordinates deviation correcting value
Figure.
Fig. 7 A to Fig. 7 E is that the present invention captures defect profile and overlaps more to the defect coordinate position on design layout figure
A embodiment schematic diagram.
Fig. 8 A and Fig. 8 B is the flow chart for the correction system that the present invention establishes flaw size, area.
Fig. 8 C, the flaw size after being defect image file correction of the genetic defects size of the present invention by high resolution
Table.
Fig. 9 is that the present invention executes defect profile and the polygon pattern of layout patterns compares the flow chart analyzed.
Figure 10 is defect classification process figure of the invention.
Figure 11 A-11G is defective patterns database of the invention.
Step 110 is to step 190
Step 200
Step 300
Step 500
Wafer 10
Chip layout 11
Crystal grain 11D
Wafer foundry 20
Data processing centre 21
Internal storage location 23
Antenna 24
Antenna 34
IC design company 30
Data processing centre 31
Internal storage location 33
Indicator screen 51
Defect pattern 1001
Defect image 1101
Route 1102
Defect image 1103
Corrective pitting image 1104
Correct polygon defect image 1105
Design layout pattern 1110
Defect 1101
Defect layout patterns 1111
Route 1113
Defect text and image data file 1130.
Specific embodiment
Work is manufactured in semiconductor fabrication factory, semiconductor packages manufactory, flat-panel screens manufacturing works, solar panels
In factory, printed circuit manufacturing works, light shield manufacturing works, LED manufacture or assembly plant, it is required to through light shield, semiconductor microactuator
Equipment and the manufacturing method thereofs such as shadow, etching and film deposition form the product with particular functionality；Due in manufacturing process
Many complicated steps, it is good that control, device parameter deviation or the technical bottleneck of processing procedure and device parameter impact product
The defect of rate, the generation of these defects are inevasible.Therefore, semiconductor factory in the fabrication process, can execute defect
Detection and analysis promote yield and reduce cost.
Firstly, referring to Fig. 1, being that the operational architecture of intelligent defect correction of the invention, classification and sampling system shows
It is intended to.As shown in Figure 1, the embodiment of the present invention will illustrate so that wafer manufactures as an example, meanwhile, during the following description,
" intelligent defect correcting system and its implementation method " will be replaced with " intelligence system ".For on the whole, intelligence system can
To execute in the wafer foundry 20 (hereinafter referred to as factory end 20), can also IC design company 30 (hereinafter referred to as
Chevron Research Company (CRC) end 30) in execute, it is of course also possible to be by factory 20 and Chevron Research Company (CRC) end 30 through cable network or via
Antenna 24/34 and wireless network execute.
For example, when Chevron Research Company (CRC) end 30 completes the integrated circuit ic design layout figure (IC with specific function
Design layout) after, data processing centre 31 can first store GDS the or OASIS archives of design layout figure to internal storage location
In 33；Then, GDS or OASIS archives can be passed into factory end 20 through cable network or wireless network；Wherein, if
It counts in layout patterns 1110 (being shown in Fig. 3 A) comprising many a layout patterns (such as: the layout of component), and each layout
Figure polygon includes layout size, layout coordinate, layout figure layer (Layer), word indicating or size；It is general and
Speech, the format (format) of design layout pattern 1110 can be image database system (Graphic Database
System, GDS) format, GDS-II format or open access information system (Open Access Same-time simultaneously
Information System, OASIS) format.Then, received archives can be passed through data processing centre by factory end 20
After 21 processing, store into internal storage location 23.Later, factory end 20 can the light shield according to manufactured by design layout pattern 1110
Related semiconductor processing procedure is carried out, producing many duplicate crystal grain 11D (being shown in Fig. 3 B) on wafer 10.In general,
Factory end 20 can use the archives at Chevron Research Company (CRC) end 30 when carrying out semiconductor chip manufacture.
During wafer 10 manufactures, defect can generate on wafer 10 in each processing procedure of manufacture, such as: it is random
Property defect (random defect) or systematic defect (systematic defect) etc..Therefore, factory end 20 is manufacturing
On any stage in the process or multiple fabrication steps, defect checking machine platform can be all used, such as: scanning electron microscope
(SEM), electron beam (E-beam) detection board, optical detection board, Defect Scanning instrument or camera etc., to these wafers 10
Defect Scanning and detection are carried out, and produces the genetic defects scan data of wafer；These Defect Scanning datagrams include: defect
Size, shape, area, die locations, coordinate or figure etc.), and these defective datas can pass through data processing centre 21
It is processed into the defect text and image data file 1130 (being shown in Fig. 3 B) of JPG, TIFF, PNG and plain text (text) specification
Afterwards, storage is into internal storage location 23.
According to above-mentioned, it is evident that stored the design at Chevron Research Company (CRC) end 30 in the internal storage location 23 at factory end 20
Layout archives 1110 and defect text and image data file 1130.Therefore, " intelligence system " of the invention can be in work
Factory end 20 executes the work such as defect correction, classification and sampling.Likewise, if factory end 20 is by defect text and image data file
After 1130 are transferred to Chevron Research Company (CRC) end 30 through cable network or wireless network, " intelligence system " of the invention can designed
Company end 30 executes the work such as defect correction, classification and sampling.Certainly, factory end 20 can also be real-time with Chevron Research Company (CRC) end 30
By cable network or wireless network by exchange correlation archives, lacked with analyzing (real-time analysis) execution in real time
Fall into the work such as correction, classification and sampling.Whom executes the work such as defect correction, classification and sampling by for above-mentioned, the present invention is simultaneously
It is without restriction.
Then, referring to FIG. 2, being the flow chart of " intelligence system " of the invention.As shown in Fig. 2, " intelligence system " of the invention
Flow chart 100 be to obtain design layout Figure 111 0 by data processing centre 21 and obtain defect text and image data file
1130 start, as shown in step 110 and step 120；Then, the design layout Figure 111 0 and defect that will be obtained by step 130
Text and image data file 1130 carry out coordinate conversion and deviation correction (deviation calibration), to will be brilliant
Defect coordinate position on circle 10 is converted to the corresponding coordinate position of design layout figure, to judge that defect image 1101 can be fallen in
On those of design layout Figure 111 0 coordinate position；Followed by by step 140 by the profile of each defect image
(contour) each for being overlapped (superposition) or being mapped on (mapping) to design layout Figure 111 0 lacks
Fall into the coordinate position of the corresponding defect layout patterns 1111 of image 1101；Then, judge that critical defect refers to by step 150
Number (Killed Defect Index；KDI), wherein critical defect index (KDI) be according to step 140 each overlap or
It is the defect image coordinate position after image, and analyzes (Critical Area Analysis, CAA) further according to key area
The overall size of method analyzing defect image is with the pass on the design layout figure in defective locations and its deviation range area
Key range (Critical Area) judges；It is also possible to checked by step 160 profile of defect image at least
Two layout patterns overlap as a result, and checking the result that the profile of defect image is intersected at least one layout patterns.Later, into
The defect of row step 170 is classified, and is the judging result by step 150 or step 160, according to the critical defect index of defect
(KDI), defect signal parameter (defect signal parameter), defect and defect pattern data file (defect
Pattern library) Graphic Pattern Matching (pattern match) as a result, and defect and high failure frequency defect database
The Graphic Pattern Matching result of (frequent failure defect library) carries out defect classification, wherein defect pattern number
According to file (defect pattern library) and high failure frequency defect database (frequent failure defect
It library) is that (such as step 180) can be obtained from internal storage location 23/33；Or according to layout patterns intersection short circuit or
Breaking result carries out defect classification；It finally, carrying out the sampling of defect by step 190, is classified according to the defect of step 170
And defect sampling rule carries out the sampling of defect.
Followed by the specific embodiment of each step in the flow chart 100 of detailed description " intelligence system ".Firstly,
For the acquirement design layout figure of step 110, the IC design layout mainly completed according to Chevron Research Company (CRC) end 30
Figure 111 0 is handled.Fig. 3 A is please referred to, is the schematic diagram that " intelligence system " of the invention obtains design layout figure.Such as Fig. 3 A institute
Show, and user (such as: the engineer at Chevron Research Company (CRC) end 30) design layout Figure 111 0 is taken out by data processing centre 31 in advance；
Wherein, the format (format) of design layout Figure 111 0 can be GDS format, GDS-II format or OASIS format.
Then, Fig. 3 B is please referred to, is the schematic diagram that " intelligence system " of the invention obtains defective data.As previously mentioned, setting
Meter layout patterns 1110 via 30 complete design of Chevron Research Company (CRC) end and are supplied to factory end 20, factory end 20 in manufacturing process,
The pattern with complete chip layout (full-chip layout) 11 can be formed on wafer 10, and complete chip is laid out
Include in 11 a plurality of crystal grain (die), such as: 11D 1,11D 2,11D 3.Then, factory end 20 uses fault detection board
Defect Scanning detection is carried out to wafer 10, to obtain the archives of the complex defect image 1101 on chip layout 11 and lack
Fall into lteral data；Later, it is captured by data processing centre 21 and calculates one or multiple defect images 1101 and generated in crystalline substance
Which crystal grain on circle 10 and those of it is located on crystal grain on position.
Then, as shown in Figure 3B, data processing centre 21 obtains each defect coordinate of wafer 10 (X1,Y1) and obtain scarce
The image file 1001 and the route 1102 on image file 1001 for falling into image 1101.Please continue to refer to Fig. 3 B, it is shown in crystalline substance
On a crystal grain 11 in multiple crystal grain on circle 10, amounting to detection has 7 defect images 1101 to generate, data processing centre 21
According to defect image coordinate (X1,Y1) it is the first reference origin coordinate (X relative to crystal grain 1101,Y01)；Such as: the first reference
Origin (X01,Y01) it is usual first reference origin coordinate produced by the input program (recipe) by defect checking machine platform
(X01,Y01) corner or the identifying position that is easily found of the selection in crystal grain 11, using as label (marker), to this this hair
It is bright and without restriction.Finally, after obtaining text and the image file case of each defect by data processing centre 21, then with crystalline substance
Circle 10 comes as defect text and image data file 1130, wherein in defect text and image data file 1130, records
The content of each defect image 1101 includes the number of crystal grain 11 and the serial number (identification of defect image 1101
Number), name of product, defect manufacturing step, lot number, defect checking machine platform number, defect coordinate (X1,Y1) and rough lack
Fall into image size (including: the full-size of X-direction and the full-size of Y-direction) etc..Finally, all can be by defect text and image
Data file 1130 is stored in internal storage location 23.
Then, the conversion of defective data coordinate and drift correction of step 130 are carried out.Fig. 3 C is please referred to, is the present invention " intelligence
System " design layout figure and the schematic diagram of defective data coordinate conversion.As shown in Figure 3 C, defect is read by data processing centre 21
Each of text and data file 1130 defect image 1101 is located at the defect coordinate (X on crystal grain 111,Y1) after, by number
After being handled according to processing center 21, such as: data processing centre 21 is according to defect coordinate in defect text and data file 1130
(X1,Y1), after coordinate is converted, opposite defect image 1101 can be found out according to reference coordinate on design layout pattern 1110 and is existed
Defect coordinate (X on the defects of design layout pattern 1110 layout patterns 11112,Y2), if Fig. 3 C is defect serial number 1~7
On 7 defect images 1101 conversion to defect layout patterns 1111 relatively on defect coordinate (X21,Y22) to defect coordinate
(X27,Y27).And the size of defect layout patterns 1111, then it is the precision or deviation range according to defect checking machine platform
To determine；Such as: Defect Scanning is carried out when the optical defect for a use of deviation range being -0.5 μm~+0.5 μm detects board
After detection, then the deviation range area of defect cloth layout patterns 1111 is 1 μm x1 μm, wherein in defect layout patterns 1111
Conductor size can be 50nm, and the size distance between conducting wire and another conducting wire can be 30nm.
In addition, by defect coordinate (X1,Y1) convert to the layout coordinate (X on design layout pattern 11102,Y2) position
The purpose set is to want to judge whether this defect image 1101 will cause the defect of open circuit or the short circuit of route 1102.So
And as previously mentioned, the coordinate (X of defect image 11011,Y1) it is that detection board is retouched by defect to measure, reference coordinate may
It is the first reference origin coordinate (X with crystal grain 1101,Y01) centered on；And design layout pattern 1110 then has the reference of oneself former
Point coordinate (X02,Y02), via the reticle data coordinate of reference origin containing layout patterns (X02,Y02) phase with marking layout figure coordinate
To position, when defect checking machine platform selection marquee layout coordinate is reference origin coordinate (X01,Y01), then design layout pattern
Reference origin coordinate (X relative to defect checking machine platform01,Y01) can calculate into coordinate transformation system；In addition, in defect
It, can be arc-shaped because of online 1102 edge of road of the effects such as optical diffraction or corner generation when detecting board measurement wafer 10
(rounding), so that the coordinate (X of defect image 11011,Y1) from right-angle corner there is certain offset distance；And in design layout
Coordinate on Figure 111 0 is then 90 degree orthogonal pattern.It will be apparent that same reference origin coordinate (X01,Y01)
There is certain deviations on wafer 10 and the marking layout figure (marker layout pattern) 1110 of reference origin, this is partially
Difference is shown on the coordinate of the layout patterns after coordinate conversion, and the system that will be corrected by grid deviation draws and corrects.
Furthermore in some cases, the file format of defect image 1101 with design layout Figure 111 0 file format not
Unanimously, such as the file format unit of defect image 1101 is pixel, micron or nanometer etc., and design layout Figure 111 0GDS
File format unit be micron or nanometer etc., between these different file formats, it is also possible to which there is deviations.Therefore, at this
In one preferred embodiment of invention, the program accurately corrected is increased, as shown at step 200.The practical school of step 200
Positive process, referring to FIG. 4, being defect of the invention to the coordinate conversion of design layout figure and the correcting process figure of drift correction.
First to obtain design layout figure and obtain defective data firstly, as shown in the step 110 and step 120 in Fig. 4, process with
Fig. 2 is identical, and so it will not be repeated.Then, step 210 is please referred to, is by defect image file 1001 and design layout Figure 111 0
The size adjusting of the two is at consistent；Such as: it can choose the image file 1001 and design layout figure of defect image 1101
1110 unit sizes are adjusted to unanimously, are the common unit such as pixel unit or micron, nanometer.Later, step could be completed
220, defect image 1101 is correctly converted to design layout Figure 111 0, in this way, the image 1101 that can first overcome one's shortcomings
File format with image file 1001 format of design layout Figure 111 0 it is inconsistent caused by coordinate conversion very large deviation asking
Topic.
Then, in order to enable, defect image converts the coordinate of design layout figure and drift correction is more completely considered
All possible factors for influencing coordinate conversion accuracy are all taken into consideration.Therefore, the present invention further provides preferable implementation
Example, referring to FIG. 5, being the coordinate flow path switch figure of size adjusting of the invention.As shown in figure 5, firstly, step 2110 is to obtain
Defect checking machine platform parameter, such as: the alignment ginseng of defect checking machine platform is obtained into internal storage location 23 by data processing centre 21
Examine the data such as coordinate and size；Or the parameter of design layout Figure 111 0 is obtained by step 2120, and such as: by data processing
Center 21 obtains the original coordinates of design layout Figure 111 0, the alignment data such as reference coordinate and size into internal storage location 23；
And the parameter of light shield (Mask) is obtained by step 2130, and such as: it is obtained by data processing centre 21 into internal storage location 23
The data such as alignment reference coordinate, original coordinates, center point coordinate and the size of light shield parameter.Later, such as step 2140 institute
Show, by the size adjusting of the size of the defect image 1101 of acquirement, the size of design layout Figure 111 0 and light shield manufacture at one
After cause, step 220 could be completed, user must select one or several marker graphics (marker pattern) as setting
The alignment reference coordinate point of defect checking machine platform, wherein marker graphic can be L-type, cross or rectangle etc. and be easy to align with
Simple graph.In typical circumstances, these marker graphics may be placed in Cutting Road (scribe near crystal grain
Line on) rather than on die design layout, light shield (Mask) data contain each label figure on Cutting Road (scribe line)
Shape, design layout figure corner and center point coordinate, therefore this mark point must be calculated to design layout by the parameter of light shield (Mask)
The original coordinates of Figure 111 0 or the distance for being directed at reference coordinate, so that the coordinate of defect coordinate to design layout Figure 111 0 convert system
System can be calculated by above-mentioned relative coordinate relationship and be converted, and the correct defect of image file 1001 of defect image 1101 is sat
Mark (X1,Y1) convert to the coordinate (X on design layout Figure 111 02,Y2).Finally, in the present embodiment, by the place of step 220
After reason, so that it may the amendment for ensuring either to convert from coordinate or image file 1001 and design cloth in defect image 1101
Real-time graph between office Figure 111 0 matches (real time pattern match), is all inclined to carry out with grid deviation data
The amendment of difference, as shown in step 230.
It refer again to Fig. 4, it, can be true after step 220 all corrects the factor of be likely to cause grid deviation
The image file 1001 for recognizing defect image 1101 has been corrected and has converted to the defect layout on design layout pattern 1110
Coordinate (X in pattern 11112,Y2)；It will be apparent that each defect layout patterns 1111 is with different layout patterns and not
Same 1101 pattern of defect image；For example, when 1000 crystal grain 11D can be formed on wafer 10, by defect image 1101
Defect coordinate (X1,Y1) convert to the defect coordinate (X on design layout Figure 111 02,Y2) when, it is possible in each defect
Deviation is formed on layout.Therefore, the present invention is further scarce on layout 1110 to be designed by three kinds of modes are provided
Fall into coordinate (X2,Y2) correction.Firstly, selecting one by data processing centre 21 to internal storage location 23 as shown in step 2410
Defect image 1101；Such as: selection one represents the layout patterns of transistor (Transistor) component；Then, by data
Reason center 21 obtains first defect layout patterns 1111；Followed by obtaining corresponding first assembly by data processing centre 21
After the image file 1001 of defect image 1101, defect layout patterns 1111 and defect are shown on indicator screen 51 together
The image file 1001 of image 1101；In one embodiment, shown defect layout patterns 1111 and defect image 1101
Image file 1001 be tuned into dimensional units it is consistent (such as: be adjusted to pixel unit or micron, nanometer etc.
Unit)；Later, a certain number of comparisons and statistics are carried out on indicator screen 51 in a manual manner by execution correction personnel；
Such as: by execution correction personnel in a manual manner on indicator screen 51 by defect layout patterns 1111 and defect image
1101 image file 1001 is with a setting Coordinates calibration, as shown in the upper half of Fig. 6 A.If showing, conversion to defect is laid out
Defect coordinate position (X on pattern 11112,Y2) with the new coordinate position (X of defect image file 10012’,Y2') position is not
At the same position it is necessary to carrying out correction for drift to new coordinate position (X2’,Y2')；Such as: by correction personnel with side manually
The position of defect image file 1001 location mark opposite on defect layout patterns 1111 is gone out new coordinate position (X by formula2’,
Y2').It will be apparent that 1001 position of defect image file is converted to the actual defects coordinate position on defect layout patterns 1111
(namely grid deviation correcting value) is (X2’-X2,Y2’-Y2), as shown in the lower half of Fig. 6 A.Later, according to aforesaid way according to
Sequence carries out a certain number of grid deviation correcting values, such as: obtain at least 51 grid deviation correcting values；Later, such as step
Shown in 250, is converged by data processing centre 21 and be made into a table and after statistical analysis, available one in X-axis and Y-axis
The standard deviation value of average coordinates accuracy value (Average Coordinate Precision Value) and coordinate precision
The coordinate modification threshold values of (Standard Deviation), as shown in Figure 6 D.In a preferred embodiment, if data processing centre
It when 21 memory size and processor speed is enough fast, is can choose defect layout patterns 1111 and each defect image
After 1101 image file 1001 compares one by one, such as: after comparing 10,000 defect image 1101, obtain one more accurately
Statistical value is as grid deviation correcting value or amendment threshold values, in this regard, the present invention is not limited thereto.Finally, such as step 260
It is shown, it, can be according to obtained seat as grid deviation correcting value or after correcting threshold values obtaining accurately statistical value
It marks accuracy standard deviation and imports coordinate transformation system, to the seat of conversion to the defect image 1101 on defect layout patterns 1111
Cursor position carries out the correction of grid deviation amount, and wherein grid deviation amount is (X2’-X2,Y2’-Y2) or by grid deviation amount (X2’-
X2,Y2’-Y2) the average coordinates accuracy value of X-axis and Y-axis Jing Guo Tong Jifenxi and the standard deviation value of coordinate precision.
In addition, the present invention can choose the mode of another correction also to obtain accurately grid deviation correcting value.Such as step
Shown in rapid 2420,1111 file of defect layout patterns of first component is obtained by data processing centre 21；Then, by data
After processing center 21 obtains the image file 1001 of the defect image 1101 of corresponding first component, together in indicator screen
The image file 1001 of defect layout patterns 1111 and defect image 1101 is shown on 51；Likewise, in one embodiment, institute
The defect layout patterns 1111 of display and the image file 1001 of defect image 1101 be tuned into unit it is consistent (such as:
The units such as pixel unit or micron, nanometer it have been adjusted to)；And then by execution correction personnel via graphical user interface
(Graphical User Interface；GUI) directly with the arrow (cursor) on mouse by actual defects image 1101 with
Position between 1102 pattern of route indicates new coordinate position on the position of the respective lines pattern of defect layout patterns 1111
(X2’,Y2 ’), as shown in the upper half figure of Fig. 6 B；Such as: by correction personnel in a manual manner with arrow (cursor) by defect map
As the position of file 1001 location mark opposite on defect layout patterns 1111 goes out new coordinate position (X2’,Y2')；Later,
It can be by the coordinate position (X of defect image 11011,Y1) convert and indicate the coordinate position (X on defect layout patterns 11112,
Y2) display.If showing the coordinate position (X of conversion to the defect image 1101 on defect layout patterns 11112,Y2) and defect
The position of image 1101 and the new coordinate position (X on defect layout patterns 11112’,Y2') not in same position, so that it may
To correction for drift, wherein grid deviation correcting value is (X2’-X2,Y2’-Y2), as shown in the lower half figure of Fig. 6 B.Later, as walked
Rapid 250, to shown in step 260, sequentially carry out a certain number of corrections, the mistake of process and mode and Fig. 6 A according to aforesaid way
Cheng Xiangtong, and an average coordinates accuracy value (Average Coordinate in X-axis and Y-axis can be obtained
Precision Value) and coordinate precision standard deviation value (Standard Deviation) coordinate modification threshold values, with make
For the basis and importing coordinate transformation system of deviation correction, so it will not be repeated.
In addition, the present invention can choose the mode of another correction also to obtain accurately grid deviation correcting value.Such as step
Shown in rapid 2430,1111 file of defect layout patterns of first component is obtained by data processing centre 21；Then, by data
After processing center 21 obtains the image file 1001 of the defect image 1101 of corresponding first component, together in indicator screen
The image file 1001 of defect layout patterns 1111 and defect image 1101 is shown on 51.Likewise, in one embodiment, institute
The defect layout patterns 1111 of display and the image file 1001 of defect image 1101 have been tuned into consistent (example in dimensional units
Such as: being adjusted to pixel unit or micron, nanometer unit)；Later, by data processing centre 21 by defect layout
It is automatic right that 1113 pattern of route in case 1111 is carried out with 1102 pattern of route on the image file 1001 of defect image 1101
Standard, as shown in the middle graph of Fig. 6 C；It later, can be by the coordinate position (X of 1101 file of defect image1,Y1) be laid out in defect
Location mark on pattern 1111 goes out new coordinate position (X2’,Y2').If showing conversion to defect layout patterns 1111
Defect coordinate position (X2,Y2) with the new coordinate position (X that indicates2’,Y2') position is not at the same position, progress deviation
Correction, wherein grid deviation correcting value be (X2’-X2,Y2’-Y2), as shown in Fig. 6 C lower half figure.Later, such as step 250 to step
Shown in rapid 270, it is identical as the process of Fig. 6 A sequentially to carry out a certain number of corrections, process and mode according to aforesaid way,
It is that can obtain one in X-axis and the average coordinates accuracy value (Average Coordinate Precision Value) of Y-axis
And the coordinate modification threshold values of the standard deviation value (Standard Deviation) of coordinate precision, to correct it as progress deviation
According to and import coordinate transformation system, so it will not be repeated.
Above-mentioned Fig. 6 A, Fig. 6 B and Fig. 6 C is to illustrate that the present invention is capable of providing multiple realities of accurate coordinates deviation correcting value
Mode is applied, it therefore, can be via step 250 to step 260 as long as any one of selection Fig. 6 A, Fig. 6 B and Fig. 6 C mode
It is shown, it obtains with grid deviation correcting value with accurate statistical value as grid deviation correcting value or amendment threshold values.
After completing step 200, " intelligence system " of the invention has been achieved with the conversion of defect image 1101 to design layout
After coordinate position correction for drift on Figure 111 0, wherein grid deviation correcting value is (X2’-X2,Y2’-Y2) or coordinate it is inclined
The statistical value (coordinate modification threshold values namely above-mentioned) of poor correcting value, such as: the average coordinates accuracy value of X-axis and Y-axis
Standard deviation value (the Standard of (Average Coordinate Precision Value) and coordinate precision
Deviation).Followed by seeking to judge that defect image 1101 generates this defect image after 0 grade of design layout Figure 111
Whether 1101 will cause the critical defect of the failure such as breaking (open circuit) or short-circuit (short circuit).Due to lacking
It falls into image 1101 or its profile (contour) is all image figure, and design layout Figure 111 0 is GDS or OASIS format, together
When, on design layout Figure 111 0 and non-defective pattern, therefore can not execute at all short circuit caused by defect image 1101 or
Open defect analysis.Again since the profile of defect image 1101 may be irregular shape, the present invention provides a kind of lack
Acquisition (clip) the defect profile method for falling into image 1101, to obtain the flaw size size and area of defect image 1101,
The basis of critical defect as open circuit or short circuit type failure.
As shown in step 140, it also please also refer to Fig. 7 A to Fig. 7 D, be the defect profile of acquisition defect image of the invention
And it overlaps to the schematic diagram of the defect coordinate position on design layout figure.Firstly, " intelligence system " by data processing centre 21 from
Image file 1001 in defect text and image data file 1130 obtains the overall size of a defect image 1101, including
The full-size of X-axis and the full-size of Y-axis.Then, by data processing centre 21 according to capturing to obtain defect image 1101
Overall size generates polygon (Polygon) defect image 1103 identical with defect profile maximum X-axis, Y-axis size
Pattern；Such as: if the full-size of X-axis is 0.1 micron and the full-size of Y-axis is 0.08 micron, polygon defect image
1103 patterns 0.008 square micron of area (μm2), such as the arrow below Fig. 7 A.Followed by defect image 1101 will be captured
The defect pattern 1103 of contour patterns or polygon overlaps (Superposition) or mapping (mapping) is to after correcting
Coordinate (the X of defect layout patterns 11112’,Y2') or grid deviation correcting value be (X2’-X2,Y2’-Y2) or grid deviation
On the statistical value of correcting value, the defect image 1101 or polygon defect 1103 patterns of image after judging this acquisition accordingly are big
The influence of the small critical defect that short circuit or open circuit etc. whether are generated to the route 1113 on 1111 file of defect layout patterns；Such as
Shown in the defect layout patterns 1111 on the left side Fig. 7 B, as a kind of systematic defect of short circuit, i.e., two routes 1113 are by one
Defect image 1101 links together；For another example shown in the defect layout patterns 1111 on the right of Fig. 7 B, as a kind of system of open circuit
Property defect, i.e. a route 1113 are completely covered by a defect image 1101 and form blocking.Then, it just can use step
150 or step 160 judge whether to have on defect pattern 1001 or defect layout patterns 1111 open circuit or the fatal of short circuit type to lack
It falls into.
Next, the key area for carrying out step 150 analyzes (Critical Area Analysis, CAA) method.Work as number
1103 area of polygon defect image of acquisition is overlapped according to processing center 21 opposite to defect layout patterns 1111
At 1101 coordinate of defect image, at this point, this polygon defect captured can be analyzed using key area analysis method
Image 1101 may determine that the machine of the defect of open circuit or short circuit type failure in the key area on defect layout patterns 1111
Rate value；The probit value of this defect is critical defect index (KDI), that is, CAA value.Such as: engineer picks each
1101 pattern of polygon defect image taken overlaps to defect layout patterns 1111, and judges whether to will cause route accordingly
1113 short circuit or open circuit, meanwhile, engineer can also be according to the pass of 1103 pattern and route 1113 of polygon defect image
Key range size judges critical defect probit value.The critical defect of (being Fig. 3 C defective patterns 6) as seen in figure 7 c
Judgement, when the size of 1103 pattern of polygon defect image of 1101 pattern of defect image or acquisition of acquisition is much smaller than route
When the distance between 1113 size or route 1113；Such as: when the size of 1103 pattern of polygon defect image is 0.008
μm2When, and when the spacing dimension of the width of route 1113 and route 1113 is all 0.1 μm, then either 1101 figure of defect image
Case or 1103 pattern of polygon defect image of acquisition will not all cause the systematicness of open circuit or short circuit type to lack to route 1113
Fall into, then judge critical area for 0, therefore critical defect index KDI=0；If working as the ruler of 1103 pattern of polygon defect image
Very little (is 0.001 μm2When) it is suitable or close with the width dimensions (when being 0.1 μm) of route 1113 when, although will cause route
1113 open circuit or short circuit, but because 1101 pattern of defect image or polygon defect image 1103 fall in defect layout patterns
Probability on 1111 route 1113 is how many related with the route 1113 on defect layout patterns 1111.Again as seen in figure 7 c,
When the critical area of route 1113 only accounts for the 1/10 of the total grid deviation range areas of defect layout patterns 1111, then judge
Critical area is 0.1, therefore critical defect index KDI=0.1, that is to say, that 1103 pattern of polygon defect image can be made
Probability at 1113 open circuit of route or short circuit on the defect layout patterns 1111 of Fig. 7 C is 0.1.
Likewise, to illustrate how analysis and judging the implementation of critical defect index with Fig. 7 D again.As illustrated in fig. 7d, this hair
Analysis (the Critical Area Analysis) method of key area used in bright is often used in Design For
The yield sunykatuib analysis of Manufacturing, that is, the key area of analysis ic design layout figure.Carrying out sunykatuib analysis
When, it has assumed that one group of defect is arbitrarily placed on an arbitrary coordinate with random counting method, how many defective effect yield is judged
And possible yield is estimated accordingly.Key area analysis method used in the present invention is by the defect of defect checking machine platform
In data, defect image 1101 and its flaw size size, area are captured, is converted to the phase on defect layout patterns 1111
It answers on coordinate, and calculates this grid deviation range areas (as previously described, because of the mobile control motor essence of defect checking machine platform
Deviation caused by degree, defect may be in any coordinates of this grid deviation range areas) the defects of layout patterns 1111 pass
Key range, and critical defect index (KDI) be the critical area that obtains of analysis divided by grid deviation range areas area (i.e.
The area of defect layout patterns 1111), and the probit value of the defect of open circuit or short circuit type failure is calculated accordingly, it is fatal lack
It falls into index (KDI).As shown in the schematic diagram on the left side Fig. 7 D, when 1101 pattern of defect image or the polygon defect image of acquisition
1103 patterns will not all cause the systematic defect of open circuit or short circuit type to route 1113, then judge critical area for 0, then
Judge the KDI value of defect sampling be equal to 0 or level off to 0 when, represent defect and cause line broken circuit or short circuit (i.e. crystal grain failure)
Probability is lower.Shown in schematic diagram on the right of Fig. 7 D, when defect image 1101 or 1103 figure of polygon defect image captured
The size of case (is 0.001 μm2When) it is suitable or close with the width dimensions (for 0.1 μm) of route 1113 when, will result in route
1113 open circuit or short circuit causes breaking critical area (Open Critical Area with regard to needing to calculate at this time；
OCA) and cause short circuit critical area (Short Critical Area；SCA), the area as shown in the dotted line in Fig. 7 E
Domain, since the critical area of open circuit and the critical area of short circuit can all cause systematic defect or randomness to lack
It falls into, therefore needs to be added the critical area of the two and then divided by grid deviation range areas area (such as said deviations model
It encloses and is detected after board carries out Defect Scanning detection for -0.5 μm~+0.5 μm of optical defect, then the seat of defect layout patterns 1111
Marking deviation range region area is 1 μm x1 μm)；Such as: when the conductor size in defect layout patterns 1111 is 50nm, and conducting wire
When size distance between another conducting wire is 30nm, and when the size of 1101 pattern of defect image is 60nm, it is evident that when
No matter defect image 1101 having a size of 60nm, which falls in which of defect layout patterns 1111 all, can cause mortality to lack
It falls into, therefore, when the critical area (OCA) of open circuit is 0.7 μm2And causing the critical area (SCA) of short circuit is 0.3 μm2
When, then KDI value is equal to 0.7 μm2+0.3μm2/ 1 μm x1 μm=1；Therefore, judge that the KDI value of defect sampling is equal to 1 or levels off to
1；When judging result be KDI value be equal to 1 or level off to 1 when, represent defect and cause line broken circuit or short circuit (i.e. crystal grain failure)
Probability is higher, and the selection chance of defect sampling is bigger.Finally, the defect machine of 1101 pattern of polygon defect image of these defects
Rate value will record into internal storage location 23.
In addition, the present invention also can choose step 160, one directly is being captured with the image where defect image 1101
File 1001 (this image file 1001 is as previously shown, including defect profile image 1101 and its relative to the position of adjacent lines)
Later, its defect layout patterns 1111 corresponding with image file 1001 is overlapped (schematic diagram among such as Fig. 6 C), to
It carries out judging whether defect image 1101 causes open circuit or short circuit type failure defect.Such as: when data processing centre 21 directly will
One captured has the image file 1001 of 1101 profile of genetic defects image and lacking where opposite defect image 1101
After sunken layout patterns 1111 are overlapped, at this point, data processing centre 21 or engineer can be according to genetic defects images
1101 profile compares the overlay position after matching to determine whether for open circuit with defect layout patterns 1111 by figure
Whether (Open Circuits) type failure defect is short-circuit (Short Circuits) type failure defect；If judgement knot
When fruit is open circuit or short circuit type failure, judgement is to belong to critical defect, then judges critical defect index (KDI) for 1；If it is determined that
When as a result to fail without open circuit or short circuit type, judgement is to belong to non-lethal defect, then judges critical defect index (KDI) for 0.
Finally, recording critical defect index (KDI) judging result of these defect images 1101 into internal storage location 23.Clearly
, since the present embodiment is the image file 1001 that will directly capture with 1101 profile of genetic defects image and opposite defect
After defect layout patterns 1111 where image 1101 are overlapped, so that it may directly judge the critical defect of defect image 1101
Index (KDI) value；Therefore, after a step of preferred embodiment for carrying out step 160 is, first passes through Fig. 4 or Fig. 5, also
It is the seat in the coordinate for obtaining correct 1101 profile of genetic defects image and accurately converting out opposite defect image 1101
Defect layout patterns 1111 where mark are crucial；In addition, being defect image carrying out the another preferred embodiment of step 160
1101 image file 1001 is the image file scanned by SEM.It is stressed again that since the precision of SEM scanning is high, therefore scan
The genetic defects image 1101 arrived is exactly actual defects position, at this point, just having known that the fatal of defect image 1101 lacks
Index (KDI) value is fallen into, also therefore, in the present embodiment, (KDI) Zhi Only has 1 or 0 to critical defect index；And it selects directly to
Defect layout patterns where image file 1001 and opposite defect image 1101 with 1101 profile of genetic defects image
1111 purposes to overlap, exactly it is to be understood that defect image 1101 is which position on defect layout patterns 1111, with
Continuing to be directed to after an action of the bowels causes the defect layout patterns 1111 of critical defect to carry out necessary layout modification.
According to above-mentioned, in progress defect image 1101 critical defect index (KDI) or key area analysis (CAA) point
When analysis, " intelligence system " of the invention can choose using with 1101 profile of genetic defects image image file 1001 come with
Defect layout patterns 1111 where opposite defect image 1101 overlap, as shown in step 160；Also it can choose use to pick
1101 area of defect image taken overlaps on opposite 1101 coordinate of defect image to design layout Figure 111 0, such as step
Shown in 150；In this regard, the present invention is not limited thereto.
According to aforementioned, generally when the defect image 1101 for carrying out wafer 10 scans, for the purpose for reaching quick scanning, greatly
It is all selection by light such as microscopy apparatus, electron beam (E-beam) detection board, optical detection board, Defect Scanning instrument or cameras
Equipment is learned, come the defective data (such as: size, width, size, coordinate or profile ... of defect etc.) being quickly obtained on wafer.
Due to using optical device above-mentioned carry out defect image 1101 scan when, can between optical device and scanned wafer 10
The resolution ratio (Resolution) that the Scanning Detction of some optical devices camera lens itself and wavelength can be had is not enough to clearly present
Defect image, such as: after defect image 1101 (defocus) out of focus, it will result in the edge blurry of defect image 1101,
So that the more actual defect pattern of defect image 1101 scanned is bigger, the erroneous judgement of critical defect will cause.In addition, each
Optical scanning device has certain precision limitation, when precision deficiency, will cause scanning defect and differentiates used minimum
Unit is bigger relative to minimum dimension layout patterns, it is this cause defect image 1101 obscure situation out of focus, will also result in
The erroneous judgement of critical defect.Such as: when resolution ratio (Resolution) unit of optical device is 50 nanometers, and defect image
When 1101 actual X-axis or Y-axis size are 35 nanometer, then its defect image 1101 that can judge of optical device is most
Small size is 50 nanometers；This result will cause the original detection defect report in defect text and image data file 1130
Be with scan compare analysis minimum unit multiple come note down scan detect 1101 size of defect image and area, and this
The size and area of one defect image 1101, which are much larger than, is broken forth with the electron microscope (SEM) of precision 1,2 nanometer grades
1101 size of actual defects image and area；It will be apparent that the incorrect of this genetic defects size influences whether critical defect
Index, it is possible to cause to judge by accident non-lethal defect or low-risk critical defect into high risk critical defect；Such as: actual defects shadow
As 1101 sizes and area not will cause the defect of open circuit or short circuit type failure, but because the fuzzy mistake of the precision deficiency of minimum unit
It is burnt the result is that multiple 1101 areas of defect image that will cause defect report are excessive and are judged as that risk is higher and fatal lack
It falls into, it will the reduction probability that really open circuit or short circuit type failure defect are sampled, and cause yield to improve slow or cost and increase
The problems such as adding.It will be apparent that the flaw size of the original detection defect report of this defect image 1101, the minimum compared by scanning
The precision of unit is insufficient, needs further to be corrected into close to actual flaw size, can just make accurate judgement, promotes open circuit
Or the success rate of short circuit type failure defect sampling.
In order to solve the problems, such as that above-mentioned optical device is out of focus during scanning wafer 10, the present invention provides a kind of pair of defect
The corrected method of flaw size and area of image 1101.As shown in the step 500 of Fig. 8 A, wherein Fig. 8 A is the present invention
The flow chart of the correction system of flaw size, area is established, and accurately flaw size correction is key area analysis
(CAA) and critical defect index (KDI) accuracy correction the only effective means.The left end of Fig. 8 B is by data processing centre 21
Genetic defects size, the area that defects detection report provides are read from defect text and image data file 1130；Then, exist
By data processing centre 21 from defect text and image data file 1130 the high defect image file of resolutions lack
Fall into size；According to preferred embodiment, the defect image file of high resolution is image file size, area acquired by SEM；
Followed by correcting genetic defects overall size according to the defect image document size of high resolution and change into polygon defect map
Case；Fig. 8 C, which is that the approximation after indicating the defect image file correction of the genetic defects size of left end by high resolution is practical, to be lacked
Fall into the flaw size table of overall size；Detailed description are as follows.
As shown in Figure 8 A, the flow chart 500 of key area of the invention analysis and critical defect index correction is by data
Processing center 21 obtains defect text and image data file 1130 starts；Firstly, as shown at step 120, by Data processing
The heart 21 obtains genetic defects data (including text file and defect image file from defect text and image data file 1130
Case)；Then, as indicated in step 510, by data processing centre 21 from the defects of defect text and image data file 1130 text
Word obtains polygon defect image 1103 in X-axis and the genetic defects size (original defect size) and defect of Y-axis
Area (area)；When the optical device precision of scanning defect is insufficient, (flaw size scanned is also big compared with actual defects size
When), such as: when the precision of an optical device is 50 nanometer, detected by minimum defect size be 50 nanometers, therefore work as
When genetic defects size is less than 50 nanometer, optical device is to be presented as unit of the multiple of 50 nanometers, therefore optical device detects
Minimum defect size and the higher SEM photograph of precision (such as: precision unit be 2 nanometers) detected by minimum defect size
There is deviation；Such as: the original size of the 3rd defect image 1101 in Fig. 8 C is that X-axis is 50 nanometers and Y-axis is 50 nanometers；And
The original size of 4th defect image 1101 is that X-axis is 150 nanometers and Y-axis is 150 nanometers, such as: the 3rd original in Fig. 8 C
The critical defect index of beginning defect image 1101 is judged as 0.4；And the critical defect index of the 4th defect image 1101 is judged as
1.Then, as indicated in step 520, from the acquisition of internal storage location 23, each is high by being confirmed as precision for data processing centre 21
Defect image 1101 simultaneously obtains defect profile size (image contour defect size) and defect profile area；Such as:
When the resolution ratio of used scanning electron microscope (SEM) photo is 3 nanometer, the 3rd can be parsed out in Fig. 8 C is lacked
The accurate dimension for falling into image 1101 is that X-axis is 35 nanometers and Y-axis is 35 nanometers；And the accurate dimension of the 4th defect image 1101
It is that X-axis is 100 nanometers and Y-axis is 120 nanometers.Therefore, the cause after the correction of the present embodiment, after available accurate correction
It orders defect index (KDI)；Such as: the practical critical defect index amendment of the 3rd defect image 1101 after calibration in Fig. 8 C
It is 0.1；And the practical critical defect index of the 4th defect image 1101 after calibration is modified to 0.55.Followed by such as step
Shown in 530, applied statistical method is to multiple genetic defects sizes, defect area group and the high defect profile ruler of multiple precisions
Very little, defect profile area group is corrected and finds out best statistical method；Then, as shown in step 540, establish and use statistics side
The flaw size correction system and measurement analysis on Uncertainty of method, online will execute produced by the optical device that fast weak detects
Genetic defects dimension data be converted into approximate actual flaw size data, and practical conversion process will be detailed at next section
Explanation.Furthermore, it is emphasized that i.e. right defects detection is most accurately SEM board, why not is directly used, and will be by multiple
Miscellaneous correction program.This is because defects detection is just carried out after wafer 10 completes manufacture, although and SEM is accurate practical
Operating process is complicated, therefore its detectability is only capable of the genetic defects dimensional data of processing about 1%, in order to accelerate processing time, institute
All defect is handled not to be available SEM, can only quickly be scanned using the optical device of detection fast speed；Therefore,
If corrected without flaw size, as described above, critical defect index is caused to judge by accident, other than influencing defect classification, also can
The improvement for influencing defect yield, in turn results in the increase of manufacturing time and cost；As shown in step 550, via flaw size school
Just it is being equal to the practical key area that promoted to analyze the critical defect index accuracy obtained and accurately differentiate critical defect.In this reality
It applies in example, to select the accurate defect image of how many SEM to execute statistics and correct, the present invention is not limited thereto.Then,
It further says, if the scanning speed of SEM equipment is improved or has other advanced scanning devices that can rapidly provide institute
Defective processing, then the critical defect index of defect can be using previously it is stated that the step 160 crossed be accurate to obtain
As a result.Because processing procedure continue it is miniature, such as layout minimum dimension 1,2 nanometers or be lower than 1 nanometer when, it is gradually suitable with SEM precision
Or smaller, drawbacks described above dimension correction system and method, it stands good in new defect checking machine platform and photograph board, herein not
It limits.
Please continue to refer to Fig. 8 C, illustrate that the defect report that the online defect checking machine platform scanning wafer of semiconductor factory generates is not
Accurate genetic defects dimension data, via the correction and measurement analysis on Uncertainty of this " flaw size correction system ", conversion
At the flaw size correcting process of approximate actual flaw size data.Shown in 8A and Fig. 8 B.As shown in step 540, at data
It reason center 21 can be to genetic defects size of each defect image 1101 before correction (original defect size)
A statistical calculation is carried out with the real defect image (real defect size) after correction, to establish a statistics mould
Type, and according to this statistical model come corrective pitting image 1101 in X-axis and the size of Y-axis；Such as: it is 1 by critical defect index
Defect image 1101 be corrected after statistical model define a correction factor (factor)=0.85；Such as: Fig. 8 C
In the original size of the 4th defect image 1101 be that X-axis is 150 nanometers and Y-axis is 150 nanometers, using after step 540,
It needs for the original size of defect image 1101 or polygon defect image 1103 to be multiplied with the factor (factor)=0.85, because
It is that X-axis is that this, which can directly obtain revised defect image 1104 or the size of revised polygon defect image 1105,
130 nanometers and Y-axis are 130 nanometers.Or the statistics mould after being corrected by the defect image 1101 that critical defect index is 0.5
Type defines a correction factor (Calibration factor)=0.9, and conversion process is as previously mentioned, repeat no more.It
Afterwards, as shown in step 550, data processing centre 21 defines the factor according to statistical model, automatically to each defect image
1101 are corrected and at opposite 1101 coordinate of defect image to design layout Figure 111 0 that overlaps.Finally, by data processing
After center 21 or engineer rejudge correction, each available more accurate critical defect of defect image 1101 refers to
Number.
By the correction course of Fig. 8 A, Fig. 8 B and Fig. 8 C, actual flaw size data can be more accurately obtained, because
It is with flaw size in positive relationship for critical defect index, incorrect flaw size data will will cause high critical defect and refer to
Number defects count is higher, and the defect for choosing open circuit or short circuit type failure is more difficult from, and increases the time and cost that yield improves.
Flaw size before the data display correction of Fig. 8 C table and after corrected.It will be apparent that in the above-described embodiment, directly selecting
It selects and is corrected using the Defect Scanning archives of SEM, for best effect；It secondly is threshold values, meanwhile, when the sample for determining threshold values
When the more, the statistical value of threshold values can be closer to the scanning result of SEM.
In the analysis and step 500 of defect open circuit or the short circuit type failure of the step 150 and step 160 by Fig. 2
After correction, the present invention can further classify to defect image 1101.As indicated at step 170, by abovementioned steps pair
The correction of defect is as a result, be categorized into non-lethal defect (Non-killer defect) or critical defect (Killer for defect
defect).For example, step 150 implementing result is with fatal defect index (KDI) value, defect signal parameter (defect
Signal parameter) and whether have the Graphic Pattern Matching of the defect database with defective patterns database and high failure frequency
Person, to classify；Wherein, above-mentioned defect signal parameter is to be directed to or select the image text with defect image 1101
Part 1001 and using on each pixel p ixel in image analysing computer dual space intensity value (intensity or
Brightness), as shown in Figure 11 A, it is as unit of pixel quantity that wherein horizontal axis, which is by intensity value and the longitudinal axis,；By Figure 11 A
Carry out reduced value (contrast) of the analyzing defect pattern with respect to its ambient background pattern and judges that this defect pattern and its shadow become
Change is the upper layer or beneath polarity number (polarity) in background.And step 160 implementing result is with defect profile and two
Different polygon patterns (polygon) overlaps or overlaps with a polygon pattern, and defect is categorized into non-lethal defect
Or the critical defect of open circuit or short circuit type failure, detailed executive mode, such as rear explanation.
In addition, establishing defective patterns database (defect pattern library) and high failure using Fig. 2 step 180
The defect database (frequent failure defect library) of frequency；Wherein, one of defective patterns source, comprising:
The layout graph of design drawing criterion (design rule check error) is violated, such as distance criterion is 30 nanometers, it is practical
Pattern is that 28 nanometers relatively easily cause low yield, can be selected into defective patterns database, such as Figure 11 B institute because reducing process window
Show；Another defective patterns source is to carry out DFM (Design for Manufacturing) emulation testing analysis design layout
When pattern 1110, if occur also may cause low yield because process window simulation analysis value risk is higher, need further comparing
To on relative position practical on wafer whether it is defective cause open circuit or short circuit, therefore defective patterns database is selected into, such as Figure 11 C
On X label shown in.In addition, in defect database (the frequent failure defect for establishing high failure frequency
Library) aspect, be by combining more 1101 data of defect image gone out by optical device actual scanning after, reuse figure
Shape matching process, agrees or the pattern of similar fitgures, builds on high failure frequency defect database, as shown in Figure 11 D,
When the route on design layout figure is more intensively located, that is, belongs to the defect pattern of high failure frequency, need further to compare on wafer
On practical relative position whether it is defective cause open circuit or short circuit, therefore the defect database of high failure frequency can be included in.Therefore, it uses
The open circuit or short circuit type that family can find systematic defect layout patterns 1111, accident analysis (failure analysis) are scarce
Sunken layout patterns, the layout patterns for violating design rule (DRC error), DFM emulation testing are risk layout patterns
(Design For Manufacturing check as weak pattern) builds on defective patterns database, Yong Huyi
The defect database of patent No. US8607169B2 that same inventor checked and approved in 2013 about high failure frequency can be quoted
The patented method of (frequent failure defect library) establishes the defect database of high failure frequency.Step
170 will hold the defect database for the defective data and defective patterns database and high failure frequency that defect checking machine platform is detected
Row Graphic Pattern Matching (the TaiWan, China patent No. I 534646 that the same inventor of pattern match checked and approved in 2016
Number), the same or similar defect layout patterns are found out to carry out defect analysis.
In addition, referring to FIG. 9, being the flow chart for executing the polygon pattern comparison analysis of defect profile and layout patterns.Such as
It is to compare analysis by the polygon pattern of step 160 execution defect profile and layout patterns to determine whether open circuit shown in Fig. 9
Or classify after the defect of short circuit type failure.Wherein, as shown in step 1610, if 1101 position of defect image is in defect
Without 1113 pattern of route or it is the virtual layout pattern of non-actual track within the scope of the grid deviation of layout patterns 1111
(dummy pattern), thus it is possible without open circuit or short circuit type failure, and this is judged as dummy pattern defect (dummy pattern
Defect), as depicted in fig. 11E, belong to non-lethal defect (Non-killer defect).Then, false as shown in step 1620
As there is 1113 pattern of route in 1101 position of defect image within the scope of the grid deviation of defect layout patterns 1111, but by step
160 execute the polygon pattern comparison analysis of defect profile and layout patterns, have no open circuit or short circuit type may fail, this is judged as
The defect that is free from risk (nuisance defect) only has an area to have route 1113 in defect layout patterns 1111 as shown in fig. 11f
And this wire sizes is much larger than defect image size, therefore no matter defect image is fallen in the region, not will cause open circuit or short
The possibility of road type failure, therefore belong to non-lethal defect (Non-killer defect).Followed by, as shown in step 1630, if
There is 1113 pattern of route in 1101 position of defect image within the scope of the grid deviation of defect layout patterns 1111, but by step 160
The polygon pattern for executing defect profile and layout patterns compares analysis, it is understood that there may be open circuit or short circuit type failure, this for open circuit or
Short circuit type fails defect (open or short defect), if Fig. 7 D is shown in the KDI=1, therefore belongs to critical defect (Killer
defect)。
It is defect classification process figure of the invention finally, please referring to such as Figure 10.As shown in Figure 10, defect signal number is obtained
According to and KDI value, according to the critical defect index KDI value and signal parameter value of each defect, and whether there is or not with defective patterns data
The defect database of library and high failure frequency executes the defect of Graphic Pattern Matching, and defect is categorized into non-lethal defect (Non-
Killer defect) and critical defect (Killer defect), the foundation of defect sampling is provided.It obtains and lacks by step 1710
Sunken data and the defect signal data of analysis, and step 1720, then be lacking for 150 key area analysis method of obtaining step calculating
Critical defect index KDI value is fallen into, step 1730 is then the critical defect index KDI value and defect signal parameter according to each defect
Value, in addition whether there is or not the defects that the defect database with defective patterns database and high failure frequency executes Graphic Pattern Matching, by defect
It does and classifies；Wherein, defective patterns database please refers to Figure 11 A to Figure 11 G.Later, step 1740 be then determine whether open circuit or
Short circuit type failure is possible, such as: when the critical defect index KDI value for judging defect is equal to 0, no matter then defect signal parameter value
For how many (as shown in Figure 11 A), this is judged for dummy pattern defect (as depicted in fig. 11E), belongs to non-lethal defect (Non-
Killer defect), it is to be filtered fall, that is, in subsequent execution defect sampling analysis, the choosing of defect can be not counted in
It selects；Such as: in 5000 defect images 1101, there are 3000 when belonging to non-lethal defect, then in defect sampling analysis, i.e.,
This 3000 defects are not counted in the selection of defect.And in step 1750, then it is as the critical defect index KDI for judging defect
When value is equal to or levels off to 0, and though defect signal parameter value be it is how many, judge this for the defect that is free from risk (as shown in fig. 11f),
Also belong to non-lethal defect (Non-killer defect), therefore, equally also it is to be filtered fall, filter type such as step
1740, it is not repeating.
Then, step 1760 is carried out.Firstly, be classify for the defect that is not filtered, such as: selection causes height
Life defect index KDI value (such as: 0.75~1) and high defect signal parameter value is classified as the first preferential sampling group；Secondly, selection is high
Critical defect index KDI value (such as: 0.75~1) and moderate defect signal parameter value is classified as the second preferential sampling group；Followed by,
Selection by the critical defect index KDI value of median (such as: 0.5~0.75) and high defect signal parameter value to be classified as first preferential
Sample group；Secondly, by the critical defect index KDI value of median (such as: 0.5~0.75) and the defect signal parameter of median
Value is classified as the second preferential sampling group；It is noted that being above to belong to high risk critical defect (high risk killer
Defect sampling group) is the defect cluster that must be modified；But the modification of defect cluster is if desired completed within the shortest time
When, then it can selection sort be more preferably the first preferential sampling group, comprising: select high critical defect index value and high defect signal
The sampling group of parameter value column and the sampling group for selecting median critical defect index value and high defect signal parameter value column；For
How sampling group is determined, the present invention is not limited thereto.
Thirdly, be selection by low critical defect index KDI value (such as: 0.2~0.5), Yi Jigao, middle defect signal ginseng
Numerical value is as another sampling group, and due to being to belong to low-risk critical defect (low risk killer defect), defect is taken
Sample order of priority is classified as third and preferentially samples group, only does slight imperfections sampling；As for minimum critical defect index KDI value (such as:
< 0.2), such as: belong to extremely low risk critical defect and low defect signal parameter value etc., be to belong to extremely low risk critical defect
(negligible risk killer defect), such defect approximation are free from risk defect (nuisance defect), very
Be similar to non-lethal defect (Non-killer defect), thus be not required to be included in defect sampling or be also included in it is to be filtered fall
Sample group.Defect image 1101 all on wafer 10 is classified and is sampled by above-mentioned process, therefore these points
Class and the result of sampling will continue to expand in defect text and image data file 1130 (being shown in Fig. 3 B), that is, will be every
It is which sampling group belonged to that one defect image 1101, which all indicates,；Certainly, the defect text and image data file after expansion
1130 also will be updated and be stored in internal storage location 31.
In addition, after completing the defect classification of step 1730, and can choose and defect map figurate number as shown in step 1770
Figure is executed according to the high defect database in library and failure frequency and compares matching, if any the same or similar defect, and is to belong to police
The property guarded against defect, then must be sampled；It but if it is belonging to spurious defects layout patterns (as shown in fig. 11g), is then lacked false
It falls into and filters out.
According to above-mentioned explanation, " intelligent defect correcting system and its implementation method " of the invention is with defect coordinate
And the key area accuracy of analysis of flaw size correction system improving defect, promotion judges semiconductor defect, and whether there is or not cause open circuit
Or the critical defect precision of short circuit type, the filtering of non-lethal defect is excluded to sample in defect, it, will in conjunction with defect signal parameter
Critical defect and its classification of risks grade with defect signal intensity value and are lacked as defect sampling priority compared to conventional method
Falling into size is defect sampling standard, promotes the ability of the critical defect of the real open circuit of discovery or short circuit type, it is good to shorten defect
Rate learning curve and promotion yield, volume production can increase business revenue ahead of time, and Yield lmproved can reduce cost.
Detailed embodiment is illustrated as above, the patent right that however, it is not to limit the invention advocates by the present invention
Range.Its scope of patent protection when depending on after attached claim and its depending on waiting same domains.All this fields, which have, usually to be known
The knowledgeable is not departing from this patent spirit or scope, and it is complete to belong to lower of disclosed spirit for the change or retouching made
At equivalent change or design, and should be included in following claims in.
Claims (31)
1. a kind of method for executing intelligent semiconductor crystal wafer defect correction by data processing centre and storage device, special
Sign is:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out each route with respect between the position of a coordinate, line width and route
Distance；
The first overlapping program is executed, is by the data processing centre from the defect image and lteral data file, one by one
Defect coordinate, flaw size and the defect area of defect image pattern are captured, and according to the defect coordinate by the defect ruler
It is very little to overlap with the defect area to a relative coordinate of the IC design layout pattern；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value, wherein the critical defect index value
Distinguish the numerical value of multiple and different sizes；
Execute a correction program, comprising:
Select at least one described critical defect index value；
A SEM scanning machine is provided, and again to each defective locations where the critical defect index value selected
Scanning to obtain accurately flaw size and a defect area, and is stored into the storage device；
Judge the accurately flaw size and defect area whether be open type or short circuit type systemic critical defect.
2. a kind of method for executing the defect correction of intelligent semiconductor crystal wafer by data processing centre and storage device,
It is characterized in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is in semiconductor factory and will be described according to the IC design layout map file case
Plurality of lines is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out each route with respect between the position of a coordinate, line width and route
Distance；
The first overlapping program is executed, is by the data processing centre from the defect image and lteral data file, one by one
Defect coordinate, flaw size and the defect area of defect image pattern are captured, and according to the defect coordinate by the defect ruler
It is very little to overlap with the defect area to a relative coordinate of the IC design layout pattern；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value, wherein the critical defect index value
Distinguish multiple and different numerical value；
Execute a correction program, comprising:
Select at least one described critical defect index value；
One SEM scanning machine is provided, and each defective locations where the critical defect index value selected are swept again
It retouches, to obtain accurately flaw size and a defect area, and stores into the storage device；
Execute the second overlapping program, be accurately flaw size and the defect area are captured by the data processing centre, and
According to the defect coordinate, accurately defect area overlaps to a phase of the IC design layout pattern by described relatively
To on coordinate；
The analysis of the second key area is executed, is by the data processing centre according to accurately flaw size and the defect area
It overlaps on the IC design layout pattern, obtains each defect in grid deviation model using key area analysis method
The key area for enclosing the design layout pattern in region, the critical defect index value after judging a correction, wherein the correction
Critical defect index value afterwards distinguishes multiple and different numerical value.
3. a kind of defect correction method for executing intelligent semiconductor crystal wafer by data processing centre and storage device, special
Sign is:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least wafer coordinate origin, defect coordinate, flaw size, defect area and defect image pattern
Intensity value；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out the position of coordinate origin, each route with respect to a coordinate, line width
And the distance between route；
The first coordinate conversion program is executed, is to obtain one by the data processing centre from the defect image data file
Defect coordinate (the X of defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout pattern
An opposite first coordinate (X2,Y2)；
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing centre
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing centre again
The configuration map file case of corresponding coordinate position near zone, and by the defect image near zone image file and accordingly
The defect image exists together in the configuration map file case of the coordinate position near zone of the IC design layout figure
It is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure accordingly indicates described second on the route archives of defect image coordinate position near zone and sits
Mark (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)；
One correction factor (Calibration factor) is provided, is in defect image and lteral data file while will have scarce
It falls into size and defect area is compared with these defects of SEM flaw size and defect area, use and count the correction
The factor；
Execute flaw size correction, be each of defect image data file flaw size is multiplied by the correction because
After son, the flaw size after correction is stored into the storage device；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
Fall into image pattern correction after flaw size and defect area, and by after the correction flaw size and the defect area
It overlaps to the coordinate (X after the correction of the IC design layout pattern2’-X2,Y2’-Y2)；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value.
4. a kind of defect correction method for executing intelligent semiconductor crystal wafer by data processing centre and storage device, special
Sign is:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least wafer coordinate origin, defect coordinate, flaw size, defect area and defect image pattern
Intensity value；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out the position of coordinate origin, each route with respect to a coordinate, line width
And the distance between route；
The first coordinate conversion program is executed, is to obtain one by the data processing centre from the defect image data file
Defect coordinate (the X of defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout pattern
An opposite first coordinate (X2,Y2)；
Execute the first coordinates correction program, comprising:
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing centre
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing centre again
The configuration map file case of corresponding coordinate position near zone, and by the defect image near zone image file and accordingly
The defect image exists together in the configuration map file case of the coordinate position near zone of the IC design layout figure
It is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure accordingly indicates described second on the route archives of defect image coordinate position near zone and sits
Mark (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
The flaw size and defect area of image pattern are fallen into, and the flaw size and the defect area are overlapped to the integrated electricity
Coordinate (X after the correction of road design layout pattern2’-X2,Y2’-Y2)；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value；
Execute a correction program, comprising:
Select at least one described critical defect index value；
One SEM scanning machine is provided, and each defective locations where the critical defect index value selected are swept again
It retouches, to obtain accurately flaw size and a defect area relatively, and stores into the storage device；
The second overlapping program is executed, is to capture accurately flaw size and the defect face relatively by the data processing centre
Product, and accurately defect area overlaps to the IC design layout pattern by described relatively according to the defect coordinate
In one relative coordinate；
The analysis of the second key area is executed, is by the data processing centre according to accurately flaw size and the defect relatively
Area overlaps on the IC design layout pattern, and it is inclined in coordinate to obtain each defect using key area analysis method
The key area of design layout pattern in poor range areas, the critical defect index value after judging a correction, wherein described
Critical defect index value distinguishes multiple and different numerical value.
5. a kind of bearing calibration for executing intelligent semiconductor crystal wafer defect by data processing centre and storage device, special
Sign is:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein defect text and image data file include multiple first defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
One amendment threshold values is provided, is stored in the storage device, wherein the amendment threshold values is the semiconductor factory to every
One defect image coordinate is converted to the amendment statistical value of the relative coordinate position on the deviation range region of defect layout patterns,
The amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation value of coordinate precision；
A correction program is executed, is by the data processing centre according to the amendment threshold values, by each defect video conversion
To the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store into the storage device；
One correction factor is provided, be by defect image and lteral data file and meanwhile have flaw size and defect area with
These defects of SEM flaw size and defect area are compared, and use and count the correction factor；
Execute flaw size correction, be each of defect image data file flaw size is multiplied by the correction because
After son, the flaw size after correction is stored into the storage device；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
Fall into image pattern correction after flaw size and defect area, and by after the correction flaw size and the defect area
It overlaps to the amendment threshold values coordinate in the deviation range region of the IC design layout pattern；
Key area analysis is executed, is to be overlapped by the data processing centre according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value.
6. a kind of bearing calibration for executing intelligent semiconductor crystal wafer defect by data processing centre and storage device, special
Sign is:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein defect text and image data file include multiple first defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
One amendment threshold values is provided, is stored in the storage device, wherein the amendment threshold values is the semiconductor factory to every
One defect image coordinate is converted to the amendment statistical value of the relative coordinate position on the deviation range region of defect layout patterns,
The amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation value of coordinate precision；
A correction program is executed, is by the data processing centre according to the amendment threshold values, by each defect video conversion
To the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store into the storage device；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
Fall into image pattern correction after flaw size and defect area, and by after the correction flaw size and the defect area
It overlaps to the amendment threshold values coordinate in the deviation range region of the IC design layout pattern；
Key area analysis is executed, is to be overlapped by the data processing centre according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value.
7. a kind of bearing calibration for executing intelligent semiconductor crystal wafer defect by data processing centre and storage device, special
Sign is:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein defect text and image data file include multiple first defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
One correction factor is provided, be by defect image and lteral data file and meanwhile have flaw size and defect area with
These defects of SEM flaw size and defect area are compared, and use and count the correction factor；
Execute flaw size correction, be each of defect image data file flaw size is multiplied by the correction because
After son, the flaw size after correction is stored into the storage device；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
Fall into image pattern correction after flaw size and defect area, and by after the correction flaw size and the defect area
It overlaps to the IC design layout pattern；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value.
8. the intelligent semiconductor crystal wafer defect correction method as described in claim the 1st to 7, feature further exist
According to the critical defect exponential size of each defect and the intensity value size of defect image pattern, to defect progress
Classification.
9. the intelligent semiconductor crystal wafer defect correction method as described in claim the 2nd, which is characterized in that more described
Defect classification includes: dummy pattern defect, the defect that is free from risk or critical defect.
10. the intelligent semiconductor crystal wafer defect correction method as described in claim the 3rd, feature further exist
In executing a sampling according to the classification results, including the dummy pattern defect and the defect that is free from risk filtered out.
11. the intelligent semiconductor crystal wafer defect correction method as described in claim the 3rd, feature further exist
In, according to the classification results execute one sampling, be by one setting critical defect index value and setting defect image
The intensity value of pattern is sampled critical defect.
12. a kind of method for executing intelligent semiconductor crystal wafer defect correction by data processing centre and storage device,
It is characterized in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein defect text and image data file include multiple first defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
One amendment threshold values is provided, is stored in the storage device, wherein the amendment threshold values is the semiconductor factory to every
One defect image coordinate is converted to the amendment statistical value of the relative coordinate position on the deviation range region of defect layout patterns,
The amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation value of coordinate precision；
A correction program is executed, is by the data processing centre according to the amendment threshold values, by each defect video conversion
To the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store into the storage device.
13. the method for the intelligent semiconductor crystal wafer defect correction as described in claim the 5th, 6 or 11, feature exist
In the amendment threshold values is by carrying out hand, the side GUI with the defect layout patterns of defect SEM image file and correspondence
Formula or figure compare matching and correlation, obtain multiple grid deviation values, then obtain grid deviation correction parameter with statistical analysis.
14. a kind of correction for executing intelligent semiconductor crystal wafer defect coordinate conversion by data processing centre and storage device
Method, it is characterised in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least wafer coordinate origin, defect coordinate, flaw size, defect area and defect image pattern
Intensity value；
The defect checking machine platform parameter is obtained, is the alignment ginseng for obtaining the defect checking machine platform by the data processing centre
Examine coordinate and unit sizes；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out the position of coordinate origin, each route with respect to a coordinate, line width
And distance and its unit sizes between route；
Light shield parameter configuration files case is obtained, is that reference point, origin, central point and unit ruler are obtained by the data processing centre
It is very little；
Unit sizes are adjusted, are the unit rulers of the unit sizes that will obtain defect image, the IC design layout pattern
Very little and light shield unit sizes are adjusted to unanimously；
Execute a coordinate conversion correction program, be by the data processing centre from the defect image data file, take
Obtain the defect coordinate (X of a defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout
One relative coordinate (X of pattern2,Y2)。
15. the bearing calibration that the intelligent semiconductor crystal wafer defect coordinate as described in claim the 14th is converted, be in
After executing the first coordinate conversion program, which is characterized in that further execute a coordinates correction program, comprising:
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing centre
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing centre again
The route archives of corresponding coordinate position near zone, and it is by the defect image near zone image file and accordingly described scarce
Image is fallen into the route archives of the coordinate position near zone of the IC design layout figure together in the display screen
It is shown on curtain；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure accordingly indicates described second on the route archives of defect image coordinate position near zone and sits
Mark (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)。
16. the bearing calibration that the intelligent semiconductor crystal wafer defect coordinate as described in claim the 15th is converted, special
Sign is, after Yu Suoshu the first coordinates correction program is corrected multiple defect images, obtains the flat of an X-axis and Y-axis
The standard deviation value (Standard Deviation) of equal coordinate precision value and coordinate precision.
17. a kind of correction for executing intelligent semiconductor crystal wafer defect coordinate conversion by data processing centre and storage device
Method, it is characterised in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least wafer coordinate origin, defect coordinate, flaw size, defect area and defect image pattern
Intensity value；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out the position of coordinate origin, each route with respect to a coordinate, line width
And the distance between route；
The first coordinate conversion program is executed, is to obtain one by the data processing centre from the defect image data file
Defect coordinate (the X of defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout pattern
An opposite first coordinate (X2,Y2)；
Execute the first coordinates correction program, comprising:
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing centre
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing centre again
The configuration map file case of corresponding coordinate position near zone, and by the defect image near zone image file and accordingly
The defect image exists together in the configuration map file case of the coordinate position near zone of the IC design layout figure
It is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure is accordingly in the configuration map file case of defect image coordinate position near zone described in mark
Second coordinate (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)。
18. a kind of defect correction method that intelligent semiconductor crystal wafer is executed by data processing centre and storage device,
It is characterized in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least wafer coordinate origin, defect coordinate, flaw size, defect area and defect image pattern
Intensity value；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out the position of coordinate origin, each route with respect to a coordinate, line width
And the distance between route；
The first coordinate conversion program is executed, is to obtain one by the data processing centre from the defect image data file
Defect coordinate (the X of defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout pattern
An opposite first coordinate (X2,Y2)；
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing centre
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing centre again
The line layout road archives of corresponding coordinate position near zone, and by the defect image near zone image file and accordingly
The defect image exists together in the configuration map file case of the coordinate position near zone of the IC design layout figure
It is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure is accordingly in the configuration map file case of defect image coordinate position near zone described in mark
Second coordinate (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)；
One correction factor is provided, be by defect image and lteral data file and meanwhile have flaw size and defect area with
These defects of SEM flaw size and defect area are compared, and use and count the correction factor；
Execute flaw size correction, be each of defect image data file flaw size is multiplied by the correction because
After son, the flaw size after correction is stored into the storage device；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
Fall into image pattern correction after flaw size and defect area, and by after the correction flaw size and the defect area
It overlaps to the coordinate (X after the correction of the IC design layout pattern2’-X2,Y2’-Y2)；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value.
19. a kind of defect correction method that intelligent semiconductor crystal wafer is executed by data processing centre and storage device,
It is characterized in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein the defect text and image data file include multiple defective datas on the wafer, and
Each defective data includes at least wafer coordinate origin, defect coordinate, flaw size, defect area and defect image pattern
Intensity value；
The IC design layout map file case is obtained, is that the IC design cloth is obtained by the data processing centre
Office's map file case, and the data processing centre picks out the position of coordinate origin, each route with respect to a coordinate, line width
And the distance between route；
The first coordinate conversion program is executed, is to obtain one by the data processing centre from the defect image data file
Defect coordinate (the X of defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout pattern
An opposite first coordinate (X2,Y2)；
Execute the first coordinates correction program, comprising:
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing centre
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing centre again
The configuration map file case of corresponding coordinate position near zone, and by the defect image near zone image file and accordingly
The defect image exists together in the configuration map file case of the coordinate position near zone of the IC design layout figure
It is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure is accordingly in the configuration map file case of defect image coordinate position near zone described in mark
Second coordinate (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)。
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
The flaw size and defect area of image pattern are fallen into, and the flaw size and the defect area are overlapped to the integrated electricity
Coordinate (X after the correction of road design layout pattern2’-X2,Y2’-Y2)；
The analysis of the first key area is executed, is by the data processing centre according to the flaw size and the defect area weight
Repeatedly on the IC design layout pattern, each defect is obtained in grid deviation range using key area analysis method
The key area of design layout pattern in region judges a fatal defect index value；
Execute a correction program, comprising:
Select at least one described critical defect index value；
One SEM scanning machine is provided, and each defective locations where the critical defect index value selected are swept again
It retouches, to obtain accurately flaw size and a defect area relatively, and stores into the storage device；
The second overlapping program is executed, is to capture accurately flaw size and the defect face relatively by the data processing centre
Product, and accurately defect area overlaps to the IC design layout pattern by described relatively according to the defect coordinate
In one relative coordinate；
The analysis of the second key area is executed, is by the data processing centre according to accurately flaw size and the defect relatively
Area overlaps on the IC design layout pattern, and it is inclined in coordinate to obtain each defect using key area analysis method
The key area of design layout pattern in poor range areas, the critical defect index value after judging a correction, wherein described
Critical defect index value distinguishes multiple and different numerical value.
20. a kind of bearing calibration that intelligent semiconductor crystal wafer defect is executed by data processing centre and storage device,
It is characterized in that:
One IC design layout map file case is provided, and is stored in the storage device, the IC design layout
Plurality of lines is configured in map file case；
A wafer fabrication schedule is executed, is according to the IC design layout map file case in semiconductor factory by the plural number
Route is formed on the wafer；
Wafer defect scanning is executed, is to scan the wafer by defect checking machine platform to obtain Defect Scanning data, and incite somebody to action
The Defect Scanning data are stored in after the data processing centre is processed into a defect text and image data file
In the storage device, wherein defect text and image data file include multiple first defective datas on the wafer, and
Each defective data includes at least the intensity value of a defect coordinate, a flaw size, defect area and defect image pattern；
One amendment threshold values is provided, is stored in the storage device, wherein the amendment threshold values is the semiconductor factory to every
One defect image coordinate is converted to the amendment statistical value of the relative coordinate position on the deviation range region of defect layout patterns,
The amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation value of coordinate precision；
A correction program is executed, is by the data processing centre according to the amendment threshold values, by each defect video conversion
To the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store into the storage device；
One correction factor is provided, be by defect image and lteral data file and meanwhile have flaw size and defect area with
These defects of SEM flaw size and defect area are compared, and use and count the correction factor；
Execute flaw size correction, be each of defect image data file flaw size is multiplied by the correction because
After son, the flaw size after correction is stored into the storage device；
The first overlapping program is executed, is captured lack one by one by the data processing centre from the defect image data file
Fall into image pattern correction after flaw size and defect area, and by after the correction flaw size and the defect area
It overlaps to the amendment threshold values coordinate in the deviation range region of the IC design layout pattern；
Key area analysis is executed, is to be overlapped by the data processing centre according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value.
21. the bearing calibration that the intelligent semiconductor crystal wafer defect coordinate as described in claim the 17th to 20 is converted,
Wherein, after Yu Suoshu the first coordinates correction program is corrected multiple defect images, being averaged for an X-axis and Y-axis is obtained
Coordinate precision value and standard deviation value (Standard Deviation).Coordinate precision.
22. a kind of defect correcting system of semiconductor crystal wafer, including a storage device, a wafer, which manufactures board group, has a wafer
Board is manufactured, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated electricity
Road design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, uses
With by the line configuring in IC design map file case, on a wafer, the wafer defect detection board is to sweep
The wafer is retouched to obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one
Defect text and image data file are simultaneously stored in the storage device, it is characterised in that:
The data processing equipment obtains the IC design map file case, to pick out in the IC design figure
The opposite coordinate position of each route on archives, between a line width of each route and every two lines road
A distance；
The data processing equipment by capturing an at least defect coordinate in the defect text and image data file one by one, at least
One flaw size and an at least defect area, and the flaw size and the defect area are overlapped according to the defect coordinate
On the opposite coordinate position of each route on to the IC design map file case；
The data processing equipment overlaps according to the flaw size and the defect area in the IC design map file
In case, the key of design layout pattern of each defect in grid deviation range areas is obtained using key area analysis method
At least one defect index value is judged in region；
The data processing equipment selects at least one defect index value, and using a scanning means to described in being chosen to
Each defective locations where defect index value rescaned with after being scanned new flaw size and scanning after
New defect area and the new flaw size after the scanning and the defect area after scanning are stored respectively
In the storage device；And
The data processing equipment to after judging the scanning the flaw size and scanning after the defect area be
No is the system defect of an open type or a short circuit type.
23. one kind partly leads the defect correcting system of wafer, including a storage device, a wafer, which manufactures board group, has a wafer system
Board is made, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated circuit
Design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, to
By the line configuring in IC design map file case on a wafer, the wafer defect detection board is to scan
To obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one to be lacked the wafer
It falls into text and image data file and is stored in the storage device, it is characterised in that:
The data processing equipment obtains a correction factor, is in defect image and lteral data file while will have defect ruler
Very little and defect area is compared with these defects of SEM flaw size and defect area, uses and counts the correction factor；
The data processing equipment executes flaw size correction, is by each of defect image data file defect
After size is multiplied by the correction factor, the flaw size after correction is stored into the storage device；
The data processing equipment executes the first overlapping program, is the flaw size after the correction of acquisition defect image pattern one by one
With defect area, and by after the correction flaw size and the defect area overlap to the IC design layout figure
On the amendment threshold values coordinate in the deviation range region of case；
Key area analysis is executed, is to be overlapped by the data processing centre according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value.
24. one kind partly leads the defect correcting system of wafer, including a storage device, a wafer, which manufactures board group, has a wafer system
Board is made, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated circuit
Design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, to
By the line configuring in IC design map file case on a wafer, the wafer defect detection board is to scan
To obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one to be lacked the wafer
It falls into text and image data file and is stored in the storage device, it is characterised in that:
The data processing equipment captures an amendment threshold values, is stored in the storage device, wherein the amendment threshold values is
The semiconductor factory converts to the relative coordinate on the deviation range region of defect layout patterns each defect image coordinate
The amendment statistical value of position, the amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation of coordinate precision
Value；
The data processing equipment executes a correction program, is according to the amendment threshold values, extremely by each defect video conversion
On the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store into the storage device；
The data processing equipment executes the first overlapping program, is the flaw size after the correction of acquisition defect image pattern one by one
With defect area, and by after the correction flaw size and the defect area overlap to the IC design layout figure
On the amendment threshold values coordinate in the deviation range region of case；
Key area analysis is executed, is to be overlapped by the data processing centre according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value.
25. one kind partly leads the defect correcting system of wafer, including a storage device, a wafer, which manufactures board group, has a wafer system
Board is made, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated circuit
Design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, to
By the line configuring in IC design map file case on a wafer, the wafer defect detection board is to scan
To obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one to be lacked the wafer
It falls into text and image data file and is stored in the storage device, it is characterised in that:
The data processing equipment captures an amendment threshold values, is stored in the storage device, wherein the amendment threshold values is
The semiconductor factory converts to the relative coordinate on the deviation range region of defect layout patterns each defect image coordinate
The amendment statistical value of position, the amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation of coordinate precision
Value；
The data processing equipment executes a correction program, is according to the amendment threshold values, extremely by each defect video conversion
On the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store into the storage device；
The data processing equipment obtains a correction factor, is in defect image and lteral data file while will have defect ruler
Very little and defect area is compared with these defects of SEM flaw size and defect area, uses and counts the correction factor；
The data processing equipment executes flaw size correction, is by each of defect image data file defect
After size is multiplied by the correction factor, the flaw size after correction is stored into the storage device；
The data processing equipment executes the first overlapping program, is the flaw size after the correction of acquisition defect image pattern one by one
With defect area, and by after the correction flaw size and the defect area overlap to the IC design layout figure
On the amendment threshold values coordinate in the deviation range region of case；
Key area analysis is executed, is to be overlapped by the data processing equipment according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value.
26. a kind of defect correcting system of semiconductor crystal wafer, including a storage device, a wafer, which manufactures board group, has a wafer
Board is manufactured, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated electricity
Road design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, uses
With by the line configuring in IC design map file case, on a wafer, the wafer defect detection board is to sweep
The wafer is retouched to obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one
Defect text and image data file are simultaneously stored in the storage device, it is characterised in that:
The data processing equipment captures an amendment threshold values, is that the amendment threshold values is captured from the storage device, wherein institute
Stating amendment threshold values is to convert each defect image coordinate to the relative coordinate on the deviation range region of defect layout patterns
The amendment statistical value of position, the amendment threshold values includes the average coordinates accuracy value of X-axis and Y-axis and the standard deviation of coordinate precision
Value；
The data processing equipment executes a correction program, is by the data processing equipment according to the amendment threshold values, will be every
In one defect video conversion to the amendment threshold values coordinate in the deviation range region of the defect layout patterns, and store extremely
In the storage device.
27. a kind of defect correcting system of semiconductor crystal wafer, including a storage device, a wafer, which manufactures board group, has a wafer
Board is manufactured, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated electricity
Road design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, uses
With by the line configuring in IC design map file case, on a wafer, the wafer defect detection board is to sweep
The wafer is retouched to obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one
Defect text and image data file are simultaneously stored in the storage device, it is characterised in that:
The data processing equipment obtains the parameter of the defect checking machine platform, to obtain alignment reference coordinate and unit ruler
It is very little；
The data processing equipment obtains the IC design layout map file case, is to pick out coordinate origin, each
Route is with respect to the distance and its unit sizes between the position of a coordinate, line width and route；
The data processing equipment obtains a light shield parameter configuration files case, to obtain reference point, origin, central point and unit
Size；
The data processing equipment adjusts unit sizes, is the unit sizes that will obtain defect image, the IC design
The unit sizes of layout patterns and the unit sizes of light shield are adjusted to unanimously；
The data processing equipment executes a coordinate conversion program, is by the data processing equipment from the defect image data
In file, the defect coordinate (X of a defect image pattern is obtained1,Y1), and converted according to the defect coordinate to the integrated electricity
One relative coordinate (X of road design layout pattern2,Y2)。
28. a kind of defect correcting system of semiconductor crystal wafer, including a storage device, a wafer, which manufactures board group, has a wafer
Board is manufactured, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated electricity
Road design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, uses
With by the line configuring in IC design map file case, on a wafer, the wafer defect detection board is to sweep
The wafer is retouched to obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one
Defect text and image data file are simultaneously stored in the storage device, it is characterised in that:
The data processing equipment obtains the IC design layout map file case, to pick out coordinate origin, each
Route is with respect to the distance between the position of a coordinate, line width and route；
The data processing equipment executes the first coordinate conversion program, is obtained from the defect text and image data file
Defect coordinate (the X of one defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout figure
The opposite first coordinate (X of the one of case2,Y2)；
The data processing equipment executes the first coordinates correction program, comprising:
One indicator screen is provided, is attached according to the coordinate position of defect image one defect image of acquirement by data processing equipment
The image file of near field, while the defect image is obtained in the IC design layout figure by data processing equipment again
The configuration map file case of corresponding coordinate position near zone, and by the defect image near zone image file and accordingly
The defect image exists together in the configuration map file case of the coordinate position near zone of the IC design layout figure
It is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure is accordingly in the configuration map file case of defect image coordinate position near zone described in mark
Second coordinate (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)。
29. a kind of defect correcting system of semiconductor crystal wafer, including a storage device, a wafer, which manufactures board group, has a wafer
Board is manufactured, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated electricity
Road design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, uses
With by the line configuring in IC design map file case, on a wafer, the wafer defect detection board is to sweep
The wafer is retouched to obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one
Defect text and image data file are simultaneously stored in the storage device, it is characterised in that:
The data processing equipment obtains the IC design layout map file case, to pick out coordinate origin, each
Route is with respect to the distance between the position of a coordinate, line width and route；
The data processing equipment executes the first coordinate conversion program, be by the data processing equipment from the defect text and
Image data file obtains the defect coordinate (X of a defect image pattern1,Y1), and converted according to the defect coordinate to the collection
At an opposite first coordinate (X of circuit design layout's pattern2,Y2)；
One indicator screen is to obtain area near a defect image according to the coordinate position of defect image by data processing equipment
The image file in domain, while it is corresponding in the IC design layout figure by data processing equipment to obtain the defect image again
Coordinate position near zone configuration map file case, and by the defect image near zone image file and corresponding described
Defect image the coordinate position near zone of the IC design layout figure configuration map file case together described
It is shown on indicator screen；
The data processing equipment is by the defect image position on the defect image near zone image file described
IC design layout figure accordingly indicates described second on the route archives of defect image coordinate position near zone and sits
Mark (X2’,Y2')；
The data processing equipment obtains the coordinate after a correction, is when described first on the IC design layout figure
Coordinate (X2,Y2) and the second coordinate (X2’,Y2') not in same coordinate position, it can be by the Data processing
The heart obtains the coordinate (X after the correction2’-X2,Y2’-Y2)；
The data processing equipment will have simultaneously flaw size and defect area in the defect text and image data file
It is compared with these defects of SEM flaw size and defect area, uses and count a correction factor；
The data processing equipment, which is executed, is multiplied by institute for each of the defect text and image data file flaw size
After stating correction factor, the flaw size after correction is stored into the storage device；
The data processing equipment executes the first overlapping program, is picked one by one from the defect text and image data file
Flaw size and defect area after taking the correction of defect image pattern, and by after the correction flaw size and the defect
Area overlaps to the coordinate (X after the correction of the IC design layout pattern2’-X2,Y2’-Y2)；
The data processing equipment executes the analysis of the first key area, is overlapped according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value；
The data processing centre executes the second overlapping program, is to capture accurately flaw size and the defect area relatively,
And accurately defect area overlaps to the one of the IC design layout pattern by described relatively according to the defect coordinate
In relative coordinate；
The data processing equipment heart executes the analysis of the second key area, is according to accurately flaw size and the defect relatively
Area overlaps on the IC design layout pattern, and it is inclined in coordinate to obtain each defect using key area analysis method
The key area of design layout pattern in poor range areas, the critical defect index value after judging a correction, wherein described
Critical defect index value distinguishes multiple and different numerical value.
30. a kind of defect correcting system of semiconductor crystal wafer, including a storage device, a wafer, which manufactures board group, has a wafer
Board is manufactured, a wafer defect detects board and a data processing equipment, wherein the storage device is to store an integrated electricity
Road design drawing archives, and plurality of lines is configured in the IC design map file case, the wafer manufactures board group, uses
With by the line configuring in IC design map file case, on a wafer, the wafer defect detection board is to sweep
The wafer is retouched to obtain a Defect Scanning data, the data processing equipment has the Defect Scanning data conversion at one
Defect text and image data file are simultaneously stored in the storage device, it is characterised in that:
The data processing equipment obtains the IC design layout map file case, to pick out coordinate origin, each
Route is with respect to the distance between the position of a coordinate, line width and route；
The data processing equipment executes the first coordinate conversion program, is taken from the defect text and image data file
Obtain the defect coordinate (X of a defect image pattern1,Y1), and converted according to the defect coordinate to the IC design layout
The opposite first coordinate (X of the one of pattern2,Y2)；
The data processing equipment executes the first coordinates correction program, comprising:
One indicator screen is provided, is that one defect shadow is obtained according to the coordinate position of defect image by the data processing equipment
The defect image is obtained in the IC design cloth by data processing centre as the image file of near zone, while again
Office schemes the configuration map file case of corresponding coordinate position near zone, and by the defect image near zone image file and
Configuration map file case one of the corresponding defect image in the coordinate position near zone of the IC design layout figure
It rises and is shown on the indicator screen；
One second coordinate is indicated, is by the defect image position on the defect image near zone image file described
IC design layout figure accordingly indicates described second on the route archives of defect image coordinate position near zone and sits
Mark (X2’,Y2')；
Coordinate after obtaining a correction is as the first coordinate (X on the IC design layout figure2,Y2) with it is described
Second coordinate (X2’,Y2') coordinate (X not in same coordinate position, after the correction can be obtained2’-X2,Y2’-Y2)；
The data processing equipment executes the first overlapping program, is picked one by one from the defect text and image data file
The flaw size and defect area of defect image pattern are taken, and the flaw size and the defect area are overlapped to the collection
At the coordinate (X after the correction of circuit design layout's pattern2’-X2,Y2’-Y2)；
The data processing equipment executes the analysis of the first key area, is overlapped according to the flaw size and the defect area
On the IC design layout pattern, each defect is obtained in grid deviation range area using key area analysis method
The key area of design layout pattern in domain judges a fatal defect index value；
The data processing equipment executes a correction program, comprising:
Select at least one described critical defect index value；
One SEM scanning machine is provided, and each defective locations where the critical defect index value selected are swept again
It retouches, to obtain accurately flaw size and a defect area relatively, and stores into the storage device；
The second overlapping program is executed, is to capture accurately flaw size and the defect face relatively by the data processing equipment
Product, and accurately defect area overlaps to the IC design layout pattern by described relatively according to the defect coordinate
In one relative coordinate；
The analysis of the second key area is executed, is by the data processing equipment according to accurately flaw size and the defect relatively
Area overlaps on the IC design layout pattern, and it is inclined in coordinate to obtain each defect using key area analysis method
The key area of design layout pattern in poor range areas, the critical defect index value after judging a correction, wherein described
Critical defect index value distinguishes multiple and different numerical value.
31. the defect correcting system of the semiconductor crystal wafer as described in claim the 24th to 30, which is characterized in that in institute
It states after the first coordinates correction program is corrected multiple defect images, obtains the average coordinates accuracy value of an X-axis and Y-axis
And the standard deviation value (Standard Deviation) of coordinate precision.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110680060.2A CN113361225A (en) | 2017-10-05 | 2017-11-07 | Intelligent coordinate conversion correction method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106134392 | 2017-10-05 | ||
| TW106134392A TWI692700B (en) | 2017-10-05 | 2017-10-05 | Smart defect calibration system and the method thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110680060.2A Division CN113361225A (en) | 2017-10-05 | 2017-11-07 | Intelligent coordinate conversion correction method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109616426A true CN109616426A (en) | 2019-04-12 |
| CN109616426B CN109616426B (en) | 2021-07-09 |
Family
ID=66002145
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110680060.2A Pending CN113361225A (en) | 2017-10-05 | 2017-11-07 | Intelligent coordinate conversion correction method |
| CN201711086885.1A Active CN109616426B (en) | 2017-10-05 | 2017-11-07 | Intelligent defect correction system and implementation method thereof |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110680060.2A Pending CN113361225A (en) | 2017-10-05 | 2017-11-07 | Intelligent coordinate conversion correction method |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN113361225A (en) |
| TW (1) | TWI692700B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690136A (en) * | 2019-10-12 | 2020-01-14 | 上海华力微电子有限公司 | Defect detection method and system |
| CN111429427A (en) * | 2020-03-20 | 2020-07-17 | 上海集成电路研发中心有限公司 | Priority ranking device, ranking method and storage medium for detecting object defect patterns |
| CN111863646A (en) * | 2019-04-24 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting defects of semiconductor device |
| CN112684314A (en) * | 2019-10-18 | 2021-04-20 | 捷普电子(广州)有限公司 | Defect information display method and system of circuit board |
| CN114152615A (en) * | 2021-10-12 | 2022-03-08 | 宏华胜精密电子(烟台)有限公司 | Detection method, device and equipment of circuit board detection equipment and storage medium |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7203678B2 (en) * | 2019-04-19 | 2023-01-13 | 株式会社日立ハイテク | Defect observation device |
| TWI722861B (en) * | 2020-04-08 | 2021-03-21 | 晶碩光學股份有限公司 | Classification method and a classification system |
| US11295831B2 (en) * | 2020-06-25 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company Limited | Systems and methods to detect cell-internal defects |
| CN114462347B (en) * | 2022-01-21 | 2023-02-24 | 深圳市亿道电子科技有限公司 | Auxiliary drawing system and method for circuit design software based on altium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102435629A (en) * | 2011-11-28 | 2012-05-02 | 上海华力微电子有限公司 | Detection method of scanning electron microscope |
| US8312401B2 (en) * | 2011-01-13 | 2012-11-13 | Elitetech Technology Co., Ltd. | Method for smart defect screen and sample |
| CN103185730A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Method for building rule of thumb of defect classification, and methods for classifying defect and judging killer defect |
| CN103187343A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Intelligent defect diagnosis method |
| US20140061456A1 (en) * | 2012-08-30 | 2014-03-06 | Kabushiki Kaisha Toshiba | Coordinate correcting method, defect image acquiring method and electron microscope |
| CN104870985A (en) * | 2012-12-28 | 2015-08-26 | 株式会社日立高新技术 | Defect observation method and defect observation device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142355B (en) * | 2010-02-02 | 2013-07-17 | 吕一云 | Application method of object manufacture defect |
| US9401313B2 (en) * | 2014-11-19 | 2016-07-26 | Deca Technologies, Inc. | Automated optical inspection of unit specific patterning |
| TWM549447U (en) * | 2016-11-23 | 2017-09-21 | Scientech Corp | Substrate alignment and inspection device, and substrate processing machine |
-
2017
- 2017-10-05 TW TW106134392A patent/TWI692700B/en active
- 2017-11-07 CN CN202110680060.2A patent/CN113361225A/en active Pending
- 2017-11-07 CN CN201711086885.1A patent/CN109616426B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8312401B2 (en) * | 2011-01-13 | 2012-11-13 | Elitetech Technology Co., Ltd. | Method for smart defect screen and sample |
| CN102435629A (en) * | 2011-11-28 | 2012-05-02 | 上海华力微电子有限公司 | Detection method of scanning electron microscope |
| CN103185730A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Method for building rule of thumb of defect classification, and methods for classifying defect and judging killer defect |
| CN103187343A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Intelligent defect diagnosis method |
| US20140061456A1 (en) * | 2012-08-30 | 2014-03-06 | Kabushiki Kaisha Toshiba | Coordinate correcting method, defect image acquiring method and electron microscope |
| CN104870985A (en) * | 2012-12-28 | 2015-08-26 | 株式会社日立高新技术 | Defect observation method and defect observation device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863646A (en) * | 2019-04-24 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting defects of semiconductor device |
| CN110690136A (en) * | 2019-10-12 | 2020-01-14 | 上海华力微电子有限公司 | Defect detection method and system |
| CN112684314A (en) * | 2019-10-18 | 2021-04-20 | 捷普电子(广州)有限公司 | Defect information display method and system of circuit board |
| CN111429427A (en) * | 2020-03-20 | 2020-07-17 | 上海集成电路研发中心有限公司 | Priority ranking device, ranking method and storage medium for detecting object defect patterns |
| WO2021184526A1 (en) * | 2020-03-20 | 2021-09-23 | 上海集成电路研发中心有限公司 | Priority ranking device and method for detection object defect pattern, and storage medium |
| CN114152615A (en) * | 2021-10-12 | 2022-03-08 | 宏华胜精密电子(烟台)有限公司 | Detection method, device and equipment of circuit board detection equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI692700B (en) | 2020-05-01 |
| TW201915792A (en) | 2019-04-16 |
| CN109616426B (en) | 2021-07-09 |
| CN113361225A (en) | 2021-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11761904B2 (en) | Smart defect calibration system in semiconductor wafer manufacturing | |
| CN109616426A (en) | Intelligent defect correcting system and its implementation method | |
| TWI671838B (en) | Semiconductor fab's defect operating system and apparatus | |
| CN106415807B (en) | Tested using the naked picture data of high-resolution | |
| JP5405453B2 (en) | Method and apparatus for locating inspection data in the design data area | |
| TWI515813B (en) | Charged particle - ray device | |
| US7593565B2 (en) | All surface data for use in substrate inspection | |
| TWI606235B (en) | Methods, inspection systems and computer readable media for inspecting a photolithographic reticle | |
| JP5444092B2 (en) | Inspection method and apparatus | |
| CN113763312B (en) | Detection of defects in semiconductor samples using weak labels | |
| CN112053318A (en) | Two-dimensional PCB defect real-time automatic detection and classification device based on deep learning | |
| CN103748670A (en) | Region setting device, observation device or inspection device, region setting method, and observation method or inspection method using region setting method | |
| WO2005008548A1 (en) | Method of transmitting cad data to a wafer inspection system | |
| JP2009206453A (en) | Manufacturing process monitoring system | |
| US6687633B2 (en) | Inspection system, inspection apparatus, inspection program, and production method of semiconductor devices | |
| CN110727247B (en) | Defect operation system and device for semiconductor factory | |
| TW201909010A (en) | Design and layout-based fast online defect diagnosis, classification and sampling method and system | |
| CN107924850A (en) | Self orientation is measured and pattern classification | |
| JP4073088B2 (en) | Manufacturing method of semiconductor substrate | |
| JP3722757B2 (en) | Defect imaging device | |
| CN117529803A (en) | Manufacturing fingerprints for active yield management |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |