CN109616426B

CN109616426B - Intelligent defect correction system and its implementation method

Info

Publication number: CN109616426B
Application number: CN201711086885.1A
Authority: CN
Inventors: 吕一云
Original assignee: Elite Semiconductor Inc
Current assignee: Elite Semiconductor Inc
Priority date: 2017-10-05
Filing date: 2017-11-07
Publication date: 2021-07-09
Anticipated expiration: 2037-11-07
Also published as: CN113361225B; CN109616426A; TW201915792A; CN113361225A; TWI692700B

Abstract

The present invention provides an intelligent semiconductor defect correction system and its implementation method. The method includes: receiving a plurality of defect data sent by a manufacturing factory, receiving IC design layout data from an integrated circuit design company, and analyzing the plurality of defect data After performing defect coordinate conversion correction and defect image correction, use critical area analysis to analyze the corrected defect data and design layout graphics to improve the accuracy of critical area analysis and accurately determine whether each defect image causes open or short-circuit failure. Fatal defect index; then, according to the fatal defect index and defect signal parameters, the fatal defects are classified into high-risk defects, medium-risk defects and low-risk defects, etc., so as to improve the accuracy of the intelligent defect correction system and its implementation method and accurately identify fatal defects. Purpose.

Description

Intelligent defect correction system and implementation method thereof

Technical Field

The present invention relates to an intelligent semiconductor defect correction, classification and sampling system and its implementation method; more particularly, the present invention relates to an intelligent defect correction, classification and sampling system and method for semiconductor manufacturing plants, semiconductor package manufacturing plants, flat panel display manufacturing plants, solar panel manufacturing plants, printed circuit manufacturing plants, mask manufacturing plants, LED manufacturing or assembly plants.

Background

Generally, Integrated Circuits (ICs) are manufactured and manufactured in a factory through equipment and processes such as masking, photolithography, etching, thin film deposition, copper processing, chemical mechanical polishing, and multiple exposure. Therefore, during the whole manufacturing process, Random and systematic defects (Random and systematic defects) may be generated due to the precision deviation of the equipment itself, abnormal faults, particles generated by the process, drawing defects of the design layout, and insufficient yellow light process window (window), which cause open or short type failures of the product, thereby reducing the wafer yield. As the size of the semiconductor process is scaled down, the number of defects is greatly increased due to the size reduction, so that thousands of defects are detected in each defect detection, which is limited by the photographing rate of a Scanning Electron Microscope (SEM), and only tens to hundreds of defects can be selected in a sampling manner to photograph, so that the difficulty of sampling defects that are truly open-circuited or short-circuited is greatly increased, and thus, the SEM photographs of the defects causing yield loss cannot be accurately provided to the process engineer in real time, and it is difficult to analyze the source of the defects in the process according to the SEM photographs of the defects, so that the yield of the defects is improved, and the cost of the semiconductor factory is increased.

In the practical operation of semiconductor factories (e.g., Foundry), the data analysis of defect and image pattern classification in real-time (real-time) has been an important method for improving yield in the past, but it is very difficult to find the failed critical defect in the defect analysis of nano-scale semiconductor process; the core part of the innovation is introduced with IC design layout data, Critical Area Analysis (CAA) method, defect pattern overlay design layout, coordinate transformation correction system, and defect size correction system, which are important breakthrough methods and systems for solving the sampling Critical defect.

Moreover, the image profile measurement data of the SEM and the optical microscope and the defect data generated by the inspection machine are compared with the critical area analysis data, and the defect size and area data of the inspection machine and the image profile measurement size and area data of the SEM and the optical microscope are different, so that the critical area analysis result is different, and in order to solve the critical area analysis deviation, the problem of defect size deviation must be solved. For example, the defect size measurement unit of the defect inspection machine is higher than the minimum size of the layout pattern, which causes the deviation problem between the size of the defect data and the actual defect size of the SEM image.

In addition, in the advanced process of sophisticated semiconductor device, especially when the process window (process window) is getting narrower and the layout pattern of the IC design is increased and complicated by multiple times, some defects related to the pattern are detected, wherein the defect that affects the yield is the "" systematic defect "", which results in a very low yield, but if the pattern does not affect the IC design circuit, such as the monitor pattern, because the yield is not affected, i.e., the pattern belongs to the "" False defect "" (False defect), but because the False defect pattern and signal are obvious, the defect sampling number of the most part is usually up to 90%, and on the contrary, the defect pattern with open circuit or short circuit failure cannot be found really.

Finally, in the Defect sampling part, except for the patent number US8312401B2 approved by the same inventor in 2012, a critical area analysis method is used to obtain the critical area of the design layout pattern in the Defect size and coordinate deviation range of each Defect, and the probability value of the Defect with open circuit or short circuit type failure, i.e. the fatal Defect Index (KDI), i.e. CAA value, is calculated; however, the accuracy of the control motor for the wafer carried by the defect inspection machine is not taken into account when calculating the critical defect index (KDI), for example, when the coordinate accuracy unit of the wafer moved by the defect inspection machine is controlled to be plus or minus W, for example, W is equal to 0.05 micron, so that the dimension of the wafer can be detected to be a multiple of plus or minus 0.05 micron; therefore, the size of the detected defect image may be larger than the actual size, which may cause a problem of high fatal defect index.

Therefore, based on the above considerations, it is an object of the present invention to overcome the above limitations to improve the mass production efficiency of the manufacturing plant.

Disclosure of Invention

The invention mainly aims to input a coordinate correction threshold and a correction factor (Calibration factor) of defect size aiming at a deviation value caused by a defect detection machine by using an IC design layout diagram and a key area analysis method, correct the coordinate of the defect data content of the defect detection machine and the deviation value of the defect size in real time, combine with the IC design layout data, overlap a plurality of defect graphs to a plurality of corresponding defect layout patterns one by one, and obtain a fatal defect index (KDI) by using a key area analysis method. The invention uses the precisely adjusted coordinates and defect layout graph and combines a defect size value with higher accuracy, so that a more precise fatal defect index can be generated, and the probability of open circuit or short circuit type failure defect can be analyzed more accurately and misjudgment can be reduced, thereby becoming an important tool for judging whether each defect belongs to Non-fatal defect (Non-fatal defect) or fatal defect (Killer defect).

In accordance with the above objects, the present invention provides a defect correction system for semiconductor wafers, comprising a storage device, a wafer manufacturing machine set, a wafer defect inspection machine and a data processing device, wherein the storage device is used for storing a design layout, and a plurality of circuits are configured in the design layout, the wafer manufacturing machine set is used for configuring the plurality of circuits in the design layout on the wafer, the wafer defect inspection machine is used for scanning the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defect text and image data and stores the file in the storage device, characterized in that the data processing device retrieves a coordinate correction threshold, which is a coordinate correction threshold retrieved from the storage device, wherein the coordinate correction threshold is a statistical value of relative coordinate position correction in a deviation range region of each defect image coordinate converted into a defect layout pattern, the coordinate correction threshold value comprises an average coordinate precision value of an X axis and a Y axis and a standard deviation value of the coordinate precision; the data processing device executes a correction program, converts each defect image to the coordinate correction threshold of the deviation range area of the defect layout pattern according to the coordinate correction threshold, and stores the coordinate correction threshold into the storage device.

In accordance with the above objects, the present invention provides a defect correction system for a semiconductor wafer, comprising a storage device, a wafer manufacturing station set, a wafer defect inspection station and a data processing device, wherein the storage device is used for storing a design layout, and a plurality of circuits are configured in the design layout, the wafer manufacturing station set is used for configuring the plurality of circuits in the design layout on the wafer, the wafer defect inspection station is used for scanning the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defect text and image data and stores the file in the storage device, characterized in that the data processing device retrieves a coordinate correction threshold value, which is stored in the storage device, wherein the coordinate correction threshold value is a statistical value of relative coordinate position correction of each defect image coordinate converted to a deviation range region of the defect layout pattern by a semiconductor manufacturer, the coordinate correction threshold value comprises an average coordinate precision value of an X axis and a Y axis and a standard deviation value of the coordinate precision; the data processing device executes a correction program, converts each defect image to a correction threshold value coordinate of a deviation range area of the defect layout pattern according to the coordinate correction threshold value, and stores the correction threshold value coordinate into the storage device; the data processing device obtains a correction factor, and compares the defects with defect size and defect area and SEM defect size and SEM defect area in the defect text and image data file to calculate the correction factor; the data processing device executes defect size correction, namely, after multiplying each defect size in the defect character and image data file by a correction factor, storing the corrected defect size into the storage device; the data processing device executes a first overlapping program, namely, the defect coordinates, the defect size and the defect area of the pattern of the defect image are captured one by one, and the corrected defect size and the corrected defect area are overlapped to the coordinate correction threshold value of the deviation range area of the design layout according to the defect coordinates; and performing critical area analysis, namely, obtaining the critical area of the design layout diagram of each defect in the coordinate deviation range area by using a critical area analysis method according to the fact that the defect size and the defect area are overlapped on the design layout diagram by the data processing device, and judging the fatal defect index value.

Another objective of the present invention is to provide a coordinate transformation correction system, a defect size correction system and an implementation method thereof, which can improve the accuracy of critical area analysis and accurately identify fatal defects. Using the original defect data and IC design layout data of the defect inspection machine, and inputting the coordinate deviation correction value by the coordinate conversion correction system, so as to reduce the coordinate deviation generated by the wafer process optical effect to expose the rectangular pattern into the circular arc pattern and convert the defect coordinate into the actual layout pattern coordinate; meanwhile, a correction system, a statistical method and measurement uncertainty analysis of the defect size are introduced, the original defect data of the defect detection machine is corrected to approximate the size of the outline of the defect image, the deviation of the size and the area of the defect data and the actual defect size and the area of an SEM photo caused by the fact that the measurement unit of the defect detection machine is higher than the minimum size of a layout graph is solved, and the analysis accuracy of a key area and the accuracy of judging fatal defect analysis are improved.

In accordance with the above objects, the present invention provides a defect correction system for semiconductor wafers, comprising a storage device, a wafer manufacturing machine set, a wafer defect inspection machine and a data processing device, wherein the storage device is used for storing a design layout, and a plurality of circuits are configured in the design layout; the data processing device captures at least one defect coordinate, at least one defect size and at least one defect area one by one from the defect text and image data file, and overlaps the defect size and the defect area to the relative coordinate position of each line on the design layout according to the defect coordinate; the data processing device uses a key region analysis method to obtain a key region of the design layout diagram of each defect in a coordinate deviation range region according to the defect size and the defect area overlapped on the design layout diagram, and judges at least one fatal defect index value; the data processing device selects at least one fatal defect index value, and utilizes the scanning device to re-scan each defect position where the selected fatal defect index value is located so as to obtain a scanned new defect size and a scanned new defect area, and respectively stores the scanned new defect size and the scanned new defect area in the storage device; and the data processing device is used for judging whether the size of the scanned new defect and the area of the scanned new defect are open circuit type or short circuit type system defects.

In accordance with the above objects, the present invention further provides a defect correction system for semiconductor wafers, which comprises a storage device, a wafer fabrication tool set, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout, and the design layout has a plurality of circuits, and the wafer fabrication tool set is used to manufacture a wafer with a plurality of circuitsThe data processing device obtains the design layout drawing and is used for identifying a coordinate origin, the position of each line relative to a coordinate, the line width and the distance between the lines; the data processing device executes a first coordinate conversion program to obtain the defect coordinates (X) of the defect image pattern from the defect text and image data file₁,Y₁) And based on the defect coordinates (X)₁,Y₁) Conversion to relative first coordinates (X) of the design layout₂,Y₂) (ii) a Providing a display screen, wherein the data processing device acquires an image file of a region near a defective image according to the coordinate position of the defective image, and simultaneously acquires an image file of the defective image in the region near the corresponding coordinate position of the design layout drawing by the data processing device, and the image file of the region near the defective image and the image file of the corresponding defective image in the region near the coordinate position of the design layout drawing are displayed on the display screen together; marking the second coordinate (X) by marking the position of the defective image on the image file in the area near the position of the defective image coordinate corresponding to the design layout diagram₂’,Y₂') to a host; obtaining a corrected coordinate deviation (X)₂’-X₂,Y₂’-Y₂) Is the first coordinate (X) on the integrated circuit design layout₂,Y₂) And the second coordinate (X)₂’,Y₂') is not at the same coordinate position, the corrected coordinate deviation amount (X) can be obtained₂’-X₂,Y₂’-Y₂)。

Another objective of the present invention is to provide a method for defect sampling based on design layout data and critical area analysis. The system and method combines a key area analysis method to obtain a selection judgment parameter of a defect sample with a fatal defect index as a main part, adds a defect intensity value/contrast value/polarity analysis value in a graph of an image analysis method to be a selection judgment parameter of a second defect sample, and judges whether a false defect exists or not to select a selection judgment parameter of a third defect sample, so as to provide the most effective method for selecting open circuit or short circuit type failure defect samples.

In accordance with the above objects, the present invention further provides a defect correction system for semiconductor wafers, comprising a storage device, a wafer manufacturing machine set, a wafer defect inspection machine and a data processing device, wherein the storage device is used for storing a design layout, the design layout is configured with a plurality of circuits, the wafer manufacturing machine set is used for configuring the plurality of circuits in the design layout on the wafer, the wafer defect inspection machine is used for scanning the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defect text and image data and stores the file in the storage device, and is characterized in that the data processing device obtains the design layout for identifying an origin of coordinates, a position of each circuit relative to a coordinate, a circuit width and a distance between circuits; the data processing device executes a first coordinate conversion program to obtain the defect coordinates (X) of the defect image pattern from the defect text and image data file₁,Y₁) And converted to a relative first coordinate (X) of the design layout according to the defect coordinates₂,Y₂) (ii) a Providing a display screen, wherein the data processing device acquires an image file of a region near a defective image according to the coordinate position of the defective image, and simultaneously acquires an image file of a region near the corresponding coordinate position of the defective image in the design layout by the data processing center, and the image file of the region near the defective image and the image file of the region near the corresponding coordinate position of the defective image in the design layout are displayed on the display screen together; marking the second coordinate (X) by marking the defective image position on the image file of the area near the defective image coordinate position corresponding to the design layout diagram₂’,Y₂’)；The corrected coordinates are obtained as the first coordinates (X) on the design layout₂,Y₂) And the second coordinate (X)₂’,Y₂') is not at the same coordinate position, the corrected coordinate deviation amount (X) can be obtained₂’-X₂,Y₂’-Y₂) (ii) a The data processing device executes a first overlapping program, which is to capture the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data file, and overlap the defect size and defect area to the corrected coordinate deviation (X) of the design layout according to the defect coordinates₂’-X₂,Y₂’-Y₂) (ii) a The data processing device executes a first key area analysis, namely, a key area of the design layout diagram of each defect in a coordinate deviation range area is obtained by using a key area analysis method according to the overlapping of the defect size and the defect area on the design layout diagram, and a fatal defect index value is judged; the data processing device executes a correction program, including selecting at least one fatal defect index value; providing an SEM scanner, rescanning each defect position where the selected fatal defect index value is located to obtain relatively accurate defect size and defect area, and storing the defect size and defect area into a storage device; executing a second overlapping program, namely capturing the relatively accurate defect size and the accurate defect area by the data processing device, and overlapping the relatively accurate defect area to the relative coordinate of the design layout according to the defect coordinate; and executing a second critical area analysis, namely, overlapping the relatively accurate defect size and the accurate defect area on the design layout by the data processing device, obtaining the critical area of the design layout of each defect in the coordinate deviation range area by using a critical area analysis method, and judging a corrected critical defect index value, wherein the corrected critical defect index value is different in a plurality of values.

Drawings

FIG. 1 is a schematic diagram of the operation structure of the intelligent defect correction, classification and sampling system of the present invention.

FIG. 2 is a flow chart of the "intelligent system" of the present invention.

FIG. 3A is a schematic diagram of an intelligent system according to the present invention for obtaining a design layout.

FIG. 3B is a schematic diagram of an intelligent system for acquiring defect data according to the present invention.

FIG. 3C is a schematic diagram of the design layout of the "intelligent system" and the coordinate transformation of defect data according to the present invention.

FIG. 4 is a flowchart illustrating the correction of the coordinate transformation and the deviation correction of the design layout according to the defect of the present invention.

Fig. 5 is a flow chart of coordinate transformation for resizing according to the present invention.

Fig. 6A, 6B, and 6C to 6D are diagrams illustrating a plurality of embodiments of the present invention for providing an accurate coordinate deviation correction amount.

Fig. 7A to 7E are diagrams illustrating a plurality of embodiments of capturing defect contours and overlapping the defect contours to defect coordinate locations on a design layout according to the present invention.

Fig. 8A and 8B are flow charts of the present invention for establishing a defect size and area correction system.

Fig. 8C is a defect size table in which the original defect size is corrected by the defect image file having a high resolution according to the present invention.

FIG. 9 is a flowchart of a polygon matching analysis of the defect outline and layout pattern according to the present invention.

FIG. 10 is a defect classification flow chart of the present invention.

FIGS. 11A-11G are defect map databases of the present invention.

Step 110 to step 190

Step 200

Step 300

Step 500

Wafer 10

Chip layout 11

Crystal grains 11D 1, 11D 2, 11D 3

Foundry 20

Data processing center 21

Memory unit 23

Antenna 24

Antenna 34

Integrated Circuit design company 30

Data processing center 31

Memory cell 33

Display screen 51

Defect pattern 1001

Defective image 1101

Line 1102

Defective image 1103

Correcting defective image 1104

Correcting polygonal defect image 1105

Design layout pattern 1110

Defect 1101

Defect layout pattern 1111

Line 1113

Defect text and image data file 1130

Detailed Description

In semiconductor manufacturing plants, semiconductor package manufacturing plants, flat panel display manufacturing plants, solar panel manufacturing plants, printed circuit manufacturing plants, mask manufacturing plants, LED manufacturing or assembly plants, it is necessary to form products with specific functionality through equipment and processing methods such as masking, semiconductor lithography, etching and thin film deposition; due to the numerous and complicated steps in the manufacturing process, the control of process and equipment parameters, equipment parameter deviations, or technical bottlenecks all cause defects that affect the yield of the product, and the generation of these defects is inevitable. Therefore, in the semiconductor manufacturing process, the defect detection and analysis are performed to improve the yield and reduce the cost.

First, please refer to fig. 1, which is a schematic diagram illustrating an operation structure of the intelligent defect correction, classification and sampling system of the present invention. As shown in fig. 1, the embodiment of the present invention will be described by taking wafer fabrication as an example, and in the following description, an "intelligent system" will be used to replace the "intelligent defect correction system and its implementation method". Generally, the intelligent system may be implemented in the foundry 20 (hereinafter referred to as the "fab side 20"), in the integrated circuit design company 30 (hereinafter referred to as the "design company side 30"), or in both the fab side 20 and the design company side 30 via a wired network or via the antenna 24/34 and a wireless network.

For example, when the design company 30 finishes an integrated circuit IC design layout (IC design layout) with a specific function, the data processing center 31 stores the GDS or OASIS file of the design layout into the memory unit 33; then, the GDS or OASIS file can be transmitted to the factory end 20 through the wired network or the wireless network; the design layout pattern 1110 (shown in fig. 3A) includes a plurality of layout patterns (e.g., layout of components), and each layout polygon includes a layout size, a layout coordinate, a layout Layer (Layer), a text label or a size; generally, the format of the design layout pattern 1110 may be a Graphic Database System (GDS) format, a GDS-II format, or an Open Access time Information System (OASIS) format. Then, the factory side 20 processes the received file through the data processing center 21 and stores the processed file in the memory unit 23. Thereafter, the fab 20 performs the related semiconductor process according to the mask manufactured by the design layout pattern 1110 to manufacture a plurality of repeated dies 11D (shown in fig. 3B) on the wafer 10. In general, the factory side 20 uses the files of the design company side 30 when manufacturing semiconductor chips.

During the fabrication of the wafer 10, defects may be generated on the wafer 10 during various processes of the fabrication, such as random defects (random defects) or systematic defects (systematic defects). Therefore, the factory side 20 scans and inspects the defects of the wafers 10 by using a defect inspection machine, such as a Scanning Electron Microscope (SEM), an electron beam (E-beam) inspection machine, an optical inspection machine, a defect scanner or a camera, at any stage or at a plurality of process steps during the manufacturing process, and generates original defect scan data of the wafers; the defect scan data includes the size, shape, area, grain position, coordinates or graphics of the defect), and the defect data is processed by the data processing center 21 into a defect text and image data file 1130 (shown in fig. 3B) with JPG, TIFF, PNG and text specifications and then stored in the memory unit 23.

From the above, it is obvious that the memory unit 23 of the factory side 20 has stored therein the design layout file 1110 of the design company side 30 and the defect text and image data file 1130. Therefore, the intelligent system of the present invention can perform defect correction, classification and sampling operations at the factory 20. Similarly, if the factory side 20 transmits the defect text and image data file 1130 to the design company side 30 via a wired network or a wireless network, the "intelligent system" of the present invention can perform the operations of defect correction, classification, and sampling at the design company side 30. Of course, the factory side 20 and the design company side 30 can exchange related files in real time through a wired network or a wireless network to perform defect correction, classification, and sampling in real-time analysis (real-time analysis). The invention is not limited by who performs the defect correction, classification, and sampling operations.

Referring to fig. 2, a flow chart of the "intelligent system" of the present invention is shown. Referring to FIG. 2, the flow chart 100 of the "intelligent system" of the present invention begins with the data processing center 21 obtaining a design layout 1110 and obtaining a defect text and image data file 1130, as shown in steps 110 and 120; next, in step 130, coordinate transformation and deviation correction (deviation correction) are performed on the obtained design layout 1110 and the defect text and image data file 1130 to transform the defect coordinate position on the wafer 10 to the corresponding coordinate position of the design layout, so as to determine that the defect image 1101 falls on the coordinate positions of the design layout 1110; then, in step 140, the outline (contour) of each defective image 1101 is overlapped (superimposed) or mapped (mapped) to the coordinate position of the defective layout pattern 1111 corresponding to each defective image 1101 on the design layout 1110; then, a Critical Defect Index (KDI) is determined in step 150, wherein the Critical Defect Index (KDI) is determined according to the coordinate position of each overlapped or mapped Defect image 1101 of step 140, and then a Critical Area Analysis (CAA) method is used to analyze the Critical Area (Critical Area) on the design layout diagram where the outline size of the Defect image 1101 is within the Area having the Defect position and the deviation range; meanwhile, the overlapping result of the contour of the defect image 1101 and at least two layout patterns may be checked in step 160, and the intersection result of the contour of the defect image 1101 and at least one layout pattern may be checked. Then, the defect classification of step 170 is performed according to the determination result of step 150 or step 160, and based on the fatal defect index (KDI) of the defect, the defect signal parameter (defect signal parameter), the pattern matching (pattern match) result of the defect and defect pattern data file (defect pattern library), and the pattern matching result of the defect and high failure frequency defect database (frequency failure defect library), wherein the defect pattern data file (defect pattern library) and the high failure frequency defect library (frequency failure defect library) can be obtained from the memory unit 23/33 (as step 180); or, classifying the defects according to the short circuit or open circuit result of the layout pattern intersection; finally, the defect sampling in step 190 is performed according to the defect classification and defect sampling rules in step 170.

Next, an embodiment of each step in the flowchart 100 of the "intelligent system" is described in detail. First, the design layout acquired in step 110 is processed mainly according to the design layout 1110 completed by the design company 30. Referring to FIG. 3A, a schematic diagram of an intelligent system for obtaining a design layout according to the present invention is shown. As shown in FIG. 3A, a user (e.g., an engineer at the design company end 30) retrieves a design layout 1110 from the data processing center 31 in advance; the format (format) of the design layout 1110 may be a GDS format, a GDS-II format, or an OASIS format.

Referring to fig. 3B, a diagram of an intelligent system for acquiring defect data according to the present invention is shown. As described above, after the design layout 1110 has been designed by the design company 30 and provided to the fab 20, the fab 20 may form a pattern having a full-chip layout 11 on the wafer 10 during the manufacturing process, and the full-chip layout 11 includes a plurality of dies (die), such as 11D 1, 11D 2, 11D 3. Then, the factory 20 uses a defect inspection machine to scan and inspect the defects of the wafer 10, so as to obtain the files and the defect text data of a plurality of defect images 1101 on the chip layout 11; thereafter, the data processing center 21 captures and calculates which dies and the locations on the dies on the wafer 10 the one or more defect images 1101 are generated on.

Next, as shown in FIG. 3B, the data processing center 21 obtains coordinates (X) of each defect of the wafer 10₁,Y₁) And acquires the image file 1001 of the defective image 1101 and the line 1102 on the image file 1001. Referring to fig. 3B, a defect image 1101 is generated on a die 11D of the dies on the wafer 10, wherein 7 defects are detected in total, and the data processing center 21 is configured to process the defect image according to the defect coordinates (X)₁,Y₁) Is a first reference origin coordinate (X) with respect to the crystal grain 11D₀₁,Y₀₁) (ii) a For example, a first reference origin coordinate (X)₀₁,Y₀₁) Generated by an input program (recipe) of a defect inspection machine, usually a first reference origin coordinate (X)₀₁,Y₀₁) The corner of the die 11D or the easily found recognition position is selected as a mark (marker), which is not limited by the invention. Finally, the data processing center 21 obtains the text and image file of each defect, and then uses the wafer 10 as a defect text and image data file 1130, wherein the defect text and image data file 1130 records the content of each defect image 1101 including the number of the die 11D and the serial number (identification number) of the defect image 1101, the product name, the defect manufacturing step, the lot number, the defect inspection machine number, and the defect coordinate (X)₁,Y₁) And the size of the rough defect image 1101 (including the maximum size in the X direction and the maximum size in the Y direction). Finally, the defective text and image data file 1130 is stored in the memory unit 23.

Next, the defect data coordinate conversion and the offset correction in step 130 are performed. Referring to FIG. 3C, the design layout and defect data coordinate transformation of the intelligent system of the present inventionAnd the other schematic diagram. As shown in FIG. 3C, the data processing center 21 reads the defect coordinates (X) of each defect image 1101 in the defect text and data file 1130 on the die 11D₁,Y₁) Then, the data processing center 21 processes the data according to the defect coordinates (X) in the defect text and data file 1130₁,Y₁) After the coordinate transformation, the defect coordinates (X) of the defect image 1101 on the defect layout pattern 1111 in the design layout 1110 are found according to the reference coordinates on the design layout 1110₂,Y₂) Referring to FIG. 3C, the 7 defect images 1101 of the defect numbers 1-7 are converted to the defect coordinates (X) corresponding to the defect layout pattern 1111₂₁,Y₂₂) To the defect coordinate (X)₂₇,Y₂₇). The size of the defect layout pattern 1111 is determined according to the accuracy or deviation range of the defect inspection machine; for example, when the defect scan test is performed by using an optical defect inspection machine with a deviation range of-0.5 μm to +0.5 μm, the area of the deviation range of the defect layout pattern 1111 is 1 μm x1 μm, wherein the dimension of the conductive line in the defect layout pattern 1111 may be 50nm, and the dimension distance between the conductive line and the other conductive line may be 30 nm.

In addition, the defect coordinates (X)₁,Y₁) Map coordinates (X) transformed onto design map 1110₂,Y₂) The purpose of the location is to determine whether the defect image 1101 would cause a defect such as a disconnection or a short circuit in the line 1102. However, as described above, the coordinates (X) of the defect image 1101₁,Y₁) Measured by a defect scan inspection machine, the reference coordinate may be the first origin coordinate (X) of the die 11D₀₁,Y₀₁) Is taken as the center; the design layout pattern 1110 has its own reference origin coordinates (X)₀₂,Y₀₂) Contains the coordinate (X) of the reference origin of the layout pattern via the mask data₀₂,Y₀₂) Relative position with respect to the mark layout coordinate, when the mark layout coordinate selected by the defect inspection machine is the reference origin coordinate (X)₀₁,Y₀₁) Then, the design layout 1110 is designed with respect to the reference origin coordinate (X) of the defect inspection tool₀₁,Y₀₁) The calculation can be carried out in a coordinate conversion system; in addition, when the defect inspection machine measures the wafer 10, the edge or corner of the circuit 1102 is rounded due to optical diffraction, so that the coordinates (X) of the defect image 1101 are generated₁,Y₁) A certain deviation distance is arranged from the right-angled corner; and the coordinates on the design layout 1110 are a 90 degree rectangular polygon pattern. Obviously, the same reference origin coordinate (X)₀₁,Y₀₁) A deviation exists between the wafer 10 and the mark layout pattern (marker layout pattern)1110 of the reference origin, and the deviation is displayed on the coordinates of the layout pattern after the coordinate conversion, and is obtained and corrected by the coordinate deviation correction system.

In some cases, the file format of the defect image 1101 may not be consistent with the file format of the design layout 1110, for example, the file format unit of the defect image 1101 is pixel, micron or nanometer, etc., and the file format unit of the design layout 1110GDS is micron or nanometer, etc., and there may be deviations between these different file formats. Therefore, in a preferred embodiment of the present invention, a procedure for accurate calibration is added, as shown in step 200. Referring to fig. 4, the actual correction process of step 200 is a flowchart illustrating the correction of the coordinate transformation and deviation correction of the design layout diagram according to the defect of the present invention. First, as shown in step 110 and step 120 in fig. 4, a design layout is obtained and defect data is obtained first, and the process is the same as that in fig. 2, and thus, the description is omitted. Then, please refer to step 210, in which the sizes of the defect image file 1001 and the design layout 1110 are adjusted to be the same; for example, the unit sizes of the image file 1001 of the defect image 1101 and the design layout 1110 may be selected to be adjusted to be uniform, that is, to be pixel units or common units such as micrometers and nanometers. Then, the step 220 is completed, and the defective image 1101 is correctly converted to the design layout 1110, so that the problem of a large deviation of coordinate conversion caused by the inconsistency between the file format of the defective image 1101 and the image file 1001 format of the design layout 1110 can be overcome.

Then, in order to convert the coordinates of the defect image to the design layout and correct the deviationIt is more fully contemplated that all factors that may affect the accuracy of the coordinate transformation are taken into account. Therefore, a further preferred embodiment of the present invention is provided, please refer to fig. 5, which is a flowchart of the coordinate transformation for resizing according to the present invention. As shown in FIG. 5, first, in step 2110, parameters of the defect inspection apparatus are obtained, for example, data such as alignment reference coordinates and dimensions of the defect inspection apparatus are obtained from the data processing center 21 to the memory unit 23; or, the parameters of the design layout 1110 are obtained in step 2120, for example, the data processing center 21 obtains the original coordinates, the alignment reference coordinates, and the dimensions of the design layout 1110 from the memory unit 23; and a step 2130 of obtaining Mask parameters, for example, data of alignment reference coordinates, original coordinates, coordinates of center point and size of the Mask parameters from the data processing center 21 to the memory unit 23. Then, as shown in step 2140, after the size of the acquired defect image 1101, the size of the design layout 1110, and the size of the mask are adjusted to be consistent, step 220 is completed, and the user needs to select one or more mark patterns (marker patterns) as alignment reference coordinate points for setting the defect inspection machine, wherein the mark patterns may be simple patterns easy to align, such as L-shaped, cross-shaped, or rectangular patterns. In general, these mark patterns may be placed on scribe lines (scribes) in the vicinity of the die instead of on the die design layout, and the Mask (Mask) data contains the coordinates of each mark pattern, the corner of the design layout and the center point on the scribe lines (scribes), so the distance from the mark point to the original coordinates or the alignment reference coordinates of the design layout 1110 must be calculated from the parameters of the Mask (Mask) so that the coordinate transformation system from the defect coordinates to the design layout 1110 can be calculated and transformed from the above-mentioned relative coordinate relationship, and the correct defect coordinates (X) of the image file 1001 of the defect image 1101 can be obtained₁,Y₁) Coordinates (X) transformed onto design layout 1110₂,Y₂). Finally, in the present embodiment, after the processing of step 220, no matter the correction from the coordinate transformation or the real time pattern matching (real time pattern match) between the image file 1001 of the defect image 1101 and the design layout 1110 is ensured,the correction of the deviation is performed with the coordinate deviation data, as shown in step 230.

Referring back to FIG. 4, when all the factors that may cause coordinate deviation have been corrected in step 220, it can be confirmed that the image file 1001 of the defect image 1101 has been corrected and converted to coordinates (X) in one of the defect layout patterns 1111 on the design layout 1110₂,Y₂) (ii) a It is apparent that each defect layout pattern 1111 has a different layout pattern and a different defect image 1101 pattern; for example, when 1000 dies 11D can be formed on the wafer 10, the defect coordinates (X) of the defect image 1101 are determined₁,Y₁) Defect coordinates (X) transformed onto design layout 1110₂,Y₂) When, there is a possibility that a deviation is formed on each of the defect layout patterns 1111. Thus, the present invention further provides three ways to design the defect coordinates (X) on the layout 1110₂,Y₂) And (4) correcting. First, in step 2410, selecting a defect image 1101 from the data processing center 21 to the memory unit 23; for example, selecting a layout pattern representing a Transistor (Transistor) device; then, the data processing center 21 obtains the first defect layout pattern 1111; then, after the data processing center 21 obtains the image file 1001 of the defect image 1101 corresponding to the first component, the image file 1001 of the defect layout pattern 1111 and the defect image 1101 are displayed on the display screen 51 (as shown in fig. 6B); in one embodiment, the displayed image files 1001 of the defect layout pattern 1111 and the defect image 1101 are adjusted to be consistent in size units (e.g., both adjusted to be pixel units or units of micron, nanometer, etc.); then, the operator manually performs a certain number of comparisons and statistics on the display screen 51; for example, the image file 1001 of the defect layout pattern 1111 and the defect image 1101 is manually aligned by the executive corrector with a set coordinate on the display screen 51, as shown in the upper half of fig. 6A. If the defect coordinates (X) converted to the defect layout pattern 1111 are displayed₂,Y₂) New coordinates (X) with the defective image file 1001₂’,Y₂') are not in the same position, the deviation is correctedUp to the new coordinate (X)₂’,Y₂') to a host; for example, the corrector manually marks the relative position of the defect image file 1001 on the defect layout pattern 1111 with a new coordinate (X)₂’,Y₂'). It is apparent that the actual defect coordinates (i.e., coordinate deviation correction amount) on the defect layout pattern 1111, to which the position of the defect image file 1001 is converted, is (X)₂’-X₂,Y₂’-Y₂) As shown in the lower half of fig. 6A. Then, a certain amount of coordinate deviation correction is performed in sequence according to the method, for example, the coordinate deviation correction of at least 51 pens is obtained; then, as shown in step 250, after being compiled into a table and statistically analyzed by the data processing center 21, a Coordinate correction threshold Value of an Average Coordinate Precision Value (Average Coordinate Precision Value) and a Standard Deviation Value (Standard development) of the Coordinate Precision can be obtained, as shown in fig. 6D. In a preferred embodiment, if the memory capacity and processor speed of the data processing center 21 are fast enough, the defect layout pattern 1111 and the image file 1001 of each defect image 1101 may be compared one by one, for example, after comparing 10,000 defect images 1101, a more accurate statistical value is obtained as the coordinate deviation correction amount or the correction threshold, and the invention is not limited thereto. Finally, as shown in step 260, after obtaining the accurate statistical value as the coordinate deviation correction amount or the correction threshold, the coordinate deviation amount can be introduced into the coordinate transformation system according to the obtained coordinate precision standard deviation value, and the coordinate deviation amount correction is performed on the coordinate position of the defect image 1101 transformed onto the defect layout pattern 1111, wherein the coordinate deviation amount is (X)₂’-X₂,Y₂’-Y₂) Or the coordinate deviation amount (X)₂’-X₂,Y₂’-Y₂) And (4) carrying out statistical analysis on the average coordinate precision value of the X axis and the Y axis and the standard deviation value of the coordinate precision.

In addition, the invention can also select another correction mode to obtain the accurate coordinate deviation correction amount. As shown in step 2420, the data processing center 21 obtains the defect layout pattern 1111 file of the first component; then, the data processing center21 obtaining an image file 1001 of a defect image 1101 corresponding to a first component, and displaying a defect layout pattern 1111 and the image file 1001 of the defect image 1101 on the display screen 51; similarly, in one embodiment, the displayed image files 1001 of the defect layout pattern 1111 and the defect image 1101 are adjusted to be consistent in units (e.g., both adjusted to be pixel units or units of micron, nanometer, etc.); then, the corrector marks the position between the actual defect image 1101 and the line 1102 pattern with a new coordinate (X) on the position of the corresponding line pattern of the defect layout pattern 1111 via the Graphical User Interface (GUI) directly by the arrow (cursor) on the mouse₂’,Y₂') as shown in the upper half of FIG. 6B; for example, the corrector manually indicates the relative position of the defect image file 1001 on the defect layout pattern 1111 as a new coordinate (X) by an arrow (cursor)₂’,Y₂') to a host; thereafter, the coordinates (X) of the defect image 1101 may be determined₁,Y₁) Converting and marking coordinates (X) on the defect layout pattern 1111₂,Y₂) And (6) displaying. If the coordinates (X) of the defect image 1101 converted to the defect layout pattern 1111 are displayed₂,Y₂) The position of the defect image 1101 and the new coordinates (X) on the defect layout pattern 1111₂’,Y₂') is not at the same position, a corrected coordinate deviation can be obtained, where the coordinate deviation is (X)₂’-X₂,Y₂’-Y₂) As shown in the lower half of fig. 6B. Then, as shown in steps 250 to 260, a certain number of corrections are sequentially performed according to the above-mentioned manner, the process is the same as the process of fig. 6A, and a Coordinate correction threshold Value of an Average Coordinate Precision Value (Average Coordinate Precision Value) and a Standard Deviation Value (Standard Deviation) of the Coordinate Precision can be obtained as a basis for the Deviation correction and introduced into the Coordinate conversion system, so that the details are not repeated.

In addition, the invention can select another correction mode to obtain the accurate coordinate deviation amount. As shown in step 2430, the defect map of the first component is obtained from the data processing center 21Case 1111 file; next, the data processing center 21 acquires the image file 1001 of the defect image 1101 corresponding to the first component, and then displays the defect layout pattern 1111 and the image file 1001 of the defect image 1101 on the display screen 51 together. Similarly, in one embodiment, the displayed image files 1001 of the defect layout pattern 1111 and the defect image 1101 are adjusted to be consistent in size units (e.g., both adjusted to be pixel units or units of micron, nanometer, etc.); thereafter, the pattern of the wiring 1113 on the defect layout pattern 1111 is automatically aligned with the pattern of the wiring 1102 on the image file 1001 of the defect image 1101 by the data processing center 21, as shown in the middle diagram of fig. 6C; thereafter, the coordinates (X) of the defect image 1101 file may be recorded₁,Y₁) Marking the position on the defect layout pattern 1111 with the new coordinate (X)₂’,Y₂'). If the defect coordinates (X) converted to the defect layout pattern 1111 are displayed₂,Y₂) With new coordinates (X) marked₂’,Y₂') when not at the same position, correcting the deviation, wherein the coordinate deviation amount is (X)₂’-X₂,Y₂’-Y₂) As shown in the lower half of fig. 6C. Then, as shown in steps 250 to 270, a certain number of corrections are sequentially performed according to the above-mentioned manner, the process is the same as the process of fig. 6A, and a Coordinate correction threshold Value of an Average Coordinate Precision Value (Average Coordinate Precision Value) and a Standard Deviation Value (Standard Deviation) of the Coordinate Precision in the X axis and the Y axis can be obtained as a basis for performing the Deviation correction and guiding into the Coordinate conversion system, which is not described again.

Fig. 6A, 6B and 6C illustrate various embodiments of the present invention that can provide accurate coordinate deviation correction amounts, and therefore, any one of the embodiments of fig. 6A, 6B and 6C can be selected to obtain coordinate deviation correction amounts or accurate statistical values as coordinate deviation amounts or coordinate correction threshold values through steps 250 to 260.

After completing step 200, the "intelligence system" of the present invention has obtained the coordinate position deviation of the defect image 1101 transformed onto the design layout 1110After correction, the coordinate deviation correction amount is (X)₂’-X₂,Y₂’-Y₂) Or a statistic of the Coordinate Deviation correction amount (i.e., the Coordinate correction threshold), such as an Average Coordinate Precision Value (Average Coordinate Precision Value) and a Standard Deviation Value (Standard Deviation) of the Coordinate Precision of the X-axis and the Y-axis. Then, it is determined whether the defect image 1101 causes a failed critical defect such as open circuit or short circuit after the defect image 1101 is generated in the design layout 1110 file. Since the defect image 1101 or its contour (contour) is an image pattern, the design layout 1110 is in GDS or OASIS format, and there is no defect pattern on the design layout 1110, the analysis of short circuit or open circuit defect caused by the defect image 1101 cannot be performed at all. Since the outline of the defect image 1101 may be irregular, the present invention provides a method for capturing (clip) the defect outline of the defect image 1101, which is used to obtain the size and area of the defect image 1101 as the basis for the critical defect of open circuit or short circuit type failure.

Referring to fig. 7A to 7D, as shown in step 140, a defect outline of the defect image is captured and overlapped to a defect coordinate position on the design layout according to the present invention. First, the "smart system" obtains from the image file 1001 in the defect text and image data file 1130 the outline dimensions of a defect image 1101, including the maximum dimension in the X-axis and the maximum dimension in the Y-axis, from the data processing center 21. Then, the data processing center 21 generates a Polygon (Polygon) defect image 1103 pattern having the same maximum X-axis and Y-axis dimensions as the defect outline according to the outline dimensions of the captured defect image 1101; for example, if the maximum dimension of the X-axis is 0.1 μm and the maximum dimension of the Y-axis is 0.08 μm, the area of the pattern of the polygonal defective image 1103 is 0.008 μm (μm)²) As indicated by the arrows below fig. 7A. Then, the outline pattern of the captured defect image 1101 or the polygonal defect pattern 1103 is overlapped (superimposed) or mapped (mapped) to the coordinates (X) of the corrected defect layout pattern 1111₂’,Y₂') or a coordinate deviation correction of (X)₂’-X₂,Y₂’-Y₂) Or the statistical value of the coordinate deviation correction value, so as to determine whether the size of the captured defect image 1101 or the polygon defect image 1103 pattern has a fatal defect effect such as a short circuit or a break circuit on the wiring 1113 of the defect layout pattern 1111 file; as shown in the defect layout pattern 1111 on the left side of fig. 7B, which is a short-circuited systematic defect, two lines 1113 are connected by a defect image 1101; also shown in the defect layout 1111 at the right of fig. 7B, which is an open-circuit systematic defect, a line 1113 is completely covered by a defect image 1101 to form a block. Then, the step 150 or the step 160 can be used to determine whether there is a critical defect of open circuit or short circuit type on the defect pattern 1001 or the defect layout pattern 1111.

Next, a Critical Area Analysis (CAA) method of step 150 is performed. When the data processing center 21 has overlapped the area of the captured polygonal defect image 1103 to the coordinates of the corresponding defect image 1101 on the defect layout pattern 1111, the critical area analysis method can be used to analyze the critical area of the captured polygonal defect image 1101 on the defect layout pattern 1111, and the probability of the open-circuit or short-circuit type failure defect can be determined; the probability value of the defect is the fatal defect index (KDI), i.e., CAA value. For example, the engineer superimposes each captured polygon defect image 1101 pattern onto the defect layout pattern 1111 to determine whether the short circuit or the open circuit of the line 1113 will be caused, and the engineer can determine the probability of the fatal defect according to the critical area size of the polygon defect image 1103 pattern and the line 1113. As shown in fig. 7C (i.e., fig. 3C, defect pattern 6), when the size of the captured defect image 1101 or the captured polygonal defect image 1103 is much smaller than the size of the lines 1113 or the distance between the lines 1113; for example, when the size of the polygonal defective image 1103 pattern is 0.008 μm²When the width of the wiring 1113 and the pitch of the wiring 1113 are both 0.1 μm, the pattern of the defect image 1101 or the captured polygonal defect image 1103 is not observedIf the pattern does not cause an open circuit or short circuit type systematic defect on the line 1113, judging that the area of the key area is 0, so that the fatal defect index KDI is 0; when the size of the pattern of the polygonal defective image 1103 is 0.001 μm²Time) is equal to or close to the width dimension (0.1 μm) of the line 1113, although the line 1113 is broken or short-circuited, the probability of the defect image 1101 or the polygon defect image 1103 falling on the line 1113 of the defect layout pattern 1111 depends on the number of lines 1113 on the defect layout pattern 1111. As shown in fig. 7C, when the critical area of the line 1113 only occupies 1/10 of the total coordinate deviation range of the defect layout pattern 1111, it is determined that the critical area is 0.1, so the critical defect index KDI is 0.1, that is, the pattern of the polygonal defect image 1103 may cause the line 1113 on the defect layout pattern 1111 of fig. 7C to be open or short-circuited with a probability of 0.1.

Similarly, the implementation of analyzing and determining the fatal defect index is illustrated in fig. 7D. As shown in FIG. 7D, the Critical Area Analysis (Critical Area Analysis) method used in the present invention is commonly used in Design For Manufacturing yield simulation Analysis, i.e., the Analysis of Critical areas of IC Design layout. In the simulation analysis, a group of defects is randomly placed on any coordinate by a random number method, and the yield is judged according to the influence of the defects so as to estimate the possible yield. The critical area analysis method used in the present invention is to extract the defect image 1101 and the size and area of the defect from the defect data of the defect inspection machine, convert the defect image 1101 and the size and area of the defect to the corresponding coordinates on the defect layout pattern 1111, and calculate the critical area of the defect layout pattern 1111 in the coordinate deviation range area (as mentioned above, the defect may be in any coordinate of the coordinate deviation range area due to the deviation caused by the motor precision controlled by the movement of the defect inspection machine), and the critical defect index (KDI) is the critical area obtained by analyzing the critical area divided by the area of the coordinate deviation range area (i.e. the area of the defect layout pattern 1111), and accordingly, calculate the probability value of the defect with open circuit or short circuit type failure, i.e. the critical defect index (KDI). As shown in the left diagram of FIG. 7D, when the defect image 1101 is shownIf the pattern of the polygon defect image 1103 captured or the pattern of the polygon defect image does not cause a system defect of open circuit or short circuit type on the line 1113, the area of the critical area is determined to be 0, and when the KDI value of the defect sample is determined to be equal to 0 or close to 0, the probability that the defect causes the open circuit or short circuit of the line (i.e., the failure of the die) is lower. As shown in the right diagram of FIG. 7D, when the size of the defect image 1101 or the pattern of the captured polygonal defect image 1103 is 0.001 μm²Time) is equal to or close to the width dimension (0.1 μm) of the line 1113, the line 1113 is broken or short-circuited, and at this time, the Critical Area (Open Critical Area; OCA) and Critical Area causing Short circuits (Short Critical Area; SCA), as shown by the dotted line in fig. 7E, since both the critical area of open circuit and the critical area of short circuit cause systematic defects or random defects, the critical area of both must be added and then divided by the area of the coordinate deviation range (for example, after the defect scanning detection is performed by the optical defect detecting machine with the deviation range of-0.5 μm to +0.5 μm, the area of the coordinate deviation range of the defect layout pattern 1111 is 1 μmx1 μm); for example, when the size of the conductive line in the defect layout pattern 1111 is 50nm and the size distance between the conductive line and another conductive line is 30nm, and when the size of the defect image 1101 pattern is 60nm, it is obvious that the defect image 1101 with the size of 60nm causes fatal defect no matter where it is located in the defect layout pattern 1111, and thus, when the critical area (OCA) of open circuit is 0.7 μm²And critical area for Short Circuit (SCA) of 0.3 μm²When it is, the KDI value is equal to 0.7 μm²+0.3μm²1 μmx1 μm ═ 1; therefore, the KDI value of the defect sample is judged to be equal to 1 or close to 1; when the KDI value is equal to or close to 1, the higher the probability of line open or short circuit (i.e. die failure) caused by the defect, the greater the chance of selecting the defect sample. Finally, the defect probability values of the patterns of the defective polygon defect image 1101 are recorded in the memory unit 23.

In addition, the present invention may select step 160, directly after capturing an image file 1001 with a defect image 1101 (as shown in the foregoing, the image file 1001 includes the defect outline image 1101 and the position of the defect outline image 1101 relative to the adjacent line), overlapping the defect outline image with the defect layout pattern 1111 corresponding to the image file 1001 (as shown in the middle diagram of fig. 6C), so as to determine whether the defect image 1101 causes an open circuit or short circuit type failure defect. For example, after the data processing center 21 directly overlaps an image file 1001 with an original defect image 1101 outline with a defect layout pattern 1111 corresponding to the defect image 1101, at this time, the data processing center 21 or an engineer may determine whether the image file is an Open circuit failure defect or a Short circuit failure defect according to an overlapping position of the original defect image 1101 outline and the defect layout pattern 1111 after pattern matching; if the judgment results are that the circuit is broken or the short-circuit type fails, judging that the circuit belongs to the fatal defect, and judging that a fatal defect index (KDI) is 1; and if the judgment result shows that no open circuit or short circuit type fails, judging that the defect belongs to a non-fatal defect, and judging that the fatal defect index (KDI) is 0. Finally, the result of determining the critical defect index (KDI) of the defect image 1101 is recorded in the memory unit 23. Obviously, since the present embodiment directly overlaps the image file 1001 captured with the outline of the original defect image 1101 with the defect layout pattern 1111 corresponding to the defect image 1101, the fatal defect index (KDI) value of the defect image 1101 can be directly determined; therefore, in a preferred embodiment of performing step 160, after the steps of fig. 4 or fig. 5, it is critical to obtain the correct coordinates of the original defect image 1101 and the precise defect layout pattern 1111 in which the coordinates of the corresponding defect image 1101 are transformed; in addition, in another preferred embodiment of performing step 160, the image file 1001 of the defect image 1101 is an image file scanned by SEM. Again, since the accuracy of the SEM scanning is high, the scanned original defect image 1101 is the actual defect location, and at this time, the critical defect index (KDI) value of the defect image 1101 is already known, and therefore, in this embodiment, the critical defect index (KDI) value is only 1 or 0; the purpose of directly overlapping the image file 1001 with the outline of the original defect image 1101 and the defect layout pattern 1111 corresponding to the defect image 1101 is to know the position of the defect image 1101 on the defect layout pattern 1111, so that the subsequent layout modification required for the defect layout pattern 1111 causing the fatal defect can be performed.

Based on the above, when performing a critical defect index (KDI) or Critical Area Analysis (CAA) analysis of the defect image 1101, the "intelligent system" of the present invention can select to use the image file 1001 with the outline of the original defect image 1101 to overlap the defect layout pattern 1111 of the opposite defect image 1101, as shown in step 160; alternatively, the area of the captured defect image 1101 may be selected to be overlapped to the coordinates of the corresponding defect image 1101 on the design layout 1110, as shown in step 150; the invention is not limited thereto.

As mentioned above, in order to achieve fast scanning when scanning the defect image 1101 of the wafer 10, optical devices such as a microscope, an electron beam (E-beam) inspection tool, an optical inspection tool, a defect scanner, or a camera are usually selected to obtain defect data (e.g., the size, width, size, coordinates, or outline … of the defect) on the wafer quickly. When the defect image 1101 is scanned by using the optical device, the Resolution (Resolution) of the scanning detection of the lens and wavelength of the optical device itself may not be high enough to clearly present the defect image 1101 between the optical device and the scanned wafer 10, for example, when the defect image 1101 is out of focus (defocus), the edge of the defect image 1101 is blurred, so that the scanned defect image 1101 is larger than the actual defect pattern, and the false determination of the fatal defect may be caused. In addition, each optical scanning apparatus has a certain accuracy limitation, and when the accuracy is insufficient, the minimum unit used for scanning defect and discrimination is larger than the minimum size layout pattern, which causes the situation of fuzzy defocusing of the defect image 1101, and also causes misjudgment of the fatal defect. For example, when the Resolution (Resolution) unit of the optical device is 50nm and the actual X-axis or Y-axis size of the defect image 1101 is 35 nm, the minimum size of the defect image 1101 that can be determined by the optical device is 50 nm; this result causes the original defect report in the defect text and image data file 1130 to be a multiple of the minimum unit of scan-to-compare analysis to record the size and area of the scanned and detected defect image 1101, where the size and area of the defect image 1101 is much larger than the size and area of the actual defect image 1101 photographed by an electron microscope (SEM) with a precision of 1, 2 nm; it is clear that this inaccuracy of the original defect size affects the critical defect index, i.e. it can cause misjudgment of non-critical defects or low-risk critical defects into high-risk critical defects; for example, the size and area of the actual defect image 1101 will not cause the defect of open circuit or short circuit type failure, but as the result of the fuzzy defocus due to the accuracy of the minimum unit is not enough, the area of the defect image 1101 that causes the defect report is too large and is determined as a fatal defect with higher risk, which will reduce the probability that the real open circuit or short circuit type failure defect is sampled, and cause the problems of slow yield improvement or cost increase. It is obvious that the defect size of the original defect report of the defect image 1101 needs to be further corrected to be close to the actual defect size because the precision of the minimum unit of the scanning comparison is not sufficient, so as to make an accurate judgment and improve the success rate of sampling the open circuit or short circuit type failure defects.

In order to solve the out-of-focus problem of the optical device during scanning the wafer 10, the present invention provides a method for correcting the defect size and area of the defect image 1101. As shown in step 500 of fig. 8A, fig. 8A is a flowchart of a system for establishing defect size and area correction according to the present invention, and accurate defect size correction is a Critical Area Analysis (CAA) and critical defect index (KDI) accuracy correction of the nefarious door. The leftmost end of FIG. 8B is the original defect size, area provided by the data processing center 21 reading the defect inspection report from the defect text and image data file 1130; then, the data processing center 21 extracts the defect size of the defect image file with high resolution from the defect text and image data file 1130; in a preferred embodiment, the high resolution defect image file is the size and area of the image file obtained by SEM; then, according to the size of the defect image file with high resolution, correcting the original defect outline size and converting the original defect outline size into a polygonal defect pattern; FIG. 8C is a defect size table showing approximate actual defect contour sizes of the leftmost original defect size after correction by a high resolution defect image file; the detailed description is as follows.

As shown in fig. 8A, the flowchart 500 of the critical area analysis and the fatal defect index correction of the present invention is started by the data processing center 21 acquiring the defect text and image data file 1130; first, as shown in step 120, the data processing center 21 obtains original defect data (including text file and defect image file) from the defect text and image data file 1130; then, as shown in step 510, the data processing center 21 obtains the original defect size (original defect size) and defect area (area) of the polygon defect image 1103 in the X-axis and Y-axis from the defect text in the defect text and image data file 1130; when the precision of the optical device for scanning the defect is not enough (i.e. the scanned defect size is larger than the actual defect size), for example, when the precision of an optical device is 50nm, the detected minimum defect size is 50nm, so when the original defect size is less than 50nm, the optical device is presented by taking the multiple of 50nm as a unit, and the minimum defect size detected by the optical device is deviated from the minimum defect size detected by an SEM photo with higher precision (for example, the precision unit is 2 nm); for example, the 3 rd defect image 1101 in FIG. 8C has original dimensions of 50nm on the X-axis and 50nm on the Y-axis; the original size of the 4 th original defect image 1101 is 150 nm on the X-axis and 150 nm on the Y-axis, for example, the critical defect index of the 3 rd original defect image 1101 in FIG. 8C is judged to be 0.4; and the fatal defect index of the 4 th defective image 1101 is judged to be 1. Next, as shown in step 520, the data processing center 21 retrieves each defect image 1101 with high precision from the memory unit 23 and obtains a defect contour size (image contour defect size) and a defect contour area; for example, when a Scanning Electron Microscope (SEM) photograph is used with a resolution of 3 nm, the exact dimensions of the 3 rd defect image 1101 in FIG. 8C can be resolved as 35 nm on the X-axis and 35 nm on the Y-axis; the exact dimensions of the 4 th defect image 1101 are 100 nm on the X-axis and 120 nm on the Y-axis. Therefore, after the correction of the embodiment, a fatal defect index (KDI) after accurate correction can be obtained; for example, the corrected actual fatal defect index of the 3 rd defective image 1101 in FIG. 8C is 0.1; and the corrected actual fatal defect index of the 4 th defective image 1101 is corrected to be 0.55. Then, as shown in step 530, a statistical method is applied to correct the plurality of original defect sizes and defect area groups and the plurality of high-precision defect contour sizes and defect contour area groups and find out an optimal statistical method; next, as shown in step 540, a defect size correction system using statistical methods and measurement uncertainty analysis are established to convert the raw defect size data generated by the optical equipment performing fast defect detection on-line into near-actual defect size data, and the actual conversion process will be described in detail in the next section. In addition, it should be emphasized that since the most accurate defect detection is the SEM machine, it is not directly used, but it is subjected to a complicated calibration procedure. Since the defect inspection is performed after the wafer 10 is manufactured, the SEM is accurate but the actual operation process is complicated, so the inspection capability can only process about 1% of the original defect size data, and in order to accelerate the process time, the SEM cannot process all the defects, and only the optical device with a faster inspection speed can be used for fast scanning; therefore, if the defect size correction is not performed, as described above, the fatal defect index misjudgment is caused, which affects the defect classification, and also affects the improvement of the defect yield, thereby increasing the manufacturing time and cost; as shown in step 550, the critical defect index accuracy and precision obtained by the critical area analysis are improved by the defect size correction. In the present embodiment, how many SEM precision defect images are selected to perform the statistics, i.e., the correction, is not limited by the invention. Then, if the scanning speed of the SEM device is improved or other advanced scanning equipment is available to rapidly provide all the defect processes, the critical defect index of the defect can be accurately obtained using the previously described step 160. Since the process continues to shrink, such as the minimum dimension of the layout is 1, 2 nm or less than 1 nm, which is gradually equivalent to or less than the SEM accuracy, the defect size calibration system and method described above are still suitable for new defect inspection machines and cameras, and are not limited herein.

With continued reference to FIG. 8C, a defect size correction process is described in which the defect report generated by the on-line defect inspection tool in the semiconductor fab scanning the wafer is inaccurate original defect size data, which is converted to approximate actual defect size data by the correction and measurement uncertainty analysis of the defect size correction system. Fig. 8A and 8B show the following. As shown in step 540, the data processing center 21 may perform a statistical operation on the original defect size (original defect size) of each defect image 1101 before correction and the real defect size (real defect size) after correction to establish a statistical model, and modify the sizes of the defect images 1101 in the X axis and the Y axis according to the statistical model; for example, a correction factor (factor) of 0.85 is defined by a statistical model after correction of the defect image 1101 with a fatal defect index of 1; for example, the original size of the 4 th defect image 1101 in fig. 8C is 150 nm on the X-axis and 150 nm on the Y-axis, and after step 540, the original size of the defect image 1101 or the polygon defect image 1103 needs to be multiplied by a factor (factor) of 0.85, so that the size of the corrected defect image 1104 or the corrected polygon defect image 1105 is 130 nm on the X-axis and 130 nm on the Y-axis. Or a Calibration factor (0.9) is defined by the statistical model after the defect image 1101 with the fatal defect index of 0.5 is calibrated, and the conversion process is as described above and is not repeated. Thereafter, as shown in step 550, the data processing center 21 defines factors according to the statistical model, and automatically corrects and overlaps each of the defect images 1101 to the coordinates of the corresponding defect image 1101 on the design layout 1110. Finally, after the data processing center 21 or the engineer determines and corrects the defect image again, a more accurate fatal defect index of each defect image 1101 can be obtained.

Through the calibration process shown in fig. 8A, 8B, and 8C, the actual defect size data can be obtained more accurately, since the fatal defect index is in a positive relationship with the defect size, incorrect defect size data will result in a higher number of high fatal defect index defects, making it more difficult to select open circuit or short circuit type failure defects, increasing the time and cost for yield improvement. The data in the table of FIG. 8C shows the defect sizes before and after correction. It is obvious that in the above embodiment, the defect scan file using SEM is directly selected for correction, which is the best effect; the second is the threshold, and the statistical value of the threshold is closer to the scanning result of SEM when the number of samples determining the threshold is larger.

After the analysis of the defect open or short type failure and the correction of step 500 in

steps

150 and 160 in fig. 2, the present invention can further classify the defect image 1101. As shown in step 170, the defect is classified as a Non-critical defect (Non-critical defect) or a critical defect (critical defect) according to the correction result of the defect in the previous steps. For example, the result of step 150 is classified by a critical defect index (KDI) value, a defect signal parameter (defect signal parameter), and whether there is a pattern match with the defect pattern database and the defect database with high failure frequency; wherein the defect signal parameter is for or selects an image file 1001 with a defect image 1101 and uses the image to analyze the intensity (intensity or brightness) of each pixel in the two-dimensional space, as shown in fig. 11A, wherein the horizontal axis is the intensity value and the vertical axis is the number of pixels; the contrast value (contrast) of the defect pattern with respect to its surrounding background pattern is analyzed and the polarity value (polarity) of the defect pattern and its light shadow change on the upper layer or lower layer of the background is determined by using fig. 11A. The step 160 is executed in such a manner that the defect contour overlaps two different polygonal patterns (polygon) or overlaps one polygon, and the defect is classified into a non-critical defect or a critical defect of open circuit or short circuit type failure, as will be described later.

In addition, a defect pattern library (defect pattern library) and a defect failure library (frequency failure library) with high failure frequency are established by using the step 180 shown in fig. 2; one of the sources of the defect pattern includes layout patterns violating design rule (design rule check error), for example, the distance rule is 30nm, the actual pattern is 28 nm, and the defect pattern is selected into the defect pattern database due to the reduction of the process window, which is likely to result in low yield, as shown in FIG. 11B; another defect pattern source is whether a design layout pattern 1110 is designed by performing dfm (design for manufacturing) simulation test analysis, which may result in low yield due to higher risk of simulation analysis value of the process window, and is selected into the defect pattern database because it needs to be further compared to whether there is a defect at the actual relative position on the wafer, which causes an open circuit or a short circuit, as shown by the X mark in fig. 11C. In addition, in the aspect of creating a defect database (frequency failure defect library) with high failure frequency, after combining a plurality of defect images 1101 actually scanned by an optical device, a pattern matching method is used to obtain patterns with consistent or similar patterns, and the patterns are created in the defect database with high failure frequency, as shown in fig. 11D, when the density of lines on the design layout is higher, i.e. the defect patterns with high failure frequency, it is necessary to further compare whether the actual relative position on the wafer is defective to cause open circuit or short circuit, so the defect database with high failure frequency is listed. Therefore, the user can create the systematic defect layout pattern 1111, the open-circuit or short-circuit type defect layout patterns found by the failure analysis (failure analysis), the layout patterns violating the Design rule (DRC error), and the Design For Manufacturing Design as well as the risk layout patterns (Design For Manufacturing as well pattern) in the defect map database, and the user can also refer to the patent method of the patent number US8607169B2 approved by the same inventor in 2013 For the defect database with high failure frequency (frequency failure library) to create the defect database with high failure frequency. Step 170 performs pattern matching on the defect data detected by the defect inspection machine with the defect pattern database and the defect database with high failure frequency (taiwan patent number I534646 approved by the same inventor in 2016) to find the same or similar defect layout pattern for defect analysis.

In addition, please refer to fig. 9, which is a flowchart for performing a polygonal pattern comparison analysis of the defect outline and the layout pattern. As shown in fig. 9, the defect contour and the layout pattern are compared and analyzed by the polygon pattern in step 160 to determine whether there is a defect with open circuit or short circuit type failure, and then classified. In step 1610, if the position of the defect image 1101 is within the coordinate deviation range of the defect layout pattern 1111 and is not a dummy layout pattern (dummy pattern) of the actual line or a dummy layout pattern (dummy pattern) of the line, so that no open circuit or short circuit type failure is possible, it is determined as a dummy pattern defect (dummy pattern defect), as shown in fig. 11E, belonging to a Non-critical defect (Non-killer defect). Next, as shown in step 1620, if the position of the defect image 1101 is within the coordinate deviation range of the defect layout pattern 1111 as the line 1113 pattern, but the step 160 performs the comparing analysis of the defect outline and the polygon pattern of the layout pattern, and there is no possibility of the open circuit or short circuit type failure, this is determined as a zero risk defect (nuisance defect), as shown in fig. 11F, only the area of the defect layout pattern 1111 is the line 1113 and the line size is much larger than the defect image size, so no matter the defect image falls in this area, the possibility of the open circuit or short circuit type failure will not be caused, and the defect belongs to a Non-critical defect (Non-killer defect). Next, as shown in step 1630, if the position of the defect image 1101 is within the coordinate deviation range of the defect layout pattern 1111 and has the pattern of the line 1113, but the step 160 performs the comparing analysis of the defect outline and the polygon pattern of the layout pattern, there may be a short-circuit or open-circuit type failure (open or short-circuit type failure), which is shown in fig. 7D as KDI 1 and belongs to a fatal defect (Killer failure).

Finally, please refer to fig. 10, which is a flowchart illustrating defect classification according to the present invention. As shown in fig. 10, defect signal data and KDI values are obtained, and the defects are classified into Non-critical defects (Non-critical defects) and critical defects (Killer defects) according to the presence or absence of defects matched with the defect pattern database and the defect database with high failure frequency by the pattern matching according to the critical defect index KDI value and signal parameter value of each defect, thereby providing a basis for defect sampling. Obtaining defect data and analyzed defect signal data through step 1710, obtaining a defect critical defect index KDI value calculated by the key area analysis method in step 150 in step 1720, and classifying the defects according to the presence or absence of the defect performing pattern matching with the defect pattern database and the defect database with high failure frequency according to the critical defect index KDI value and the defect signal parameter value of each defect in step 1730; please refer to fig. 11A to 11G for the defect map database. Then, step 1740 is to determine whether there is a possibility of open circuit or short circuit type failure, for example, when the fatal defect index KDI value of the defect is equal to 0, no matter how many the defect signal parameter values are (as shown in fig. 11A), it is determined that the defect is a dummy pattern defect (as shown in fig. 11E) and belongs to a Non-fatal defect (Non-killer defect), and the defect is to be filtered out, that is, the defect can not be selected when subsequently performing defect sampling analysis; for example, if 3000 non-fatal defects are included in 5000 defect images 1101, the 3000 defects are not included in the defect selection in the defect sampling analysis. In step 1750, when the fatal defect index KDI value of the defect is determined to be equal to or close to 0, no matter how many the defect signal parameter values are, it is determined that the defect is a zero-risk defect (as shown in fig. 11F) and also belongs to a Non-fatal defect (Non-killer), and therefore, the defect is also filtered, and the filtering manner is as in step 1740 and is not repeated.

Next, step 1760 is performed. Firstly, classifying the defect that is not filtered out, for example, selecting the high fatal defect index KDI value (for example, 0.75-1) and the high defect signal parameter value as the first priority sampling group; secondly, selecting a high fatal defect index KDI value (e.g. 0.75-1) and a medium defect signal parameter value as a second priority sampling group; then, selecting the median fatal defect index KDI value (e.g. 0.5-0.75) and the high defect signal parameter value as the first priority sampling group; then, the median fatal defect index KDI value (e.g. 0.5-0.75) and the median defect signal parameter value are listed as the second priority sampling group; it should be noted that the above are all the groups of samples belonging to a high risk fatal defect (high risk killer defect) that must be modified; if the modification of the defect group is required to be completed in the shortest time, the defect group can be preferentially selected and classified as the first priority sampling group, which comprises the sampling group for selecting the high fatal defect index value and the high defect signal parameter value sequence and the sampling group for selecting the middle fatal defect index value and the high defect signal parameter value sequence; the invention is not limited as to how the sampling groups are determined.

Then, selecting a low fatal defect index KDI value (for example, 0.2-0.5) and high and medium defect signal parameter values as another sampling group, wherein the defect sampling priority is the third preferred sampling group due to low risk fatal defect (low risk killer defect), and only a few micro-defects are sampled; for example, the lowest critical defect index KDI value (e.g., <0.2), such as the values of the very low risk critical defect and the low defect signal parameter, are very low risk critical defects (nuisance defects), which are close to zero risk defects (Non-critical defects), and are very close to Non-critical defects (Non-critical defects), so that there is no need to list the defect samples or to list the sample groups to be filtered. In the above process, all the defect images 1101 on the wafer 10 have been classified and sampled, so the classification and sampling results are continuously expanded in the defect text and image data file 1130 (shown in fig. 3B), i.e., each defect image 1101 is indicated as belonging to which sampling group; of course, the extended defect text and image data file 1130 is also updated and stored in the memory unit 31.

In addition, as shown in step 1770, after the defect classification of step 1730 is completed, and the defect pattern database and the defect database with high failure frequency can be selected to perform pattern matching, if the same or similar defect and the defect belongs to a warning defect, the defect must be sampled; however, if the defect belongs to the dummy defect layout pattern (as shown in FIG. 11G), the dummy defect is filtered.

According to the above description, the present invention provides an intelligent defect correction system and an implementation method thereof, which improves the accuracy of analyzing critical areas of defects by using a defect coordinate and defect size correction system, improves the accuracy of determining whether a semiconductor defect causes a critical defect of an open circuit or a short circuit type, filters out non-critical defects in defect samples, and combines defect signal parameters to use a critical defect and a risk classification level thereof as a defect sampling priority.

The present invention has been described in detail with reference to the embodiments, but the invention is not limited thereto. The scope of protection is to be determined by the claims appended hereto and their equivalents. It will be appreciated by those skilled in the art that changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention, which is set forth in the claims below.

Claims

1. A defect correction method for performing intelligent semiconductor wafers by a data processing center and a storage device, is characterized in that:

providing a design layout diagram and storing it in the storage device, and configuring a plurality of lines in the design layout diagram;

Performing the wafer manufacturing process is to form the circuit on the wafer according to the design layout in the semiconductor factory;

To perform wafer defect scanning, the wafer is scanned by a defect inspection machine to obtain defect scanning data, and the defect scanning data is processed by the data processing center into defect text and image data files, which are then stored in the In the storage device, wherein the defect text and image data files include a plurality of defect data on the wafer, and each defect data at least includes defect coordinates, defect size, defect area and intensity value of the pattern of the defect image ;

Obtaining the design layout diagram is obtained by the data processing center, and the data processing center identifies the relative coordinate position of each of the lines, the line width and the distance between the lines;

Execute the first overlapping procedure, in which the data processing center extracts the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and according to the The defect coordinates overlap the defect size and the defect area on the relative coordinates of the design layout;

To perform the first critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout, and uses the critical area analysis method to obtain all the defects in the coordinate deviation range area. The critical area of the design layout is determined, and the fatal defect index value is determined, wherein the fatal defect index value distinguishes a plurality of values of different sizes; and

Perform calibration procedures, including:

selecting at least one of said fatal defect index values;

providing a SEM scanning machine, and rescanning each defect position where the selected fatal defect index value is located to obtain accurate defect size and accurate defect area, and store them in the storage device; and

It is judged whether the precise defect size and the precise defect area are systemic fatal defects of open circuit type or short circuit type.

2. A defect correction method for performing intelligent semiconductor wafers by a data processing center and a storage device, characterized in that:

Performing a wafer fabrication process is to form the circuit on a wafer in a semiconductor factory and according to the design layout;

Obtaining the design layout diagram is obtained by the data processing center, and the data processing center identifies the relative coordinate positions of the lines, the line widths, and the distances between the lines;

To perform the first critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout, and uses the critical area analysis method to obtain all the defects in the coordinate deviation range area. The critical area of the design layout is determined, and the fatal defect index value is determined, wherein the fatal defect index value distinguishes a plurality of different values; and

Perform calibration procedures, including:

selecting at least one of said fatal defect index values;

Provide a SEM scanner, and rescan each defect position where the selected fatal defect index value is located to obtain accurate defect size and accurate defect area, and store them in the storage device;

A second overlapping procedure is performed, in which the data processing center captures the precise defect size and the precise defect area, and overlaps the precise defect area to the design layout according to the defect coordinates on the relative coordinates of the graph; and

Performing the second critical area analysis, the data processing center superimposes the precise defect size and the precise defect area on the design layout, and uses the critical area analysis method to obtain the coordinate deviation of the defect In the critical area of the design layout within the scope area, the corrected fatal defect index value is determined, wherein the corrected fatal defect index value distinguishes a plurality of different values.

3. A defect correction method for performing intelligent semiconductor wafers by a data processing center and a storage device, characterized in that:

To perform wafer defect scanning, the wafer is scanned by a defect inspection machine to obtain defect scanning data, and the defect scanning data is processed by the data processing center into defect text and image data files, which are then stored in the In the storage device, the defect text and image data files include a plurality of defect data on the wafer, and each defect data at least includes the origin of wafer coordinates, defect coordinates, defect size, defect area and defect image The intensity value of the pattern;

Obtaining the design layout diagram is obtained by the data processing center, and the data processing center identifies the coordinate origin, the relative coordinate position of each of the lines, the line width and the distance between the lines;

Executing the first coordinate conversion program is that the data processing center obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and according to the defect The coordinates (X ₁ , Y ₁ ) are converted to the first coordinates (X ₂ , Y ₂ ) relative to the design layout;

To provide a display screen, the data processing center obtains an image file of an area near the defect image according to the coordinate position of the defect image, and at the same time, the data processing center obtains the corresponding coordinate position of the defect image in the design layout drawing. an image file of a nearby area, and the image file of the area near the defect image and the image file of the area near the coordinate position of the corresponding defect image in the design layout are displayed on the display screen together;

The second coordinate (X ₂ ', Y ₂ ') is marked, which is the area near the coordinate position of the defect image corresponding to the defect image in the design layout drawing of the defect image on the image file in the vicinity of the defect image. The second coordinate (X ₂ ', Y ₂ ') is marked on the image file;

The corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) is obtained when the first coordinate (X ₂ , Y ₂ ) and the second coordinate on the design layout are When (X ₂ ', Y ₂ ') are not at the same coordinate position, the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained;

Provide a calibration factor, which is to compare the defects with the defect size and the defect area in the defect text and image data files with the SEM defect size and SEM defect area, so as to calculate the calibration factor;

Performing defect size correction, after multiplying each of the defect sizes in the defect text and image data files by the correction factor, and storing the corrected defect size in the storage device;

Executing the first overlapping procedure is that the data processing center captures the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and according to the defect coordinates overlapping the defect size and the defect area to the corrected coordinate deviation (X2'-X2, Y2'-Y2) of the design layout; and

To perform the first critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout, and uses the critical area analysis method to obtain all the defects in the coordinate deviation range area. Describe the key areas of the design layout, and determine the fatal defect index value.

4. A defect correction method for performing intelligent semiconductor wafers by a data processing center and a storage device, characterized in that:

The design layout diagram is obtained by the data processing center, and the data processing center identifies the coordinate origin, the relative coordinate position of each of the lines, the line width and the distance between the lines ;

Execute the first coordinate correction procedure, including:

To provide a display screen, the data processing center obtains an image file of the area near the defect image according to the coordinate position of the defect image, and at the same time, the data processing center obtains the area near the corresponding coordinate position of the design layout of the defect image. and displaying the image file of the area near the defect image and the image file of the corresponding area of the defect image near the coordinate position of the design layout drawing on the display screen together;

Marking the second coordinate (X ₂ ', Y ₂ ') is to place the coordinate position of the defective image on the image file in the vicinity of the defective image in the design layout drawing corresponding to the defective image The second coordinate (X ₂ ', Y ₂ ') is marked on the image file of the area near the coordinate position;

The corrected coordinate deviation amount (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) is obtained when the first coordinate (X ₂ , Y ₂ ) of the design layout and the second coordinate ( When X ₂ ', Y ₂ ') are not in the same coordinate position, the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained;

Execute the first overlapping procedure, in which the data processing center extracts the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and according to the The defect coordinates overlap the defect size and the defect area to the corrected coordinate deviation amount (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) of the design layout;

To perform the first critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout, and uses the critical area analysis method to obtain all the defects in the coordinate deviation range area. Describe the key areas of the design layout, and determine the fatal defect index value;

Perform calibration procedures, including:

selecting at least one of said fatal defect index values;

To perform the second critical area analysis, the data processing center superimposes the precise defect size and the precise defect area on the design layout, and uses the critical area analysis method to obtain the coordinates of each defect. In the critical area of the design layout within the deviation range area, the corrected fatal defect index value is determined, wherein the corrected fatal defect index value distinguishes a plurality of different values.

5. A defect correction method for performing intelligent semiconductor wafers by a data processing center and a storage device, characterized in that:

To perform wafer defect scanning, the wafer is scanned by a defect inspection machine to obtain defect scanning data, and the defect scanning data is processed by the data processing center into defect text and image data files, which are then stored in the In the storage device, the defect text and image data files include a plurality of first defect data on the wafer, and each of the first defect data at least includes defect coordinates, defect size, defect area and defect image. the intensity value of the pattern;

Provide a coordinate correction threshold value, which is stored in the storage device, wherein the coordinate correction threshold value is the deviation range area of the defect layout pattern converted from the coordinate position of the pattern of each of the defective images by the semiconductor factory The statistic value of the coordinate position correction on the coordinate correction threshold value, the coordinate correction threshold value includes the average coordinate precision value of the X-axis and the Y-axis and the standard deviation value of the coordinate precision;

Execute a calibration procedure, in which the data processing center converts the coordinate position of the pattern of each of the defective images to the coordinate correction of the deviation range region of the defective layout pattern according to the coordinate correction threshold threshold value, and stored in the storage device;

Providing a correction factor is to compare a plurality of defects with the defect size and defect area in the defect text and image data files with the SEM defect size and SEM defect area, so as to calculate the correction factor;

Performing defect size correction, after multiplying each defect size in the defective text and image data files by the correction factor, and storing the corrected defect size in the storage device;

Execute the first overlapping procedure, in which the data processing center extracts the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and according to the Defect coordinates overlaying the defect size and the defect area onto the corrected coordinate correction threshold of the deviation range region of the design layout; and

To perform critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout diagram, and uses the critical area analysis method to obtain all the defects in the coordinate deviation range area. Describe the key areas of the design layout, and determine the fatal defect index value.

6. A defect correction method for performing intelligent semiconductor wafers by a data processing center and a storage device, characterized in that:

Provide a coordinate correction threshold value, which is stored in the storage device, wherein the coordinate correction threshold value is the coordinate position of the semiconductor factory that converts the coordinate position of each of the defective images to the coordinate position on the deviation range area of the defect layout pattern The corrected statistical value, the coordinate correction threshold value includes the average coordinate precision value of the X-axis and the Y-axis and the standard deviation value of the coordinate precision;

A calibration procedure is executed, in which the data processing center converts the coordinate position of each of the defective images to the coordinate correction threshold of the deviation range region of the defective layout pattern according to the coordinate correction threshold on and stored in the storage device;

Performing critical area analysis, the data processing center superimposes the corrected defect size and the defect area on the design layout, and uses the critical area analysis method to obtain the coordinate deviation range area of each defect. In the critical area of the design layout diagram, the fatal defect index value is judged.

7. The defect correction method for performing smart semiconductor wafers by a data processing center and a storage device as claimed in claim 5 or 6, wherein the coordinate correction threshold is determined by using a defect SEM image file and corresponding The defect layout pattern is manually, graphically assisted by a user interface (GUI) method or graphically matched and corrected to obtain a plurality of coordinate deviation values, and then obtain the coordinate deviation correction parameters through statistical analysis.

8. A defect correction method for executing an intelligent semiconductor wafer by a data processing center and a storage device, characterized in that:

To perform wafer defect scanning, the wafer is scanned by a defect inspection machine to obtain defect scanning data, and the defect scanning data is processed by the data processing center into defect text and image data files, which are then stored in the In the storage device, the defect text and image data files include a plurality of first defect data on the wafer, and each of the first defect data at least includes defect coordinates, defect size, defect area and the pattern of the defect image. strength value;

Providing a correction factor is to compare the defects with the defect size and defect area in the defect text and image data files with the SEM defect size and SEM defect area, so as to calculate the correction factor;

Execute the first overlapping procedure, in which the data processing center extracts the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and according to the Defect coordinates overlap the defect size and the defect area to the corrected coordinate correction threshold of the design layout; and

Performing the first critical area analysis, the data processing center overlaps the corrected defect size and the defect area on the design layout, and uses the critical area analysis method to obtain the coordinate deviation range area of each defect. In the critical area of the design layout diagram, the fatal defect index value is judged.

9. The defect correction method for smart semiconductor wafers executed by a data processing center and a storage device as claimed in any one of claims 2 to 6 or 8, wherein the method is further based on a fatal defect index of each of the defects The size and the magnitude of the intensity value of the pattern of the defect image are used to classify the defect.

10. The defect correction method for performing smart semiconductor wafers by a data processing center and a storage device as claimed in claim 9, wherein the defect classification comprises: virtual pattern defects, zero-risk defects or fatal defects.

11. The defect correction method for smart semiconductor wafers performed by a data processing center and a storage device as claimed in claim 9, wherein sampling is performed according to the defect classification result, comprising: virtual pattern defects and zero risk Defect filtering.

12. The defect correction method for smart semiconductor wafers performed by a data processing center and a storage device as claimed in claim 9, wherein sampling is performed according to the defect classification result by a set fatal defect index value and the intensity value of the pattern of the defect image set to sample fatal defects.

13. A defect correction method for executing an intelligent semiconductor wafer by a data processing center and a storage device, characterized in that:

Provide a coordinate correction threshold value, which is stored in the storage device, wherein the coordinate correction threshold value is the coordinate position of the semiconductor factory that converts the coordinate position of each of the defective images to the coordinate position on the deviation range area of the defect layout pattern The corrected statistical value, the coordinate correction threshold value includes the average coordinate precision value of the X-axis and the Y-axis and the standard deviation value of the coordinate precision; and

A calibration procedure is executed, in which the data processing center converts the coordinate position of each of the defective images to the coordinate correction threshold of the deviation range region of the defective layout pattern according to the coordinate correction threshold and stored in the storage device.

14. A correction method for performing intelligent semiconductor wafer defect coordinate transformation by a data processing center and a storage device, characterized in that:

To obtain the parameters of the defect detection machine, the data processing center obtains the alignment reference coordinates and the unit size of the defect detection machine;

The design layout diagram is obtained by the data processing center, and the data processing center identifies the origin of coordinates, the position of the relative coordinates of each of the lines, the line width and the distance between the lines and its unit size;

Obtaining the mask parameters is to obtain the reference point, origin, center point and unit size from the data processing center;

Adjusting the unit size is to adjust the unit size of obtaining the defect image, the unit size of the design layout drawing, and the unit size of the mask to be consistent; and

The calibration program for executing coordinate transformation is that the data processing center obtains the defect coordinates (X 1 , Y 1 ) of the pattern of the defect image from the defect text and image data files, and determines the defect coordinates (X ₁ , Y ₁ ) according to the defect image. Coordinates (X ₁ , Y ₁ ) are converted to relative coordinates (X ₂ , Y ₂ ) of the design layout.

15. The correction method for performing intelligent semiconductor wafer defect coordinate transformation by using a data processing center and a storage device as claimed in claim 14, wherein after executing the coordinate transformation correction program, further executing the coordinate transformation Correction procedures, including:

To provide a display screen, the data processing center obtains an image file of an area near the defect image according to the coordinate position of the defect image, and at the same time, the data processing center obtains the corresponding coordinate position of the defect image in the design layout drawing. The image file of the nearby area, and the image file of the area near the defect image and the image file of the area near the coordinate position of the corresponding defect image in the design layout drawing are displayed on the display screen together show;

Marking the second coordinate is the image file in which the coordinate position of the defect image on the image file of the area near the defect image is in the area near the coordinate position corresponding to the defect image in the design layout drawing The second coordinate (X ₂ ', Y ₂ ') is marked on it; and

The corrected coordinate deviation amount (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) is obtained when the relative coordinates (X ₂ , Y ₂ ) on the design layout are different from the second coordinate ( When X ₂ ', Y ₂ ') are not at the same coordinate position, the corrected coordinate deviation amount (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained.

16. The correction method for performing intelligent semiconductor wafer defect coordinate transformation by using a data processing center and a storage device as claimed in claim 15, wherein after the coordinate correction program corrects the defect image, Obtain the average coordinate accuracy value of the X-axis and the Y-axis and the standard deviation value (Standard Deviation) of the coordinate accuracy.

17. A correction method for performing intelligent semiconductor wafer defect coordinate transformation by a data processing center and a storage device, characterized in that:

The design layout diagram is obtained by the data processing center, and the data processing center identifies the origin of coordinates, the position of the relative coordinates of each of the lines, the line width and the distance between the lines ;

Executing the first coordinate conversion program is that the data processing center obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and according to the defect coordinates ( X ₁ , Y ₁ ) are converted to first coordinates (X ₂ , Y ₂ ) relative to the design layout; and

Execute the first coordinate correction procedure, including:

Marking the second coordinate (X ₂ ', Y ₂ ') is to place the coordinate position of the defective image on the image file in the vicinity of the defective image in the design layout drawing corresponding to the defective image The second coordinate (X ₂ ', Y ₂ ') is marked on the image file in the vicinity of the coordinate position; and

The corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) is obtained when the first coordinate (X ₂ , Y ₂ ) and the second coordinate on the design layout are When (X ₂ ', Y ₂ ') are not at the same coordinate position, the corrected coordinate deviation amount (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained.

18. A defect correction method for executing an intelligent semiconductor wafer by a data processing center and a storage device, characterized in that:

Executing the first coordinate conversion program is that the data processing center obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and according to the defect The coordinate position of the image is converted to the first coordinate (X ₂ , Y ₂ ) relative to the design layout;

To provide a display screen, the data processing center obtains the image file of the area near the defect image according to the coordinate position of the defect image, and at the same time, the data processing center obtains the defect image in the design layout map the image file of the area near the corresponding coordinate position, and put the image file of the area near the defect image and the corresponding image file of the defect image in the area near the coordinate position of the design layout drawing together in the displayed on the display screen;

Marking the second coordinate (X ₂ ', Y ₂ ') is to place the coordinate position of the defective image on the image file in the vicinity of the defective image on the corresponding position of the defective image in the design layout drawing The second coordinate (X ₂ ', Y ₂ ') is marked on the image file of the area near the coordinate position;

The corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) is obtained when the first coordinate (X ₂ , Y ₂ ) and the second coordinate on the design layout are When (X ₂ ', Y ₂ ') are not in the same coordinate position, the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained;

To execute the first overlapping procedure, the data processing center extracts the defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and compares the defect size with the defect size. the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) of the defect area overlapping to the design layout; and

To perform the first critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout diagram, and uses the critical area analysis method to obtain the defect in the coordinate deviation range area. In the critical area of the design layout, the fatal defect index value is determined.

19. A defect correction method for executing an intelligent semiconductor wafer by a data processing center and a storage device, characterized in that:

Performing a wafer fabrication process is to form the circuit on the wafer according to the design layout in a semiconductor factory;

Execute the first coordinate correction procedure, including:

The display screen is provided, and the data processing center obtains an image file of the vicinity of the defect image according to the coordinate position of the defect image, and at the same time, the data processing center obtains the corresponding defect image in the design layout drawing. The image file of the area near the coordinate position, and the image file of the area near the defect image and the corresponding image file of the defect image in the area near the coordinate position of the design layout are displayed on the display together. displayed on the screen;

Marking the second coordinate (X ₂ ', Y ₂ ') is to place the coordinate position of the defective image on the image file in the vicinity of the defective image on the corresponding position of the defective image in the design layout drawing The second coordinate (X ₂ ', Y ₂ ') is marked on the image file in the vicinity of the coordinate position; and

To execute the first overlapping procedure, the data processing center extracts the defect coordinates, defect size, and defect area of the pattern of the defect image one by one from the defect text and image data files, and converts the The defect size and the defect area are overlapped to the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) of the design layout to obtain the overlapped coordinates;

To perform the first critical area analysis, the data processing center superimposes the defect size and the defect area on the design layout, and uses the critical area analysis method to obtain all the defects in the coordinate deviation range area. The critical area of the design layout diagram is described, and the fatal defect index value is determined; and

Perform calibration procedures, including:

selecting at least one of said fatal defect index values;

To perform the second critical area analysis, the data processing center superimposes the precise defect size and the precise defect area on the design layout, and uses the critical area analysis method to obtain the coordinates of each of the defects. In the critical area of the design layout within the deviation range area, the corrected fatal defect index value is determined, wherein the corrected fatal defect index value distinguishes a plurality of different values.

20. The defect correction method for smart semiconductor wafers performed by a data processing center and a storage device as claimed in claim 19, wherein after the first coordinate correction program corrects the defect image, X is obtained The average coordinate accuracy value and standard deviation value (Standard Deviation) of the axis and Y-axis.

21. A defect correction method for executing an intelligent semiconductor wafer by a data processing center and a storage device, characterized in that:

Performing defect size correction, after multiplying the defect size in the defect text and image data files by the correction factor, and storing the corrected defect size in the storage device;

Execute the first overlapping procedure, in which the data processing center extracts the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and according to the Defect coordinates overlaying the defect size and the defect area onto the coordinate correction threshold of the deviation range region of the design layout; and

22. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout Figure, and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the wafer, and the wafer defect inspection machine is used for To scan the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device obtains the design layout diagram to identify the relative coordinate positions of the lines on the design layout diagram, the line width of each of the lines and the distance between each two of the lines. distance;

The data processing device extracts at least one defect coordinate, at least one defect size and at least one defect area one by one from the defect text and image data files, and recalculates the defect size and the defect area according to the defect coordinates. overlapping to the relative coordinate positions of each of the lines on the design layout;

The data processing device is superimposed on the design layout according to the defect size and the defect area, uses the key area analysis method to obtain the key areas of the design layout in which each defect is within the coordinate deviation range, and judges at least one defect index value;

The data processing device selects at least one of the defect index values, and uses a scanning device to re-scan each of the defect positions where the selected defect index value is located to obtain a new defect size after scanning and a new defect size after scanning. creating a new defect area and storing the new defect size after the scan and the new defect area after the scan in the storage device, respectively; and

The data processing device is used for judging whether the new defect size after the scanning and the new defect area after the scanning are open-circuit type or short-circuit type system defects.

23. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout , and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the semiconductor wafer, and the wafer defect inspection machine For scanning the semiconductor wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device obtains the correction factor by comparing each defect with the defect size and defect area in the defect text and image data files with the SEM defect size and SEM defect area, so as to calculate the correction factor;

The data processing device performs defect size correction by multiplying each of the defect sizes in the defective text and image data files by the correction factor, and then storing the corrected defect size in the storage device;

The data processing device executes the first overlapping procedure, which is to capture the defect coordinates, the defect size and the defect area of the defect text and image data files one by one, and compare the defect size and the defect area according to the defect coordinates. overlaid on the coordinate correction threshold of the deviation range region of the design layout; and

24. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout , and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the semiconductor wafer, and the wafer defect inspection machine For scanning the semiconductor wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The coordinate correction threshold value captured by the data processing device is stored in the storage device, wherein the coordinate correction threshold value is the deviation range of converting the coordinate position of each defective image to the defective layout pattern by the semiconductor factory The statistic value of the coordinate position correction on the area, the coordinate correction threshold value includes the average coordinate precision value of the X-axis and the Y-axis and the standard deviation value of the coordinate precision;

The data processing device executes a calibration procedure to convert the coordinate position of each of the defective images to the coordinate correction threshold of the deviation range region of the defective layout pattern according to the coordinate correction threshold , and stored in the storage device;

The data processing device executes the first overlapping procedure, which is to capture the defect coordinates, defect size and defect area of the pattern of the defect image one by one, and overlap the defect size and the defect area according to the defect coordinates to the coordinate correction threshold of the deviation range region of the design layout; and

Performing the key area analysis is that the data processing center overlaps the design layout with the defect size and the defect area, and uses the key area analysis method to obtain the design of each defect within the coordinate deviation range. The critical area of the layout diagram is used to determine the fatal defect index value.

25. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout , and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the semiconductor wafer, and the wafer defect inspection machine For scanning the semiconductor wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device obtains the correction factor by comparing the defects having both the defect size and the defect area in the defect text and image data files with the SEM defect size and the SEM defect area, so as to calculate the correction factor;

The data processing device performs defect size correction by multiplying the defect size in the defective text and image data files by the correction factor, and then storing the corrected defect size in the storage device ;

To perform critical area analysis, the data processing device superimposes the defect size and the defect area on the design layout diagram, and uses the critical area analysis method to obtain all the defects within the coordinate deviation range area. Describe the key areas of the design layout, and determine the fatal defect index value.

26. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout Figure, and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the wafer, and the wafer defect inspection machine is used for To scan the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device retrieves the coordinate correction threshold by retrieving the coordinate correction threshold from the storage device, wherein the coordinate correction threshold is for converting the coordinate position of each defective image into a defective layout pattern The statistical value of the coordinate position correction on the deviation range area of the coordinate correction threshold value includes the average coordinate accuracy value of the X-axis and the Y-axis and the standard deviation value of the coordinate accuracy; and

The data processing device executes a calibration procedure, and the data processing device converts each defective image to the coordinate correction threshold of the deviation range region of the defective layout pattern according to the coordinate correction threshold. , and stored in the storage device.

27. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout , and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the wafer, and the wafer defect inspection machine The stage is used for scanning the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device obtains the parameters of the defect detection machine, so as to obtain the alignment reference coordinates and the unit size;

The data processing device obtains the design layout diagram for identifying the coordinate origin, the relative coordinate position of each of the lines, the line width, the distance between the lines and the unit size thereof;

The data processing device obtains the mask parameters for obtaining the reference point, the origin, the center point and the unit size;

The data processing device adjusts the unit size by adjusting the unit size of the acquired defect image, the unit size of the design layout and the unit size of the mask to be consistent; and

The data processing device executes the coordinate conversion program, and the data processing device obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and according to the defect coordinates (X ₁ , Y ₁ ) is converted to relative coordinates (X ₂ , Y ₂ ) of the design layout.

28. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout , and the design layout diagram is configured with a plurality of circuits, the wafer manufacturing machine set is used to arrange the circuits in the design layout diagram on the wafer, and the wafer defect inspection machine The stage is used for scanning the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device obtains the design layout diagram for identifying the coordinate origin, the relative coordinate position of each of the lines, the line width and the distance between the lines;

The data processing device executes a first coordinate conversion program, which obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and converts them into relative coordinates according to the defect coordinates. the first coordinate (X ₂ , Y ₂ ) of the design layout; and

The data processing device executes the first coordinate correction program, including:

The display screen is provided, and the data processing device obtains an image file of an area near the defect image according to the coordinate position of the defect image, and at the same time, the data processing device obtains the image file of the defect image in the vicinity of the corresponding coordinate position of the design layout drawing. file, and display the image file of the area near the defect image and the image file of the corresponding area of the defect image near the coordinate position of the design layout drawing on the display screen together;

The second coordinate (X ₂ ', Y ₂ ') is marked, which is the area near the coordinate position of the defect image corresponding to the defect image in the design layout drawing of the defect image on the image file in the vicinity of the defect image. The second coordinate (X ₂ ', Y ₂ ') is marked on the image file; and

The corrected coordinate deviation is obtained when the first coordinates (X ₂ , Y ₂ ) and the second coordinates (X ₂ ', Y ₂ ') on the design layout are not in the same coordinate position , the corrected coordinate deviation amount (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained.

29. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout , and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the wafer, and the wafer defect inspection machine The stage is used for scanning the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device executes the first coordinate conversion program, and the data processing device obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and according to the defect coordinates (X ₁ , Y ₁ ) is converted to a first coordinate (X ₂ , Y ₂ ) relative to the design layout;

The display screen is obtained by the data processing device according to the coordinate position of the defective image to obtain an image file of the vicinity of the defective image, and at the same time, the data processing device obtains the coordinates of the defective image in the corresponding design layout drawing. The image file of the area near the position, and the image file of the area near the defect image and the corresponding image file of the defect image in the area near the coordinate position of the design layout are displayed on the display screen together display on;

The data processing device marks the position of the defective image on the image file in the area near the defective image on the image file in the area near the coordinate position of the defective image corresponding to the design layout drawing. Two coordinates (X ₂ ', Y ₂ ');

The data processing device obtains the corrected coordinate deviation when the first coordinates (X ₂ , Y ₂ ) and the second coordinates (X ₂ ', Y ₂ ') on the design layout are not At the same coordinate position, the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) can be obtained from the data processing center;

The data processing device compares a plurality of defects having both the defect size and the defect area in the defect text and image data files with the SEM defect size and the SEM defect area, so as to calculate the correction factor;

The data processing device multiplies each defect size in the defective text and image data files by the correction factor, and stores the corrected defect size in the storage device;

The data processing device executes the first overlapping procedure, which is to extract the defect coordinates, defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and analyze the defects according to the defects. The coordinates overlap the defect size and the defect area to the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) of the design layout to obtain the overlapped coordinates ;

The data processing device executes the first critical area analysis by using the critical area analysis method to obtain the description of each defect within the coordinate deviation range area according to the overlap of the defect size and the defect area on the design layout. Design the key areas of the layout, and determine the fatal defect index value;

The data processing center executes the second overlapping procedure, which is to capture the precise defect size and precise defect area, and overlap the precise defect area on the relative coordinates of the design layout according to the defect coordinates ;and

The data processing device performs the second critical area analysis by overlapping the precise defect size and the precise defect area on the design layout, and using the critical area analysis method to obtain the coordinate deviation range area of each defect. A corrected fatal defect index value is determined in the key area of the design layout diagram within the corrected fatal defect index value, wherein the corrected fatal defect index value distinguishes a plurality of different values.

30. A defect correction system for semiconductor wafers, comprising a storage device, a wafer fabrication tool set comprising a wafer fabrication tool, a wafer defect inspection tool and a data processing device, wherein the storage device is used to store a design layout Figure, and the design layout diagram is configured with a plurality of lines, the wafer manufacturing machine set is used to arrange the lines in the design layout diagram on the wafer, and the wafer defect inspection machine is used for To scan the wafer to obtain defect scan data, the data processing device converts the defect scan data into a file with defective text and image data and stores it in the storage device, characterized in that:

The data processing device executes the first coordinate conversion program, which obtains the defect coordinates (X ₁ , Y ₁ ) of the pattern of the defect image from the defect text and image data files, and converts them into relative coordinates according to the defect coordinates. Describe the first coordinate (X ₂ , Y ₂ ) of the design layout;

The display screen is provided, and the data processing device obtains an image file of an area near the defect image according to the coordinate position of the defect image, and at the same time, the data processing center obtains the defect image in the corresponding coordinate position of the design layout. and displaying the image file of the area near the defect image and the image file of the corresponding area of the defect image near the coordinate position of the design layout drawing on the display screen together;

Marking the second coordinate (X ₂ ', Y ₂ ') is to set the position of the defective image on the image file in the vicinity of the defective image to the coordinate position of the defective image corresponding to the design layout drawing The second coordinates (X ₂ ', Y ₂ ') are marked on the image file of the nearby area;

The data processing device executes the first overlapping procedure, which is to extract the defect size and defect area of the pattern of the defect image one by one from the defect text and image data files, and compare the defect size with the defect size. The defect area is overlapped with the corrected coordinate deviation (X ₂ '-X ₂ , Y ₂ '-Y ₂ ) of the design layout;

The data processing device executes the first critical area analysis by using the critical area analysis method to obtain the description of each defect within the coordinate deviation range area according to the overlap of the defect size and the defect area on the design layout. Design the key areas of the layout and determine the fatal defect index value; and

The data processing device executes a calibration procedure, including:

selecting at least one of said fatal defect index values;

A second overlapping procedure is performed, in which the data processing device captures the precise defect size and the precise defect area, and overlaps the precise defect area to the design layout according to the defect coordinates on the relative coordinates of the graph; and

The second critical area analysis is performed by the data processing device overlapping the design layout diagram according to the precise defect size and the precise defect area, and using the critical area analysis method to obtain the coordinate deviation of the defect In the critical area of the design layout within the scope area, the corrected fatal defect index value is determined, wherein the corrected fatal defect index value distinguishes a plurality of different values.

31. The defect correction system for semiconductor wafers according to claim 28 or 30, wherein after the defect image is corrected by the first coordinate correction program, the average coordinate precision values of the X-axis and the Y-axis are obtained and the standard deviation of the coordinate accuracy (Standard Deviation).