JP2007195191A5 - - Google Patents

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Publication number
JP2007195191A5
JP2007195191A5 JP2007010029A JP2007010029A JP2007195191A5 JP 2007195191 A5 JP2007195191 A5 JP 2007195191A5 JP 2007010029 A JP2007010029 A JP 2007010029A JP 2007010029 A JP2007010029 A JP 2007010029A JP 2007195191 A5 JP2007195191 A5 JP 2007195191A5
Authority
JP
Japan
Prior art keywords
pins
programmable device
bank
support
banks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007010029A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007195191A (ja
JP4621215B2 (ja
Filing date
Publication date
Priority claimed from US11/337,046 external-priority patent/US20070164784A1/en
Priority claimed from US11/558,363 external-priority patent/US7378868B2/en
Application filed filed Critical
Publication of JP2007195191A publication Critical patent/JP2007195191A/ja
Publication of JP2007195191A5 publication Critical patent/JP2007195191A5/ja
Application granted granted Critical
Publication of JP4621215B2 publication Critical patent/JP4621215B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2007010029A 2006-01-19 2007-01-19 モジュール式ｉ／ｏバンクアーキテクチャ Expired - Fee Related JP4621215B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/337,046 US20070164784A1 (en) 2006-01-19 2006-01-19 Modular I/O bank architecture
US11/558,363 US7378868B2 (en) 2006-01-19 2006-11-09 Modular I/O bank architecture

Publications (3)

Publication Number Publication Date
JP2007195191A JP2007195191A (ja) 2007-08-02
JP2007195191A5 true JP2007195191A5 (enExample) 2010-03-04
JP4621215B2 JP4621215B2 (ja) 2011-01-26

Family

ID=37864532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007010029A Expired - Fee Related JP4621215B2 (ja) 2006-01-19 2007-01-19 モジュール式ｉ／ｏバンクアーキテクチャ

Country Status (3)

Country Link
US (1) US7378868B2 (enExample)
EP (1) EP1811668A1 (enExample)
JP (1) JP4621215B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7818512B2 (en) * 2007-06-27 2010-10-19 International Business Machines Corporation High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules
US8037258B2 (en) * 2007-06-27 2011-10-11 International Business Machines Corporation Structure for dual-mode memory chip for high capacity memory subsystem
US8037272B2 (en) * 2007-06-27 2011-10-11 International Business Machines Corporation Structure for memory chip for high capacity memory subsystem supporting multiple speed bus
US7921271B2 (en) * 2007-06-27 2011-04-05 International Business Machines Corporation Hub for supporting high capacity memory subsystem
US8037270B2 (en) * 2007-06-27 2011-10-11 International Business Machines Corporation Structure for memory chip for high capacity memory subsystem supporting replication of command data
US7921264B2 (en) * 2007-06-27 2011-04-05 International Business Machines Corporation Dual-mode memory chip for high capacity memory subsystem
US7822936B2 (en) * 2007-06-27 2010-10-26 International Business Machines Corporation Memory chip for high capacity memory subsystem supporting replication of command data
US8019949B2 (en) * 2007-06-27 2011-09-13 International Business Machines Corporation High capacity memory subsystem architecture storing interleaved data for reduced bus speed
US7809913B2 (en) * 2007-06-27 2010-10-05 International Business Machines Corporation Memory chip for high capacity memory subsystem supporting multiple speed bus
US7996641B2 (en) * 2007-06-27 2011-08-09 International Business Machines Corporation Structure for hub for supporting high capacity memory subsystem
JP5719926B2 (ja) * 2010-06-04 2015-05-20 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 集積回路のための入出力バンクアーキテクチャ
US9401717B2 (en) 2012-05-28 2016-07-26 Baysand Inc. Flexible, space-efficient I/O circuitry for integrated circuits

Family Cites Families (22)

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Publication number Priority date Publication date Assignee Title
JPS62285443A (ja) * 1986-06-03 1987-12-11 Fuji Photo Film Co Ltd マスタスライス集積回路装置
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
JPH04146664A (ja) * 1990-10-08 1992-05-20 Kawasaki Steel Corp 集積回路
US5480026A (en) * 1995-01-17 1996-01-02 Darling; David W. Bocci ball caddy
US5889413A (en) * 1996-11-22 1999-03-30 Xilinx, Inc. Lookup tables which double as shift registers
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
JP3024590B2 (ja) * 1997-04-25 2000-03-21 日本電気株式会社 プログラマブル論理デバイス
US6289496B1 (en) * 1998-06-29 2001-09-11 Xilinx, Inc. Placement of input-output design objects into a programmable gate array supporting multiple voltage standards
TW446780B (en) * 1999-10-07 2001-07-21 Mitsubishi Electric Corp Full-rotary crocheting device
JP2001156171A (ja) * 1999-11-24 2001-06-08 Ricoh Co Ltd 半導体集積回路
US6864710B1 (en) * 1999-12-30 2005-03-08 Cypress Semiconductor Corp. Programmable logic device
JP2001196921A (ja) * 2000-01-17 2001-07-19 Nec Corp プログラマブル集積回路装置
US6384628B1 (en) * 2000-03-31 2002-05-07 Cypress Semiconductor Corp. Multiple voltage supply programmable logic device
US6608500B1 (en) * 2000-03-31 2003-08-19 Cypress Semiconductor Corp. I/O architecture/cell design for programmable logic device
US6535043B2 (en) 2000-05-26 2003-03-18 Lattice Semiconductor Corp Clock signal selection system, method of generating a clock signal and programmable clock manager including same
US7020728B1 (en) * 2001-07-13 2006-03-28 Cypress Semiconductor Corp. Programmable serial interface
US7167023B1 (en) * 2001-08-29 2007-01-23 Altera Corporation Multiple data rate interface architecture
US6946872B1 (en) * 2003-07-18 2005-09-20 Altera Corporation Multiple data rate interface architecture
JP4175155B2 (ja) * 2003-03-24 2008-11-05 セイコーエプソン株式会社 半導体装置
US6838902B1 (en) * 2003-05-28 2005-01-04 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7061269B1 (en) * 2004-05-12 2006-06-13 Lattice Semiconductor Corporation I/O buffer architecture for programmable devices

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