JP2007194940A - Field programmable gate array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the number of components and to lower the manufacturing cost by simplifying the constitution of a peripheral circuit. <P>SOLUTION: An FPGA 10 which is loaded with configuration data from an ROM 20 and structures and executes a logic circuit, corresponding to the loaded configuration data includes a monitor section 14, which monitors whether the voltage Vcc of electric power supplied to the FPGA 10 exceeds a predetermined operation threshold Vth and a loading instruction section 15, which instructs new loading of configuration data from the ROM 20 once informed by the monitor part 14 that the voltage Vcc drops below the operation threshold Vth. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field programmable gate array that constructs and executes a logic circuit according to configuration data loaded from outside.

  Conventionally, as one of the semiconductor devices, a field programmable gate array (FPGA) that receives configuration data from the outside and constructs and executes a logic circuit corresponding to the loaded configuration data. It has been known. The FPGA includes a logic circuit element and a memory, and constructs a logic circuit by connecting the logic elements according to configuration data loaded in the memory. By using the FPGA for the device or the substrate, it becomes possible to construct a circuit after the device or the substrate is assembled, and it is necessary to manufacture a semiconductor device for the target circuit or to change the circuit. The burden is reduced.

  FIG. 3 is a diagram showing the connection of the power source of the FPGA in the prior art.

  The FPGA 501 shown in FIG. 3 has a built-in configuration circuit for loading configuration data from an external memory into the built-in memory, and a signal having the same voltage as the power supply voltage Vcc, which is the voltage of power supplied to the FPGA, is configured. When supplied to the terminal, loading starts. The configuration data of the built-in memory disappears when power supply to the FPGA is stopped, but loading is performed each time the power is turned on by supplying a signal having the same voltage as the power supply voltage Vcc to the configuration terminal. Can reconstruct the logic circuit according to the configuration data.

By the way, in the board | substrate and apparatus with which FPGA is mounted, even if the electric power supplied from a power supply does not stop, a voltage may fall abnormally. In this case, loading is not performed even if the configuration data stored in the built-in memory is destroyed, so that the function of the logic circuit remains impaired. In order to prevent such a situation, as shown in FIG. 4, a reset IC 602 with a power monitoring function capable of discriminating an abnormality in the power supply voltage is provided outside the FPGA 601, and a signal representing the determination result of the reset IC with a power monitoring function Is known to be input to the FPGA configuration terminal (see, for example, Patent Document 1). According to this circuit configuration, the logic circuit is reconstructed even when an abnormality occurs in the power supply voltage.
JP 2002-176352 A

  However, the circuit configuration shown in FIG. 4 complicates the circuit configuration around the FPGA and increases the manufacturing cost of the device.

  In view of the above circumstances, an object of the present invention is to provide a field programmable gate array capable of simplifying the configuration of a peripheral circuit and reducing the number of parts and the manufacturing cost.

The field programmable gate array of the present invention that achieves the above object is a field programmable gate array that receives configuration data from the outside and constructs and executes a logic circuit corresponding to the loaded configuration data.
A monitor for monitoring whether the voltage of the power supplied to the field programmable gate array exceeds a predetermined operation threshold;
A load instructing unit for instructing a new loading of configuration data from the outside is constructed in response to the monitor unit receiving the voltage below the operating threshold value.

  According to the present invention, the field programmable gate array itself that has constructed the logic circuit according to the configuration data instructs the new loading of the configuration data in response to the voltage of the supplied power being below the operation threshold. For this reason, a logic circuit is constructed in response to a voltage abnormality without providing a reset IC with a power monitoring function or a peripheral circuit element different from the field programmable gate array. Therefore, the configuration of the peripheral circuit is simplified, and the number of parts and the manufacturing cost are reduced.

  Here, in the field programmable gate array of the present invention, the monitor section monitors whether the voltage exceeds the operation threshold by monitoring a voltage divided by the resistance. Preferably there is.

  By monitoring the divided voltage divided by the monitor, the peripheral component necessary for the function of monitoring the voltage of the supplied power is only the divided resistor. Therefore, the configuration of the peripheral circuit becomes simpler, and the number of parts and the manufacturing cost are reduced.

  As described above, according to the present invention, a field programmable gate array that simplifies the configuration of the peripheral circuit and reduces the number of components and the manufacturing cost is realized.

  Embodiments of a field programmable gate array of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a field programmable gate array and peripheral circuits according to an embodiment of the present invention.

  Field programmable gate array 10 (hereinafter referred to as FPGA 10) forms electrical circuit 1 together with other peripheral circuit elements. In addition to the FPGA 10, the electric circuit 1 includes a ROM 20, a divided resistor 30 (30a, 30b), and a pull-up resistor 40 as peripheral circuit elements of the FPGA 10. The electric circuit 1 is formed on a circuit board (not shown), and this circuit board is mounted on an electric device. The FPGA 10 is also connected to various components mounted on the circuit board and the electrical equipment, but illustration of these components is omitted.

  The FPGA 10 operates upon receiving power supply, and constructs and executes a logic circuit corresponding to configuration data loaded from the external ROM 20. The FPGA 10 includes a configuration circuit 11, a RAM 12, and a logic construction unit 13. Here, the voltage of power supplied to the FPGA supplied from the power source to the FPGA 10 is referred to as a power source voltage Vcc.

  The configuration circuit 11 reads configuration data from the outside and writes the configuration data to the RAM 12 when the configuration signal Sccfg supplied from the logic construction unit 13 of the FPGA 10 changes from L level to H level. is there. The RAM 12 is a volatile memory that holds the written configuration data. When the power supply is stopped, the configuration data written in the RAM 12 is lost. The logic construction unit 13 has a large number of logic elements (not shown), and the logic elements are connected to each other according to the data written in the RAM 12, thereby constructing a logic circuit according to the configuration data. .

  The ROM 20 is a non-volatile memory and stores configuration data. The configuration data is generated by converting data representing a logic circuit created by circuit design work using a logic synthesis tool or the like.

  The dividing resistor 30 includes a resistor 30 a and a resistor 30 b connected in series, and supplies a voltage-divided signal Ssense obtained by dividing the power supply voltage Vcc supplied to the FPGA 10 to the FPGA 10.

  In the electric circuit 1 shown in FIG. 1, the power supply voltage Vcc is supplied to the configuration circuit 11 of the FPGA 10 via the pull-up resistor 40, and the RAM 12 is stored in the ROM 20 by the configuration circuit 11. Configuration data is loaded. Therefore, in the logic construction unit 13 of the FPGA 10, a logic circuit corresponding to the configuration data is constructed.

  Here, the logic circuit constructed by the logic construction unit 13 includes a monitor unit 14 and a loading instruction unit 15 as an original function of the FPGA 10, in addition to the functional circuit 16 that controls the operation of various components (not shown). ing.

  The monitor unit 14 monitors whether or not a power supply voltage Vcc, which is a voltage of power supplied to the FPGA 10, exceeds a predetermined operation threshold value. More specifically, the monitor unit 14 is a low-level recognition voltage with respect to an input signal in a logic circuit in which the divided signal Ssense obtained by dividing the power supply voltage Vcc by the dividing resistor 30 is constructed as the monitor unit 14. Monitor whether or not In this embodiment, the operation threshold is the lowest voltage value at which the configuration data written in the RAM 12 will not be lost. That is, when the power supply voltage Vcc supplied to the FPGA 10 is equal to or lower than the operation threshold, there is a possibility that the configuration data written in the RAM 12 is lost. Here, the dividing resistor 30 is configured such that when the power supply voltage Vcc becomes an operation threshold value in the FPGA 10, the voltage value of the signal Ssense is a low level recognition voltage of the logic element provided in the logic construction unit 13, that is, this voltage. When the following voltage is input, the port is set to a voltage that is recognized as a low level. The operation threshold value in the FPGA 10 is Vth, the input voltage of the configuration terminal of the logic element provided in the logic construction unit 13 is Vi, and the low level recognition voltage of this terminal (when a voltage lower than this voltage is input) The port is recognized as the Low level). When the resistance values of the resistors 30a and 30b constituting the divided resistor 30 are R1 and R2, respectively, the resistance values R1 and R2 are set so as to satisfy the relationship of the following expression (1).

R1 / R2 = (Vth / ViL) -1 (1)
For example, when the voltage value of the power supply voltage Vcc gradually decreases to be equal to or lower than the operation threshold Vth in the FPGA 10, the voltage value Vi of the divided signal Ssense divided by the dividing resistor 30 is provided in the logic construction unit 13. The logic element becomes lower than the recognition voltage ViL at the low level, and the logic element discriminates the signal Ssense that has been discriminated as the H level as the L level. In this way, the monitor unit 14 constructed as a logic circuit in the logic construction unit 13 can accurately monitor whether or not the power supply voltage Vcc exceeds the operation threshold value Vth.

  The loading instruction unit 15 instructs the configuration circuit 11 to newly load configuration data from the ROM 20 when the monitor unit 14 determines that the power supply voltage Vcc has become equal to or lower than the operation threshold value Vth. More specifically, when the monitor unit 14 determines that the signal Ssense is at the L level, the loading instruction unit 15 drives the configuration signal Sccfg to the L level, and drives the configuration signal Scfg to the H level after a predetermined time has elapsed. .

  FIG. 2 is a timing chart showing an example of signal fluctuations in each part and operation of the configuration circuit as the voltage Vcc of power supplied to the FPGA fluctuates in the electric circuit shown in FIG.

  In FIG. 2, the power supply voltage Vcc is not supplied before time t1. In this state, all contents of the RAM 12 are lost. Further, all signal terminals of the FPGA 10 are set in the input direction, that is, in a high impedance state.

  When the power supply voltage Vcc is supplied at time t1, the voltage of the signal Ssense divided by the dividing resistor 30 also rises accordingly. The voltage of the configuration signal Scfg is raised to the power supply voltage Vcc by the pull-up resistor 40 because the terminal in the logic construction unit 13 is in a high impedance state. When the configuration signal Sccfg transits from the L level to the H level, the configuration circuit 11 loads the configuration data (“LOAD” state). When loading is completed, the logic construction unit 13 of the FPGA 10 constructs and executes a logic circuit corresponding to the configuration data.

  If the power supply voltage Vcc slightly decreases at time t2 due to a power supply abnormality or the like, the configuration data written in the RAM 12 is not lost when the power supply voltage Vcc does not fall below the operation threshold Vth. However, when the power supply voltage Vcc further decreases at time t3 and the value of the voltage Vcc becomes equal to or lower than the operation threshold Vth, the configuration data written in the RAM 12 may be lost, and the logic circuit may be destroyed. At this time, since the signal Ssense of the divided voltage by the dividing resistor 30 decreases and becomes equal to or lower than the low level recognition voltage ViL, the monitor unit 14 determines that the input signal Ssense has transitioned from the H level to the L level. That is, the monitor unit 14 detects that the voltage Vcc of the power supplied to the FPGA 10 has become equal to or less than the operation threshold value Vth. As a result, the loading instruction unit 15 drives the configuration signal Scfg to the L level, and drives the configuration signal Scfg to the H level at a time t4 after a predetermined time has elapsed. As a result, the configuration circuit 11 loads configuration data from the ROM 20 again ("LOAD" state). When loading is completed, in the logic construction unit 13 of the FPGA 10, the monitor unit 14, the loading instruction unit 15, and the functional circuit 16 are constructed again as logic circuits according to the configuration data.

  According to the present embodiment, the FPGA 10 that has constructed the logic circuit according to the configuration data receives the fact that the supply power voltage Vcc has become equal to or lower than the operation threshold value Vth, and then sends the configuration data to the configuration circuit 11. Instruct new loading. Therefore, it is not necessary to provide the electric circuit 1 with a reset IC with a power monitoring function and peripheral circuit elements different from the FPGA 10. Therefore, the configuration of the peripheral circuit of the FPGA 10 is simplified, and the number of parts and the manufacturing cost of the electric circuit 1 are reduced.

  Further, the monitor unit 14 monitors the divided voltage Ssense obtained by dividing the resistance, so that the peripheral element of the FPGA 10 necessary for the function of monitoring the voltage Vcc of the supplied power is only the divided resistor 30. Therefore, the configuration of the peripheral circuit of the FPGA 10 is simplified, and the number of parts and the manufacturing cost of the electric circuit 1 are reduced.

  In the present embodiment, the monitor unit 14 has been described as monitoring the voltage of the divided signal Ssense divided by the dividing resistor 30, but the present invention is not limited to this, and the field programmable gate array is not limited thereto. For example, the voltage of the supplied power may be monitored based on another signal such as a signal output from another component. However, when an appropriate signal for monitoring cannot be obtained, the necessary peripheral components are only divided resistors by monitoring the voltage of the signal Ssense by resistance division.

  In the present embodiment, the operation threshold Vth in the monitor of the monitor unit 14 has been described as the lowest voltage value at which the configuration data written in the RAM 12 is not lost. However, the present invention is not limited to this. is not. As the predetermined operation threshold value of the present invention, for example, a voltage value to which a certainty is given to the above-mentioned lowest voltage or a margin for absorbing variation for each product is added may be adopted. .

It is a circuit diagram which shows the structure of the field programmable gate array which is one Embodiment of this invention, and a peripheral circuit. 2 is a timing chart illustrating an example of signal fluctuations in each unit and an operation of a configuration circuit as the voltage Vcc of power supplied to the FPGA fluctuates in the electric circuit shown in FIG. 1. It is a figure which shows the connection of the power supply of FPGA in a prior art. It is a figure which shows the connection of the power supply of FPGA in another prior art.

Explanation of symbols

1 electric circuit 10 FPGA (field programmable gate array)
DESCRIPTION OF SYMBOLS 11 Configuration circuit 13 Logic construction part 14 Monitor part 15 Instruction part 16 Functional circuit 30 (30a, 30b) Dividing resistance 40 Pull-up resistance

Claims (2)

In a field programmable gate array that receives configuration data from the outside and constructs and executes a logic circuit corresponding to the loaded configuration data.
A monitor for monitoring whether the voltage of the power supplied to the field programmable gate array exceeds a predetermined operation threshold;
A field programmable gate array comprising: a loading instructing unit for instructing a new loading of external configuration data in response to the monitor unit receiving the voltage being equal to or lower than the operation threshold value.   The field programmable according to claim 1, wherein the monitoring unit monitors whether the voltage exceeds the operation threshold by monitoring a divided voltage obtained by dividing the voltage by resistance. Gate array.

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