CN216490429U - Power-on reset circuit and MCU - Google Patents
Power-on reset circuit and MCU Download PDFInfo
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- CN216490429U CN216490429U CN202123088758.XU CN202123088758U CN216490429U CN 216490429 U CN216490429 U CN 216490429U CN 202123088758 U CN202123088758 U CN 202123088758U CN 216490429 U CN216490429 U CN 216490429U
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Abstract
The application provides a power-on reset circuit and MCU, this power-on reset circuit includes: a reference voltage generator which generates a stable compensation reference voltage when the first power supply voltage reaches a first threshold value, and generates an enable signal of the first power-on reset signal generator when the first power supply voltage reaches a second threshold value, enables the first power-on reset signal generator, and generates a first power-on reset signal; the buck converter circuit converts the first supply voltage to a stable regulated second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together; the second power-on reset signal generator generates a second power-on reset signal for initialization when the first power-on reset signal and the second power supply voltage are enabled together. The method and the device can judge whether the power supply voltage reaches the required level more accurately, so that the core part of the integrated circuit is initialized accurately.
Description
Technical Field
The application relates to the technical field of electronics, in particular to a power-on reset circuit and an MCU.
Background
The power-on reset circuit is widely applied to circuit design and is an indispensable part for ensuring the stable and reliable operation of the whole electronic system.
At present, when an electronic system is turned on, an external power supply voltage is supplied to semiconductor devices of various element integrated circuits and ramps up during a certain time interval. During this power-on, the power-on reset circuit is used to reset the elements in the semiconductor device. Once the supply voltage of the integrated circuit within the semiconductor device reaches a desired level, the state of the semiconductor device is typically preset or initialized so that normal operation begins at the end of the power-up phase.
In the process of implementing the present application, the inventor finds that at least the following problems exist in the prior art: there is hysteresis in the determination that the power supply voltage reaches the required level, resulting in hysteresis in the semiconductor device entering a normal operating state.
SUMMERY OF THE UTILITY MODEL
The application provides a power-on reset circuit and an MCU (micro control unit) to solve the problem that hysteresis exists in the judgment that the power supply voltage reaches a required level in the conventional power-on reset circuit.
In a first aspect, the present application provides a power-on reset circuit, including:
a reference voltage generator powered by the first power supply voltage for generating a stable compensation reference voltage when the first power supply voltage reaches a first threshold value and generating an enable signal of the first power-on reset signal generator when the first power supply voltage reaches a second threshold value;
a first power-on reset signal generator powered by a first power supply voltage for generating a first power-on reset signal when enabled by an enable signal;
a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together;
the second power-on reset signal generator is used for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and the second power-on reset signal is used for initialization;
the first power-on reset signal generator is connected with the reference voltage generator.
Optionally, the power-on reset circuit further includes: and the trigger circuit is arranged between the first power-on reset signal generator and the first power supply voltage and is used for conducting the connection between the first power-on reset signal generator and the first power supply voltage under the action of the enabling signal.
Optionally, the first power-on reset signal generator and the second power-on reset signal generator both include: a non-linear voltage divider for inputting a first power voltage, the non-linear voltage divider including an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor; the level detector comprises an inverter, wherein the input end of the inverter is connected with the output end of the non-linear voltage divider, the output end of the inverter is connected with a first power supply voltage through a capacitor, and the level detector is used for outputting a first power-on reset signal according to a reference voltage.
Optionally, the first power-on reset signal generator further includes a control switch, configured to turn on a nonlinear voltage divider included in the first power-on reset signal generator when enabled by the enable signal, where the nonlinear voltage divider includes a first nonlinear voltage divider and a second nonlinear voltage divider, an output end of the first nonlinear voltage divider is connected to a first level detector including an inverter, and an output end of the second nonlinear voltage divider is connected to a second level detector including an inverter.
Optionally, the power-on reset circuit is used for a flash memory, and an output terminal of the flash memory is used for connecting to an output terminal of the second power-on reset signal generator to monitor the second power-on reset signal.
In a second aspect, the present application provides a power-on reset circuit, comprising:
a reference voltage generator powered by the first supply voltage for generating a stable compensation reference voltage when the first supply voltage reaches a compensation reference voltage threshold;
a first power-on reset signal generator powered by a first power supply voltage for generating a first power-on reset signal when the first power supply voltage reaches a first power-on reset signal voltage threshold;
a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together;
the second power-on reset signal generator is used for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and the second power-on reset signal is used for initializing a core part of the integrated circuit;
wherein the first power-on reset signal generator is not connected to the reference voltage generator.
Optionally, the first power-on reset signal generator and the second power-on reset signal generator both include: a non-linear voltage divider for inputting a first power voltage, the non-linear voltage divider including an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor; the level detector comprises an inverter, wherein the input end of the inverter is connected with the output end of the non-linear voltage divider, the output end of the inverter is connected with a first power supply voltage through a capacitor, and the level detector is used for outputting a first power-on reset signal according to a reference voltage.
Optionally, the first power-on reset signal generator further includes a control switch, configured to turn on a non-linear voltage divider included in the first power-on reset signal generator when enabled by the enable signal, where the non-linear voltage divider includes a first non-linear voltage divider and a second non-linear voltage divider, an output end of the first non-linear voltage divider is connected to a first level detector including an inverter, and an output end of the second non-linear voltage divider is connected to a second level detector including an inverter.
Optionally, the power-on reset circuit is used for a flash memory, and an output terminal of the flash memory is used for connecting to an output terminal of the second power-on reset signal generator to monitor the second power-on reset signal. The power-on reset circuit is used for the flash memory, whether the second power-on reset signal is stable or not can be determined when the flash memory is powered on, and an alarm can be given when the second power-on reset signal is unstable so as to optimize the stability of the second power-on reset signal.
The power-on reset circuit can prevent the reference voltage generator from triggering the first power-on reset signal generator to generate the first power-on reset signal by mistake, and improves the stability of the system.
In a third aspect, the present application provides an MCU, comprising: a power-on reset circuit and a core portion of the integrated circuit;
the power-on reset circuit includes: a reference voltage generator powered by the first power supply voltage for generating a stable compensation reference voltage when the first power supply voltage reaches a first threshold value and generating an enable signal of the first power-on reset signal generator when the first power supply voltage reaches a second threshold value; a first power-on reset signal generator powered by a first power supply voltage for generating a first power-on reset signal when enabled by an enable signal; a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together; a second power-on reset signal generator for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, the second power-on reset signal being used for initializing a core portion of the integrated circuit; the first power-on reset signal generator is connected with the reference voltage generator.
Optionally, the power-on reset circuit further includes: and the trigger circuit is arranged between the first power-on reset signal generator and the first power supply voltage and is used for conducting the connection between the first power-on reset signal generator and the first power supply voltage under the action of the enabling signal.
Optionally, the first power-on reset signal generator and the second power-on reset signal generator both include: a non-linear voltage divider for inputting a first power voltage, the non-linear voltage divider including an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor; the level detector comprises an inverter, wherein the input end of the inverter is connected with the output end of the non-linear voltage divider, the output end of the inverter is connected with a first power supply voltage through a capacitor, and the level detector is used for outputting a first power-on reset signal according to a reference voltage.
Optionally, the first power-on reset signal generator further includes a control switch, configured to turn on a nonlinear voltage divider included in the first power-on reset signal generator when enabled by the enable signal, where the nonlinear voltage divider includes a first nonlinear voltage divider and a second nonlinear voltage divider, an output end of the first nonlinear voltage divider is connected to a first level detector including an inverter, and an output end of the second nonlinear voltage divider is connected to a second level detector including an inverter.
Optionally, the power-on reset circuit is used for a flash memory, and an output terminal of the flash memory is used for connecting to an output terminal of the second power-on reset signal generator to monitor the second power-on reset signal.
Optionally, the MCU further comprises: and when the first power supply voltage is lower than the reset voltage threshold value, the power-on reset circuit controls the MCU to enter a reset state.
In a fourth aspect, the present application provides an MCU, comprising: a power-on reset circuit and a core portion of the integrated circuit;
the power-on reset circuit includes: a reference voltage generator powered by the first supply voltage for generating a stable compensation reference voltage when the first supply voltage reaches a compensation reference voltage threshold; a first power-on reset signal generator powered by a first power supply voltage for generating a first power-on reset signal when the first power supply voltage reaches a first power-on reset signal voltage threshold; a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together; the second power-on reset signal generator is used for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and the second power-on reset signal is used for initialization; wherein the first power-on reset signal generator is not connected to the reference voltage generator.
Optionally, the first power-on reset signal generator and the second power-on reset signal generator both include: a non-linear voltage divider for inputting a first power voltage, the non-linear voltage divider including an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor; the level detector comprises an inverter, wherein the input end of the inverter is connected with the output end of the non-linear voltage divider, the output end of the inverter is connected with a first power supply voltage through a capacitor, and the level detector is used for outputting a first power-on reset signal according to a reference voltage.
Optionally, the first power-on reset signal generator further includes a control switch, configured to turn on a nonlinear voltage divider included in the first power-on reset signal generator when enabled by the enable signal, where the nonlinear voltage divider includes a first nonlinear voltage divider and a second nonlinear voltage divider, an output end of the first nonlinear voltage divider is connected to a first level detector including an inverter, and an output end of the second nonlinear voltage divider is connected to a second level detector including an inverter.
Optionally, the power-on reset circuit is used for a flash memory, and an output terminal of the flash memory is used for connecting to an output terminal of the second power-on reset signal generator to monitor the second power-on reset signal.
Optionally, the MCU further comprises: and when the first power supply voltage is lower than the reset voltage threshold value, the power-on reset circuit controls the MCU to enter a reset state.
According to the power-on reset circuit and the MCU, the power-on reset circuit comprises a reference voltage generator, a first power-on reset signal generator, a buck converter circuit and a second power-on reset signal generator; the reference voltage generator is powered by a first power supply voltage, generates a stable compensation reference voltage when the first power supply voltage reaches a first threshold value, and generates an enabling signal of the first power-on reset signal generator when the first power supply voltage reaches a second threshold value; the first power-on reset signal generator is powered by a first power supply voltage and generates a first power-on reset signal when enabled by an enable signal; the buck converter circuit converts the first supply voltage to a stable regulated second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together; the second power-on reset signal generator generates a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and the second power-on reset signal is used for initialization. According to the method and the device, the reference voltage generator is firstly ensured to generate stable compensation reference voltage, and then the first power-on reset signal generator is enabled to generate the first power-on reset signal so as to reset the buck converter circuit and the second power-on reset signal generator, so that whether the power supply voltage reaches a required level can be accurately judged, and the core part of the integrated circuit is accurately initialized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic diagram of a power-on reset circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of signal transmission in a power-on reset circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a power-on reset circuit according to another embodiment of the present disclosure;
fig. 4 is a schematic diagram of a power-on reset circuit according to another embodiment of the present application;
fig. 5 is a schematic diagram of signal transmission in a power-on reset circuit according to another embodiment of the present application;
fig. 6 is a schematic diagram of a power-on reset signal generator according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a first power-on reset signal generator according to an embodiment of the present application;
fig. 8 is a schematic diagram of a principle of an MCU provided in an embodiment of the present application;
fig. 9 is a schematic diagram of a MCU according to another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The current power-on reset circuit has hysteresis in determining that a power supply voltage reaches a required level when it is used to reset an element in a semiconductor device, thereby causing the semiconductor device to enter a normal operation state. In addition, there is a problem that voltage ripple greatly increases the requirements for the service life and quality of certain components.
Based on the above problems, the present application provides a power-on reset circuit and an MCU, which can more accurately determine whether the power voltage reaches the required level by adjusting the compensation reference voltage generated by the reference voltage generator, so as to accurately initialize the core part of the integrated circuit.
Fig. 1 is a schematic diagram of a power-on reset circuit according to an embodiment of the present disclosure. As shown in fig. 1, a power-on reset circuit 100 according to an embodiment of the present application includes: a reference voltage generator 110, a first power-on reset signal generator 120, a buck converter circuit 130, and a second power-on reset signal generator 140. Wherein:
the reference voltage generator 110, powered by the first power voltage, is used to generate a stable compensation reference voltage when the first power voltage reaches a first threshold value, and to generate an enable signal of the first power-on reset signal generator 120 when the first power voltage reaches a second threshold value.
The first power-on reset signal generator 120 is powered by a first power supply voltage and generates a first power-on reset signal when enabled by an enable signal.
The buck converter circuit 130 is configured to convert the first power voltage into the second power voltage when the compensation reference voltage and the first power-on reset signal are enabled together.
The second power-on reset signal generator 140 is configured to generate a second power-on reset signal when the first power-on reset signal and the second power supply voltage are jointly enabled, where the second power-on reset signal is used for initialization.
The first power-on reset signal generator 120 is connected to the reference voltage generator 110.
In the embodiment of the present application, the first power supply voltage is an external power supply voltage, and the second power supply voltage is a stable regulated internal power supply voltage obtained by converting the first power supply voltage by the buck converter circuit 130. The first threshold is, for example, 1.7V, and the reference voltage generator 110 generates a stable compensation reference voltage when the first power supply voltage reaches 1.7V. The second threshold may be set based on a voltage value of the first power supply voltage during the ramp-up, and the reference voltage generator 110 generates an enable signal of the first power-on reset signal generator 120, such as a high-level signal or a low-level signal, when the first power supply voltage reaches the second threshold. The first power-on reset signal is, for example, a voltage signal, and the first power-on reset signal is gradually increased during the first power supply voltage ramp-up period to reset the buck converter circuit 130 and the second power-on reset signal generator 140. The second power-on reset signal is, for example, a voltage signal for resetting and initializing a core portion of the integrated circuit, specifically, a core portion of the integrated circuit, such as a digital integrated circuit.
For example, fig. 2 is a schematic diagram of signal transmission in the power-on reset circuit according to an embodiment of the present application, and as shown in fig. 2, during the ramp-up period of the first power supply voltage, the reference voltage generator 110 generates a stable compensation reference voltage when the first power supply voltage reaches the first threshold value, and outputs the compensation reference voltage to the buck converter circuit 130. Meanwhile, the reference voltage generator 110 generates an enable signal of the first power-on reset signal generator 120 when the first power voltage reaches the second threshold value, and outputs the enable signal to the first power-on reset signal generator 120. The first power-on reset signal generator 120 is supplied with a first power supply voltage, and generates a first power-on reset signal when enabled by an enable signal of the first power-on reset signal generator 120. The first power-on reset signal generator 120 outputs the first power-on reset signal to the buck converter circuit 130 and the second power-on reset signal generator 140, respectively. The buck converter circuit 130 converts the first power supply voltage to a stable regulated second power supply voltage when the compensation reference voltage and the first power-on-reset signal are enabled together, and outputs the second power supply voltage to the second power-on-reset signal generator 140 and a core portion of the integrated circuit. The second power-on reset signal generator 140 generates a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and outputs the second power-on reset signal to a core portion of the integrated circuit to initialize the core portion of the integrated circuit.
The power-on reset circuit provided by the embodiment of the application comprises a reference voltage generator, a first power-on reset signal generator, a buck converter circuit and a second power-on reset signal generator; the reference voltage generator is powered by a first power supply voltage, generates a stable compensation reference voltage when the first power supply voltage reaches a first threshold value, and generates an enabling signal of the first power-on reset signal generator when the first power supply voltage reaches a second threshold value; the first power-on reset signal generator is powered by a first power supply voltage and generates a first power-on reset signal when enabled by an enable signal; the buck converter circuit converts the first supply voltage to a stable regulated second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together; the second power-on reset signal generator generates a second power-on reset signal when the first power-on reset signal and a second power supply voltage are enabled together, the second power-on reset signal being used for initializing a core portion of the integrated circuit. According to the embodiment of the application, the reference voltage generator is firstly ensured to generate stable compensation reference voltage, and then the first power-on reset signal generator is enabled to generate the first power-on reset signal so as to reset the buck converter circuit and the second power-on reset signal generator, so that whether the power supply voltage reaches the required level can be accurately judged, and the core part of the integrated circuit is accurately initialized.
Based on the above embodiments, fig. 3 is a schematic diagram of a power-on reset circuit according to another embodiment of the present application. As shown in fig. 3, the power-on reset circuit 100 according to the embodiment of the present application further includes: and a trigger circuit 150 disposed between the first power-on reset signal generator 120 and the first power voltage, wherein the trigger circuit 150 is configured to conduct the connection between the first power-on reset signal generator 120 and the first power voltage under the action of the enable signal.
Illustratively, the trigger circuit 150 is, for example, a switch circuit. The trigger circuit 150 turns on the connection of the first power-on reset signal generator 120 with the first power supply voltage under the enable of the enable signal of the first power-on reset signal generator 120 generated by the reference voltage generator 110, so that the first power-on reset signal generator 120 is powered by the first power supply voltage.
Fig. 4 is a schematic diagram of a power-on reset circuit according to another embodiment of the present disclosure. As shown in fig. 4, the power-on reset circuit 400 according to the embodiment of the present application includes: a reference voltage generator 410, a first power-on reset signal generator 420, a buck converter circuit 430, and a second power-on reset signal generator 440. Wherein:
the reference voltage generator 410, powered by the first power supply voltage, is configured to generate a stable compensated reference voltage when the first power supply voltage reaches a compensated reference voltage threshold.
The first power-on-reset signal generator 420, powered by the first power supply voltage, is configured to generate a first power-on-reset signal when the first power supply voltage reaches a first power-on-reset signal voltage threshold.
The buck converter circuit 430 is configured to convert the first power voltage to the second power voltage when the compensation reference voltage and the first power-on reset signal are enabled together.
The second power-on reset signal generator 440 is configured to generate a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, where the second power-on reset signal is used for initialization.
Wherein the first power-on reset signal generator 420 is not connected to the reference voltage generator 410.
In the embodiment of the present application, for example, the compensation reference voltage threshold may be set based on the voltage value of the first power supply voltage during the ramp-up, and the reference voltage generator 410 generates a stable compensation reference voltage when the first power supply voltage reaches the compensation reference voltage threshold. The first power-on reset signal voltage threshold is, for example, 1.7V, the first power-on reset signal generator 420 generates the first power-on reset signal when the first power supply voltage reaches the first power-on reset signal voltage threshold. The first power-on reset signal is, for example, a voltage signal, and the first power-on reset signal is gradually increased during the first power supply voltage ramp-up period to reset the buck converter circuit 430 and the second power-on reset signal generator 440. The second power-on reset signal is, for example, a voltage signal for resetting and initializing a core portion of the integrated circuit, specifically, a core portion of the integrated circuit, such as a digital integrated circuit.
Fig. 5 is a schematic diagram of signal transmission in a power-on reset circuit according to another embodiment of the present application, and as shown in fig. 5, the first power-on reset signal generator 420 is not connected to the reference voltage generator 410. During the ramp-up of the first power supply voltage, the reference voltage generator 410 generates a stable compensation reference voltage when the first power supply voltage reaches the compensation reference voltage threshold, and outputs the compensation reference voltage to the buck converter circuit 430. The first power-on-reset signal generator 420 is supplied with a first power supply voltage, and generates a first power-on-reset signal when the first power supply voltage reaches a first power-on-reset signal voltage threshold. The first power-on reset signal generator 420 outputs a first power-on reset signal to the buck converter circuit 430 and the second power-on reset signal generator 440, respectively. The buck converter circuit 430 converts the first power supply voltage to a regulated second power supply voltage when the compensation reference voltage and the first power-on-reset signal are enabled together, and outputs the second power supply voltage to the second power-on-reset signal generator 440 and a core portion of the integrated circuit. The second power-on reset signal generator 440 generates a second power-on reset signal when the first power-on reset signal and the second power voltage are enabled together, and outputs the second power-on reset signal to the core portion of the integrated circuit to initialize the core portion of the integrated circuit.
The power-on reset circuit provided by the embodiment of the application comprises a reference voltage generator, a first power-on reset signal generator, a buck converter circuit and a second power-on reset signal generator; the reference voltage generator is powered by a first power supply voltage, and generates a stable compensation reference voltage when the first power supply voltage reaches a compensation reference voltage threshold value; the first power-on reset signal generator is powered by a first power supply voltage and generates a first power-on reset signal when the first power supply voltage reaches a first power-on reset signal voltage threshold; the buck converter circuit converts the first supply voltage to a stable regulated second supply voltage when the compensation reference voltage and the first power-on reset signal are enabled together; the second power-on reset signal generator generates a second power-on reset signal when the first power-on reset signal and a second power supply voltage are enabled together, the second power-on reset signal being used for initializing a core portion of the integrated circuit. In the embodiment of the application, the first power-on reset signal generator is not connected with the reference voltage generator, the reference voltage generator does not depend on the first power-on reset signal generator to generate stable compensation reference voltage, and the first power-on reset signal generator generates a first power-on reset signal when the first power voltage reaches a voltage threshold of the first power-on reset signal so as to reset the buck converter circuit and the second power-on reset signal generator, so that whether the power voltage reaches a required level can be more accurately judged, and a core part of the integrated circuit is accurately initialized; meanwhile, the reference voltage generator can be prevented from triggering the first power-on reset signal generator to generate the first power-on reset signal by mistake, and the stability of the system is improved.
Based on the above embodiments, fig. 6 is a schematic diagram of a principle of a power-on reset signal generator according to an embodiment of the present application, and may be applied to a first power-on reset signal generator and a second power-on reset signal generator. As shown in fig. 6, the power-on reset signal generator 600 according to the embodiment of the present application includes: a non-linear voltage divider 610 for inputting a first power voltage, the non-linear voltage divider including an active resistor 611 and at least one passive resistor 612 connected in series, the non-linear voltage divider 610 for dividing the input first power voltage by the active resistor 611 and the at least one passive resistor 612 to output a reference voltage at an output terminal of the non-linear voltage divider 610 according to the active resistor 611 and the at least one passive resistor 612; the level detector 620 comprises an inverter 621, an input terminal of the inverter 621 is connected to an output terminal of the non-linear voltage divider 610, an output terminal of the inverter 621 is connected to the first power voltage via a capacitor 622, and the level detector 620 is configured to output a first power-on reset signal according to a reference voltage.
Illustratively, the active resistor 611 is, for example, a PMOS active resistor, and the passive resistor 612 is, for example, a P + diffused passive resistor, and the PMOS active resistor and the P + diffused passive resistor form the non-linear voltage divider 610. Among them, the PMOS active resistor can enhance the response time when the power-up ramp time is fast, and the P + diffused passive resistor can secure a stable resistance value with respect to process spread and can prevent a possible ground bounce (ground bounce) during an internal operation. The inverter 621 includes, for example, one PMOS and two NMOS. When the first power supply voltage starts to ramp up, the non-linear voltage divider 610 determines a reference voltage by dividing the first power supply voltage by a ratio of the active resistor 611 and the passive resistor 612, and then outputs the reference voltage to the inverter 621, and the level detector 620 outputs a first power-on reset signal according to the reference voltage. When the reference voltage reaches the threshold voltage of the inverter 621, the first power-on reset signal switches to low, i.e., outputs a low level signal. The capacitor 622 may be formed of a P + junction diode, and the coupling effect on the reference voltage caused by the P + diffused passive resistor is effectively compensated by the capacitor 622.
Based on the above embodiments, fig. 7 is a schematic diagram of a first power-on reset signal generator according to an embodiment of the present application, and as shown in fig. 7, the first power-on reset signal generator 700 includes: the control switch 710 is configured to, when enabled by an enable signal of the first power-on reset signal generator 700, turn on the non-linear voltage divider 720 included in the first power-on reset signal generator 700, so that the output terminal of the non-linear voltage divider 720 outputs the reference voltage. The output terminal of the non-linear voltage divider 720 is connected to a level detector 730 comprising an inverter, so that the level detector 730 outputs a first power-on reset signal according to the reference voltage. Wherein the non-linear voltage divider 720 includes a first non-linear voltage divider 721 and a second non-linear voltage divider 722, the level detector 730 includes a first level detector 731 including an inverter and a second level detector 732 including an inverter; an output of the first non-linear voltage divider 721 is connected to an input of a first level detector 731 and an output of the second non-linear voltage divider 722 is connected to an input of a second level detector 732.
Specifically, the enable signal of the first power-on reset signal generator 700 is, for example, a low level signal, and the control switch 710 turns on the contact a when enabled by the enable signal, at which time, the first non-linear voltage divider 721 and the first level detector 731 enter an active state, and the second non-linear voltage divider 722 and the second level detector 732 are at a ground potential, i.e., an inactive state. The first power supply voltage is input to the first nonlinear voltage divider 721 and the first level detector 731, thereby outputting a first power-on reset signal. The first power-on reset signal is initially increased in steps, and is switched to low, i.e., outputs a low level signal, when the reference voltage output to the first level detector 731 by the first non-linear voltage divider 721 reaches the threshold voltage of the first level detector 731.
When the enable signal of the first power-on reset signal generator 700 is, for example, a high level signal, the control switch 710 turns on the contact B when enabled by the enable signal, and at this time, the first non-linear voltage divider 721 and the first level detector 731 are both at ground potential, i.e., in an inactive state, while the second non-linear voltage divider 722 and the second level detector 732 enter an active state. The first power supply voltage is input to the second non-linear voltage divider 722 and the second level detector 732, thereby outputting a first power-on reset signal. The first power-on reset signal is initially increased in steps, and is switched to low when the reference voltage output from the second non-linear voltage divider 722 to the second level detector 732 reaches the threshold voltage of the second level detector 732, i.e., a low level signal is output.
It should be noted that in the embodiment of the present application, the first power-on reset signal generator 700 supports a first power voltage rating of the power-on reset circuit, such as 3.0V, through the first non-linear voltage divider 721 and the first level detector 731; another first supply voltage rating, such as 1.80V, for the power-on-reset circuit is supported by the second non-linear voltage divider 722 and the second level detector 732. Wherein the selection of two different first power supply voltage ratings is made by controlling switch 710 under the enable signal of first power-on-reset signal generator 700.
Embodiments of the present application may allow sufficient flexibility in controlling the standby current for each selected power supply voltage configuration by supporting two different ratings of the first power supply voltage.
On the basis of the above embodiment, the power-on reset circuit may be used in a flash memory, and an output terminal of the flash memory is used for connecting to an output terminal of the second power-on reset signal generator to monitor the second power-on reset signal.
For example, flash memory typically designs two output pad pins to be commonly implemented in a memory device, wherein one pad pin may be used for parametric testing, functional testing, and assembly, while the other pad pin is typically not used, and therefore, this unused pad pin may be developed to be connected to the output of the second power-on-reset signal generator, and the second power-on-reset signal is monitored during power-on reset to determine whether the second power-on-reset signal is stable when the flash is powered on. An alarm may be issued when the second power-on reset signal is unstable to optimize the stability of the second power-on reset signal.
Fig. 8 is a schematic diagram of a principle of an MCU provided in an embodiment of the present application. As shown in fig. 8, the MCU800 of the embodiment of the present application includes: a power-on-reset circuit 100 and a core portion 820 of the integrated circuit. The power-on reset circuit 100 includes: a reference voltage generator 110, a first power-on reset signal generator 120, a buck converter circuit 130, and a second power-on reset signal generator 140; the reference voltage generator 110, powered by the first power voltage, is configured to generate a stable compensation reference voltage when the first power voltage reaches a first threshold, and generate an enable signal of the first power-on reset signal generator 120 when the first power voltage reaches a second threshold; a first power-on reset signal generator 120, powered by a first power supply voltage, for generating a first power-on reset signal when enabled by an enable signal; a buck converter circuit 130 for converting the first supply voltage to a stable regulated second supply voltage when the compensation reference voltage and the first power-on-reset signal are jointly enabled; and a second power-on reset signal generator 140 for generating a second power-on reset signal for initializing the core portion 820 of the integrated circuit when the first power-on reset signal and the second power supply voltage are jointly enabled. The first power-on reset signal generator 120 is connected to the reference voltage generator 110.
Illustratively, when the MCU800 powers on, the reference voltage generator 110 is powered by the first power voltage, generates a stable compensation reference voltage when the first power voltage reaches a first threshold, and generates an enable signal of the first power-on reset signal generator 120 when the first power voltage reaches a second threshold, so as to enable the first power-on reset signal generator 120 to generate the first power-on reset signal, and further enable the second power-on reset signal generator 140 to generate the second power-on reset signal, after a delay of about 50ms to 200ms, the first power-on reset signal and the second power-on reset signal will be released, so that the MCU800 initializes, thereby ensuring that the MCU800 can initialize normally when powered on, and ensuring that the program works normally and stably.
The MCU that this application embodiment provided, including power-on reset circuit, can improve MCU internal work's when the power-on through power-on reset circuit voltage signal's stability.
In some embodiments, the power-on-reset circuit 100 further comprises: and a trigger circuit arranged between the first power-on reset signal generator 120 and the first power supply voltage, the trigger circuit being configured to conduct the connection between the first power-on reset signal generator 120 and the first power supply voltage under the effect of the enable signal.
Optionally, the first power-on reset signal generator 120 and the second power-on reset signal generator 140 each include: a non-linear voltage divider for inputting a first power voltage, the non-linear voltage divider including an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor; the level detector comprises an inverter, wherein the input end of the inverter is connected with the output end of the non-linear voltage divider, the output end of the inverter is connected with a first power supply voltage through a capacitor, and the level detector is used for outputting a first power-on reset signal according to a reference voltage.
Optionally, the first power-on reset signal generator 120 further includes a control switch, configured to turn on a non-linear voltage divider included in the first power-on reset signal generator 120 when enabled by the enable signal, where the non-linear voltage divider includes a first non-linear voltage divider and a second non-linear voltage divider, an output end of the first non-linear voltage divider is connected to a first level detector including an inverter, and an output end of the second non-linear voltage divider is connected to a second level detector including an inverter.
Optionally, the power-on reset circuit 100 is used in a flash memory, and an output of the flash memory is used to connect to an output of the second power-on reset signal generator 140 to monitor the second power-on reset signal.
On the basis of the above embodiment, when the first power supply voltage is lower than the reset voltage threshold, the power-on reset circuit 100 controls the MCU800 to enter the reset state.
Illustratively, the reset voltage threshold is, for example, 0.3V. When the first power voltage is lower than the reset voltage threshold due to power failure or other reasons, the reference voltage generator 110 of the power-on reset circuit 100 starts to output a "0" level signal to the reset terminal of the MCU800, that is, outputs a low level signal to the reset terminal of the MCU800, and further forces the MCU800 to enter a reset state in advance, that is, a backup state is protected, thereby ensuring that data in the MCU800 is not lost due to power failure.
Fig. 9 is a schematic diagram of a MCU according to another embodiment of the present application. As shown in fig. 9, the MCU900 of the embodiment of the present application includes: a power-on-reset circuit 400 and a core portion 920 of the integrated circuit. The power-on reset circuit 400 includes: a reference voltage generator 410, a first power-on-reset signal generator 420, a buck converter circuit 430 and a second power-on-reset signal generator 440. The reference voltage generator 410 is powered by the first power voltage and is configured to generate a stable compensation reference voltage when the first power voltage reaches a compensation reference voltage threshold. The first power-on-reset signal generator 420, powered by the first power supply voltage, is configured to generate a first power-on-reset signal when the first power supply voltage reaches a first power-on-reset signal voltage threshold. A buck converter circuit 430 for converting the first supply voltage to a regulated second supply voltage when the compensation reference voltage and the first power-on-reset signal are jointly enabled. The second power-on reset signal generator 440 is configured to generate a second power-on reset signal when the first power-on reset signal and the second power supply voltage are jointly enabled, the second power-on reset signal being used to initialize the core portion 920 of the integrated circuit. Wherein the first power-on reset signal generator 420 is not connected to the reference voltage generator 410.
Optionally, the first power-on reset signal generator 420 and the second power-on reset signal generator 440 each include: a non-linear voltage divider for inputting a first power voltage, the non-linear voltage divider including an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor; the level detector comprises an inverter, wherein the input end of the inverter is connected with the output end of the non-linear voltage divider, the output end of the inverter is connected with a first power supply voltage through a capacitor, and the level detector is used for outputting a first power-on reset signal according to a reference voltage.
Optionally, the first power-on reset signal generator 420 further includes a control switch, configured to turn on a non-linear voltage divider included in the first power-on reset signal generator 420 when enabled by the enable signal, where the non-linear voltage divider includes a first non-linear voltage divider and a second non-linear voltage divider, an output end of the first non-linear voltage divider is connected to a first level detector including an inverter, and an output end of the second non-linear voltage divider is connected to a second level detector including an inverter.
Optionally, the power-on reset circuit 400 is used in a flash memory, and an output terminal of the flash memory is used to connect to an output terminal of the second power-on reset signal generator 440 to monitor the second power-on reset signal.
On the basis of the above embodiment, when the first power supply voltage is lower than the reset voltage threshold, the power-on reset circuit 400 controls the MCU900 to enter the reset state.
It is to be understood that the various numerical references referred to in the embodiments of the present application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of the present application. In the embodiment of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (11)
1. A power-on-reset circuit, comprising:
a reference voltage generator powered by a first power supply voltage for generating a compensation reference voltage when the first power supply voltage reaches a first threshold value and generating an enable signal of a first power-on reset signal generator when the first power supply voltage reaches a second threshold value;
a first power-on reset signal generator, powered by the first power supply voltage, for generating a first power-on reset signal when enabled by the enable signal;
a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on-reset signal are enabled together;
and the second power-on reset signal generator is used for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and the second power-on reset signal is used for initialization.
2. The power-on-reset circuit of claim 1, further comprising:
and the trigger circuit is arranged between the first power-on reset signal generator and the first power supply voltage and is used for conducting the connection between the first power-on reset signal generator and the first power supply voltage under the action of the enabling signal.
3. A power-on-reset circuit, comprising:
a reference voltage generator powered by a first supply voltage for generating a compensation reference voltage when the first supply voltage reaches a compensation reference voltage threshold;
a first power-on-reset signal generator powered by the first supply voltage for generating a first power-on-reset signal when the first supply voltage reaches a first power-on-reset signal voltage threshold;
a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on-reset signal are enabled together;
the second power-on reset signal generator is used for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, and the second power-on reset signal is used for initialization;
wherein the first power-on-reset signal generator is not connected to the reference voltage generator.
4. A power-on-reset circuit according to any of claims 1 to 3, wherein the first power-on-reset signal generator and the second power-on-reset signal generator each comprise:
a non-linear voltage divider for inputting the first power supply voltage, the non-linear voltage divider comprising an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power supply voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor;
the level detector comprises an inverter, the input end of the inverter is connected with the output end of the nonlinear voltage divider, the output end of the inverter is connected with the first power supply voltage through a capacitor, and the level detector is used for outputting the first power-on reset signal according to the reference voltage.
5. The power-on reset circuit according to claim 4, wherein the first power-on reset signal generator further comprises a control switch for turning on a non-linear voltage divider included in the first power-on reset signal generator when enabled by the enable signal, the non-linear voltage divider comprises a first non-linear voltage divider and a second non-linear voltage divider, an output end of the first non-linear voltage divider is connected with a first level detector including an inverter, and an output end of the second non-linear voltage divider is connected with a second level detector including an inverter.
6. A power-on-reset circuit according to any of claims 1 to 3, wherein the power-on-reset circuit is used in a flash memory, and an output of the flash memory is used to connect to an output of the second power-on-reset signal generator to monitor the second power-on-reset signal.
7. An MCU, comprising: a power-on reset circuit and a core portion of the integrated circuit;
the power-on reset circuit includes: a reference voltage generator powered by a first power supply voltage for generating a compensation reference voltage when the first power supply voltage reaches a first threshold value and generating an enable signal of a first power-on reset signal generator when the first power supply voltage reaches a second threshold value; a first power-on reset signal generator, powered by the first power supply voltage, for generating a first power-on reset signal when enabled by the enable signal; a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on-reset signal are enabled together; a second power-on reset signal generator for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, the second power-on reset signal being used for initializing a core portion of the integrated circuit; wherein the first power-on reset signal generator is connected with the reference voltage generator.
8. The MCU of claim 7, wherein the power-on-reset circuit further comprises: and the trigger circuit is arranged between the first power-on reset signal generator and the first power supply voltage and is used for conducting the connection between the first power-on reset signal generator and the first power supply voltage under the action of the enabling signal.
9. An MCU, comprising: a power-on reset circuit and a core portion of the integrated circuit;
the power-on reset circuit includes: a reference voltage generator powered by a first supply voltage for generating a compensation reference voltage when the first supply voltage reaches a compensation reference voltage threshold; a first power-on-reset signal generator powered by the first supply voltage for generating a first power-on-reset signal when the first supply voltage reaches a first power-on-reset signal voltage threshold; a buck converter circuit for converting the first supply voltage to a second supply voltage when the compensation reference voltage and the first power-on-reset signal are enabled together; a second power-on reset signal generator for generating a second power-on reset signal when the first power-on reset signal and the second power supply voltage are enabled together, the second power-on reset signal being used for initializing a core portion of the integrated circuit; wherein the first power-on-reset signal generator is not connected to the reference voltage generator.
10. The MCU of any one of claims 7 to 9, wherein the first power-on reset signal generator and the second power-on reset signal generator each comprise:
a non-linear voltage divider for inputting the first power supply voltage, the non-linear voltage divider comprising an active resistor and at least one passive resistor connected in series with each other, the non-linear voltage divider for dividing the input first power supply voltage by the active resistor and the at least one passive resistor to output a reference voltage at an output terminal of the non-linear voltage divider according to the active resistor and the at least one passive resistor;
the level detector comprises an inverter, the input end of the inverter is connected with the output end of the nonlinear voltage divider, the output end of the inverter is connected with the first power supply voltage through a capacitor, and the level detector is used for outputting the first power-on reset signal according to the reference voltage.
11. The MCU of any one of claims 7 to 9, further comprising:
and when the first power supply voltage is lower than a reset voltage threshold value, the power-on reset circuit controls the MCU to enter a reset state.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123088758.XU CN216490429U (en) | 2021-12-09 | 2021-12-09 | Power-on reset circuit and MCU |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123088758.XU CN216490429U (en) | 2021-12-09 | 2021-12-09 | Power-on reset circuit and MCU |
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| CN216490429U true CN216490429U (en) | 2022-05-10 |
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| CN202123088758.XU Active CN216490429U (en) | 2021-12-09 | 2021-12-09 | Power-on reset circuit and MCU |
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