JP2006209876A - Electronic control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an electronic control device in no danger of being changed over to another mode even when noise is superposed on an operation mode selecting terminal in a data rewrite mode. <P>SOLUTION: A mode determination circuit 22 determines the operation mode to the rewrite mode when each level of the operation mode selecting terminal T1 and a test mode transition enable terminal MD0, where a latch circuit L1 is latched when a reset signal becomes inactive, is L and H respectively. Therefore, there is no danger of being changed over to another mode even when noise is superposed on the operation mode selecting terminal T1 when and after the mode is changed to the data rewrite mode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic control device capable of rewriting data by connecting a data writing device.

Conventionally, an electronic control device of this type shown in FIG. 5 is known. FIG. 5 is a conceptual diagram when a microcomputer (hereinafter referred to as a microcomputer) as an electronic control device and a data writing device (hereinafter referred to as a writer) are connected.
The microcomputer 2 includes three operation mode selection terminals T1 to T3, and each operation mode selection terminal T1 to T3 is connected to the writer 5 respectively. The microcomputer 2 includes a mode decode circuit 23 that determines an operation mode based on an active or inactive combination of signals output from the operation mode selection terminals T1 to T3. For example, as the operation mode, user mode (also called normal mode), test mode for testing at the time of factory shipment, data rewrite mode for rewriting data stored in the flash ROM built in the microcomputer, etc. are set. Has been. When the mode decode circuit 23 determines that the data rewrite mode is selected, the serial communication circuit 24 receives serial data from the writer 5 via the serial communication terminals SIN, SOUT, and SCLK, and the received data is stored in the flash memory. The data is written into the flash ROM 26 under the control of the rewrite control circuit 25.

JP 2001-325243 A

  However, the conventional microcomputer 2 may be switched to another mode when noise is superimposed on the operation mode selection terminals T1 to T3.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize an electronic control device that is not likely to switch to another mode even when noise is superimposed on an operation mode selection terminal.

In order to achieve the above object, according to the present invention, in the electronic control device (1) to which the data writing device (5) can be connected, a reset terminal for inputting a reset signal from the data writing device. (RESN), an operation mode selection terminal (T1 to T3) for inputting an operation mode selection signal for determining a predetermined mode from a plurality of operation modes including a data rewrite mode, from the data writing device, An enable terminal (MD0) for inputting a permission signal for permitting switching from the data writing device, a data communication terminal (ESIN, ESOUT, ESCK) for performing data communication with the data writing device, and this data A first storage medium (26) for storing data input from a communication terminal, the reset terminal, and an operation mode selection The level of the signal appearing at each of the terminal and the enable terminal is monitored, and the level of the enable signal appearing at the enable terminal and the operation mode selection terminal when the reset signal input from the reset terminal reaches a level indicating reset release. The operation mode selection means (22) that latches the level of the operation mode selection signal that appears, and determines the operation mode based on the level of each latched signal, and the operation mode determination means, which rewrites the operation mode to the data A technical means for storing data output from the data writing device when the mode is determined, in the first storage medium via the data communication terminal is used.
In the embodiment described later, the ECU 1 corresponds to the electronic control device of claim 1 and the writer 5 corresponds to the data writing device. The test mode transition enable signal corresponds to the permission signal, and the test mode transition enable terminal MD0 corresponds to the enable terminal. The serial data input terminal ESIN corresponds to the data communication terminal, the flash ROM 26 corresponds to the first storage medium, and the mode determination circuit 22 corresponds to the mode determination means.

  According to a second aspect of the present invention, in the electronic control unit (1) according to the first aspect, the operation mode selection terminals (T1 to T3) are connected to the operation mode determined by the operation mode determining means (22). After the determination is completed, a technical means that the terminal can be used as a terminal other than the operation mode selection terminal is used.

According to a third aspect of the present invention, the electronic control device (1) according to the first or second aspect further comprises a second storage medium (3) for storing data, wherein the operation mode selection is performed. An input line (3a) connected to a chip select terminal (CS) provided in the second storage medium is connected to an input line (2a) connected to the terminals (T1 to T3), and the chip The technical means that the select terminal is set to have a polarity opposite to the polarity of the operation mode selection terminal when in the data rewrite mode is used.
“Polarity” indicates whether the voltage appearing at the terminal is active or inactive, and “reverse polarity” indicates that when one terminal is active, the other terminal is inactive. It is a property.

According to a fourth aspect of the present invention, in the electronic control unit (1) according to the third aspect, the data communication lines (2b, 2c) connected to the data communication terminals (ESIN, ESOUT, ESCK) The technical means that the data communication lines (3b, 3c) connected to the data communication terminals (DO, DI, SCK) of the second storage medium (3) are connected is used.
In addition, the code | symbol in the said parenthesis respond | corresponds with the code | symbol in embodiment of the invention mentioned later.

  According to the first to fourth aspects of the invention, the levels of the signals appearing at the reset terminal, the operation mode selection terminal, and the enable terminal are monitored, and when the reset signal reaches a level indicating reset release, The level of the enable signal that appears and the level of the operation mode selection signal that appears at the operation mode selection terminal can be latched, and the operation mode can be determined based on the level of each latched signal. Even when noise is superimposed on the selection terminal, there is no possibility of switching to another mode.

  According to the second aspect of the invention, the operation mode selection terminal can be used as a terminal other than the operation mode selection terminal after the operation mode determination by the operation mode determination means is completed. The number can be increased.

  According to the invention of claim 3, since the input line connected to the chip select terminal provided in the second storage medium is connected to the input line connected to the operation mode selection terminal, that is, the input line is Since it is shared, the number of lines connected to the data writing device can be reduced as compared with the case where it is not shared, so that the electronic control device can be reduced in size. Since the chip select terminal has a polarity opposite to the polarity of the operation mode selection terminal when in the data rewrite mode, the second storage medium is in the middle of writing data to the first storage medium. There is no risk of becoming active.

  According to the invention of claim 4, since the data communication line connected to the data communication terminal of the second storage medium is connected to the data communication line connected to the data communication terminal, that is, the data communication line is Since it is shared, the number of lines connected to the data writing device can be reduced as compared with the case where it is not shared, so that the electronic control device can be reduced in size. Since the chip select terminal has a polarity opposite to the polarity of the operation mode selection terminal when in the data rewrite mode, the second storage medium is in the middle of writing data to the first storage medium. There is no risk of becoming active.

  The best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram showing an outline of a state where an electronic control device and a writer according to this embodiment are connected, and FIG. 2 is an explanatory diagram showing a main configuration of a microcomputer provided in the electronic control device shown in FIG. FIG. FIG. 3 is a circuit diagram of a mode determination circuit provided in the microcomputer shown in FIG. 2, and FIG. 4 is a mode chart showing the correspondence between the signal level of each terminal and the mode in the mode determination circuit shown in FIG. is there. In this embodiment, an electronic control unit (ECU) mounted on a vehicle will be described as an example of the electronic control device according to the present invention.

[Main configuration]
First, main components of the ECU and the writer will be described.
As shown in FIG. 1, the ECU 1 connects a microcomputer 2 that performs vehicle engine control and travel control, an EEPROM 3 that stores rewritable data unique to the vehicle, and a writer 5 that writes data to the flash ROM 26. A terminal board 1a. The terminal board 1a has a 5V monitoring terminal for monitoring the 5V power supplied to the microcomputer 2 by the writer 5, a reset terminal RESN for inputting a reset signal output from the writer 5, and an output from the writer 5. A test mode transition enable terminal MD for inputting a test mode transition enable signal (a signal for permitting mode transition), a serial data input terminal SIN for inputting serial data output from the writer 5, and a microcomputer 2 includes a serial data output terminal SOUT for outputting serial data, a clock terminal SCLK for inputting a clock signal for controlling the output of serial data from the writer 5, and an operation mode selection signal for selecting an operation mode. Connect the operation mode selection terminal SELN for input and the ground line. Ground and the terminal GND are provided.
The 5V monitoring terminal, reset terminal RESN, test mode transition enable terminal MD, serial data input terminal SIN, serial data output terminal SOUT, clock terminal SCLK, operation mode selection terminal SELN and GND terminal provided on the terminal board 1a are respectively The microcomputer 2 is connected to a 5V monitoring terminal VDD5VO, a reset terminal RESN, a test mode transition enable terminal MD0, a serial data input terminal ESIN, a serial data output terminal ESOUT, a clock terminal ESCK, an operation mode selection terminal ESBSY, and a ground terminal GNDI. .

The input line 2a that connects the operation mode selection terminal SELN of the terminal board 1a and the operation mode selection terminal ESBSY of the microcomputer 2 is connected to the chip select terminal CS of the EEPROM 3 by the input line 3a. That is, the input lines 2a and 3a are shared.
The data communication line 2b connecting the serial data input terminal SIN of the terminal board 1a and the serial data input terminal ESIN of the microcomputer 2 is connected to the data output terminal DO of the EEPROM 3 by the data communication line 3b. The data communication line 2c that connects the data output terminal SOUT and the serial data output terminal ESOUT of the microcomputer 2 is connected to the data input terminal DI of the EEPROM 3 by the data communication line 3c. That is, the data communication lines 2b and 3b and the data communication lines 2c and 3c are shared.
A line 2d connecting the clock terminal SCLK of the terminal board 1a and the clock terminal ESCK of the microcomputer 2 is connected to the clock terminal SCK of the EEPROM 3 by the line 3d. That is, the lines 2d and 3d are shared.
A pull-down resistor R5 is connected to a line 2e that connects the test mode transition enable terminal MD of the terminal board 1a and the test mode transition enable terminal MD0 of the microcomputer 2. In addition, pull-down resistors R1, R2, and R3 are connected to the lines 3a, 3d, and 3c, respectively.

As shown in FIG. 2, the microcomputer 2 includes a power-on reset generation circuit 21 for setting itself to a system reset state when 5V power is not supplied, a mode determination circuit 22 for determining an operation mode, A serial communication circuit 24 for communicating serial data with the writer 5 and a flash rewrite control circuit 25 for performing control for writing data received by the serial communication circuit 24 into the flash ROM 26 are provided.
As shown in FIG. 4, the operation mode of the microcomputer 2 depends on the terminal states of the test mode transition enable terminal MD0 and the operation mode selection terminals T1 to T3, the user mode (also referred to as normal mode), the rewrite mode, and the test modes 1 to 4. A total of six modes are selected. The operation mode selection terminal T1 and the test mode transition enable terminal MD0 are input to the AND circuit A1, and the output of the AND circuit A1 is input to the D terminal of the latch circuit L1. The operation mode selection terminal T2 and the test mode transition enable terminal MD0 are input to the AND circuit A2, and the output of the AND circuit A2 is input to the D terminal of the latch circuit L2. The operation mode selection terminal T3 and the test mode transition enable terminal MD0 are input to the AND circuit A3, and the output of the AND circuit A3 is input to the D terminal of the latch circuit L3. The reset terminal RESN and the power-on reset release signal are input to the AND circuit A13, and the output of the AND circuit A13 is input to the G terminals of the latch circuits L1 to L3, so that the reset signal is inactive (reset release) and power The latch circuits L1 to L3 latch the signal input to the D terminal at the timing when the on-reset release signal becomes active (power-on reset release).
The Q terminal of the latch circuit L1 is connected to the inverter I1, and the output of the inverter I1 is input to the AND circuit A8. The output of the test mode transition enable terminal MD0 is input to the AND circuit A8.

[Main operations]
Next, the main operation of the microcomputer 2 when the writer 5 is connected to the ECU 1 and data is written from the writer 5 to the flash ROM 26 will be described.
As shown in FIG. 4, the test mode transition enable signal appearing at the test mode transition enable terminal MD0 changes to the L level when the user mode is set, and the rewrite mode or the test mode other than the user mode is changed. Sometimes it changes to H level. In the rewrite mode, the operation mode selection terminal T1 changes to the L level, and the operation mode is selected regardless of the operation mode selection terminals T2 and T3. In FIG. 4, * indicates don't care.
When each terminal provided in the writer 5 is connected to the terminal board 1a of the ECU 1 and the ECU 1 power is turned on, 5V power is supplied to the microcomputer 2, the power-on reset generation circuit 21 outputs a reset signal, and the microcomputer 2 is powered. The on-reset is released. Further, the reset signal (L) output from the writer 5 is input to the mode determination circuit 22 via the reset terminal RESN, and the reset state is entered.

Here, when the reset signal becomes inactive (reset release), the signal input to the D terminal of the latch circuit L1 is latched. At this time, the L-level operation mode selection signal input to the operation mode selection terminal T1 and the H-level enable signal input to the test mode transition enable terminal MD0 are input to the AND circuit A1 of the mode determination circuit 22, respectively. Since the output of the AND circuit A1 is at L level, the L level is latched by the latch circuit L1. The L level output of the latch circuit L1 is inverted by the inverter I1 to become the H level and is input to the AND circuit A8. Since the AND circuit A8 receives the H level test mode transition enable signal, the output of the AND circuit A8 becomes H level (= 1), and the operation mode is determined to be the rewrite mode (FIG. 4). Then, when the writer 5 transmits a flash rewrite command for instructing rewriting of data stored in the flash ROM 26 and serial data to the microcomputer 2 via the serial data input terminal SIN, the serial communication circuit 24 of the microcomputer 2 Serial data is received, and the flash rewrite control circuit 25 writes the received data into the flash ROM 26.
As shown in FIG. 3, the test mode transition enable terminal MD0 is connected to the inverter I2, and whether or not the user mode is selected is determined only by the output level of the inverter I2. That is, when the test mode transition enable signal is at the L level (inactive) (in a mode other than the rewrite mode and the test mode), all are in the user mode (FIG. 4).

[Effect of the embodiment]
(1) As described above, when the ECU 1 is used, the mode determination circuit 22 is configured so that each of the operation mode selection terminal T1 and the test mode transition enable terminal MD0 latched by the latch circuit L1 when the reset signal becomes active. When the levels are L and H, respectively, the operation mode is determined as the rewrite mode. For this reason, even if noise is superimposed on the operation mode selection terminal T1 after changing to the data rewriting mode, there is no possibility of switching to another mode.
(2) Further, after the operation mode is determined, the operation mode selection terminals T1 to T3 are not affected by the state of the operation mode. Other functions can be assigned.

(3) Furthermore, the rewrite mode is determined only when the test mode transition enable signal output from the test mode transition enable terminal MD0 is active. When the test mode transition enable signal is inactive, the operation mode is fixed to the user mode. can do. For this reason, even if an inadvertent operation mode switching occurs, if the test mode transition enable terminal is pulled down, the user mode is restored, so that the fail-safe is improved.
(4) Since the input lines 2a and 3a, the data communication lines 2b and 3b, the data communication lines 2c and 3c, and the data communication lines 2d and 3d are shared, the number of lines is reduced as compared with the configuration that is not shared. Therefore, the ECU 1 can be downsized.
(5) Since the chip select terminal CS has a polarity opposite to that of the operation mode selection terminal T1 when in the data rewrite mode, the EEPROM 3 becomes high impedance when data is written to the flash ROM 26. Therefore, there is no possibility that data is written in the EEPROM 3 by mistake.

[Other Embodiments]
(1) In the above embodiment, when the reset signal becomes inactive, the rewrite mode is determined on condition that the operation mode selection terminal T1 is L and the test mode transition enable terminal MD0 is H. When the reset signal becomes inactive, the combination of two or three output levels of the operation mode selection terminals T1 to T3 is a predetermined combination, and the output level of the test mode transition enable terminal MD0 is H It is also possible to determine the rewrite mode on the condition. The output level of the terminal for determining the operation mode is not limited to the above combination, and can be changed.
(2) In the above embodiment, the ECU is described as an example of the electronic control device according to the present invention. However, data is written by connecting an electronic control device other than the ECU equipped with the microcomputer or a direct writer. The present invention can be applied to various types of microcomputers.

It is explanatory drawing which shows the outline of the state with which the electronic control apparatus and writer which concern on embodiment of this invention were connected. It is explanatory drawing which shows the main structures of the microcomputer provided in the electronic control apparatus shown in FIG. FIG. 3 is a circuit diagram of a mode determination circuit provided in the microcomputer shown in FIG. 2. 4 is a mode chart showing a correspondence relationship between signal levels of respective terminals and modes in the mode determination circuit shown in FIG. 3. It is a conceptual diagram at the time of connecting the conventional microcomputer and a writer.

Explanation of symbols

  1 .. ECU (Electronic Control Unit), 2... Microcomputer, 2 a, 3 a... Input line, 2 b, 2 c, 3 b, 3 c... Data communication line 3. ..Writer (data writing device), 22..mode decision circuit (mode decision means), 26..flash ROM (first storage medium), CS..chip select terminal, ESIN..serial data input terminal (data communication) Terminal), ESOUT... Serial data output terminal (data communication terminal), MD0... Test mode transition enable terminal (enable terminal), RESN.

Claims (4)

In an electronic control device to which a data writing device can be connected,
A reset terminal for inputting a reset signal from the data writing device;
An operation mode selection terminal for inputting an operation mode selection signal for determining a predetermined mode from a plurality of operation modes including a data rewrite mode from the data writing device;
An enable terminal for inputting a permission signal for permitting mode switching from the data writing device;
A data communication terminal for communicating data with the data writing device;
A first storage medium for storing data input from the data communication terminal;
The level of the signal appearing at each of the reset terminal, the operation mode selection terminal, and the enable terminal is monitored, and when the reset signal input from the reset terminal reaches a level indicating reset release, the permission signal appearing at the enable terminal An operation mode determination means for latching the level and the level of the operation mode selection signal appearing at the operation mode selection terminal, and determining the operation mode based on the level of each latched signal;
The operation mode determination means stores the data output from the data writing device when the operation mode is determined as the data rewrite mode, in the first storage medium via the data communication terminal. Electronic control device.   2. The electronic control according to claim 1, wherein the operation mode selection terminal can be used as a terminal other than the operation mode selection terminal after the determination of the operation mode by the operation mode determination unit is completed. apparatus. A second storage medium for storing data;
An input line connected to a chip select terminal provided in the second storage medium is connected to an input line connected to the operation mode selection terminal;
The said chip select terminal is set so that it may become a polarity opposite to the polarity of the said operation mode selection terminal when it is in the said data rewriting mode. Electronic control device.   The electronic control device according to claim 3, wherein a data communication line connected to a data communication terminal of the second storage medium is connected to a data communication line connected to the data communication terminal.

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