JP2008102094A - Voltage monitoring method and its device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately monitor the deviation of many various voltages to be monitored from an upper limit and a lower limit with simple circuitry and with a small space. <P>SOLUTION: This voltage monitoring device comprises a first comparator circuit for detecting a state where a comparative voltage proportional to the voltage to be monitored is higher than a first threshold voltage and outputting a logic-1 level, a second comparator circuit for detecting a state where the comparative voltage is higher than a second threshold voltage higher than the first threshold voltage and outputting the logic-1 level, an inverter circuit for inverting the output of the second comparator circuit, and an AND-circuit for obtaining AND of the outputs of the first comparator circuit and the inverter circuit. The voltage monitoring device detects whether the comparative voltage deviates from the range surrounded by the first and second threshold voltages based on the output of the AND-circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a voltage monitoring method and apparatus, and more particularly, to a voltage monitoring method and apparatus for monitoring whether or not a monitoring target voltage is within a predetermined range.

  In recent years, for example, in a package board (PCB) constituting a base station device of a mobile communication system, not only the lower limit of the power supply voltage but also the upper limit voltage monitoring (voltage range monitoring) as the mounting device voltage decreases. is needed. In addition, with the diversification of mounted devices, since various types of power supply voltages are used, the scale of the power supply monitoring circuit is increasing.

As an example of this type of conventional voltage monitoring apparatus, a power supply monitoring apparatus that monitors deviations from the upper limit and the lower limit of the monitored voltage by a circuit combining discrete devices such as resistors, transistors, and comparators is known. (Patent Document 1).
Special table 2003-501717

  However, the conventional monitoring circuit is composed of individual elements such as a resistor, a comparator circuit, a logic circuit, and the like, and a combination of a comparator circuit that detects the upper limit of the voltage to be monitored and a comparator circuit that detects the lower limit. In this method, deviation from the upper limit and lower limit is detected, so that not only the circuit configuration becomes complicated, but also the size and number of elements to be monitored increase as the type and number of voltages to be monitored increase. There was a problem.

  The present invention has been made in view of the above-mentioned problems of the prior art, and the object of the present invention is to monitor the deviation from the upper limit and the lower limit for a large number of monitored voltages with a simple circuit configuration and a small space. An object of the present invention is to provide a voltage monitoring method and apparatus capable of performing with accuracy.

  A voltage monitoring apparatus according to a first aspect of the present invention includes a first comparator circuit that detects a state in which a comparison voltage proportional to a monitoring target voltage is higher than a first threshold voltage and outputs a logic 1 level, and the comparison A second comparator circuit for detecting a state where the voltage is higher than the second threshold voltage higher than the first threshold voltage and outputting a logic 1 level; and an inverter circuit for inverting the output of the second comparator circuit; A logical product circuit that takes a logical product of the outputs of the first comparator circuit and the inverter circuit, and based on the output of the logical product circuit, the comparison voltage is sandwiched between the first and second threshold voltages. This is to detect whether or not the vehicle has deviated.

  In the present invention, since both the first and second comparator circuits detect a state in which the upper limit threshold is exceeded, most of the circuits can be shared and simplified. In addition, a configuration that takes the logical product of the output of the first comparator circuit and the inverted output of the second comparator circuit enables efficient and accurate monitoring of deviations from the upper and lower limits of the monitored voltage with a simple logical configuration. It becomes possible. The logic 1 level may be a high level or a low level.

An IC chip according to a second aspect of the present invention includes a first comparator circuit that detects a state in which a comparison voltage proportional to a monitoring target voltage is higher than a first threshold voltage and outputs a logic 1 level, and the comparison A second comparator circuit for detecting a state where the voltage is higher than the second threshold voltage higher than the first threshold voltage and outputting a logic 1 level; and an inverter circuit for inverting the output of the second comparator circuit; A plurality of voltage monitoring units comprising a logical product circuit that takes a logical product of the outputs of the first comparator circuit and the inverter circuit, and the first and second threshold voltages applied to the plurality of voltage monitoring units, respectively. It is configured to be programmable.

  Therefore, various types and a large number of voltages can be monitored efficiently with a small space. In addition, since the upper limit and lower limit voltage can be monitored at substantially one location, there is no voltage variation caused by drawing the monitoring target voltage or the comparison voltage, and the monitoring can be performed with high accuracy.

  In addition, the voltage monitoring method according to the third aspect of the present invention includes a comparison result between the comparison voltage proportional to the monitoring target voltage and the first threshold voltage, and an inverted output of the comparison result between the higher second threshold voltage and the comparison result. By taking the logical product of these, it is detected whether or not the comparison voltage has deviated from the range sandwiched between the first and second threshold voltages. Therefore, deviation from the upper limit and the lower limit of the monitoring target voltage can be efficiently monitored by a simple method.

  As described above, according to the present invention, it is possible to monitor deviations from the upper and lower limits of various and many monitored voltages with high accuracy with a simple circuit configuration and a small space. The place that contributes to improvement is extremely large.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings.

  FIG. 1 is a block diagram of a power supply monitoring apparatus according to an embodiment, and shows a case where this apparatus is configured by a PLD (Programmable Logic Device). In the figure, 10 is an analog block on which a plurality of comparator circuits and the like are mounted, 11 is a programmable attenuator (PLATT) capable of programming an input voltage attenuation ratio, and 12 is a programmable standard capable of programming (generating / selecting) various reference voltages Vr. Voltage generator (PLREF), CMP is a comparator circuit having the same circuit configuration for monitoring deviations from lower limit voltages such as comparison voltages Vm1, Vm2, etc., 20 is a logic block in which a plurality of logic circuits are mounted, and A is An AND gate circuit, I is an inverter circuit.

  A preferred aspect of the present embodiment is, for example, a commercially available PLD chip for power supply monitoring (for example, “ispPAC-POWR1208P1” manufactured by Lattice) except for a part of the analog block 10 (PLATT11, PLREF12) in advance. As shown in FIG. 1, a power supply monitoring IC chip capable of monitoring deviations from the upper limit voltage and the lower limit voltage with respect to the monitoring target voltages V1, V2, etc. with high accuracy by circuit synthesis (programming) as shown in FIG. . In this case, the PLATT11 and PLREF12 portions can be programmed by the user.

  The analog block 10 includes a plurality of input ports IP1 to IPn for inputting various and many monitoring target voltages V1, V2, and the like. Here, a plurality of DC power supply devices used in an electronic device (system) are provided. An output voltage (not shown) is connected. The programmable attenuator (PLATT) 11 is an attenuator circuit for enabling monitoring of a wide range of monitoring target voltages (for example, 0.6 V to 6 V, etc.). For example, a plurality of resistors are provided between the input port IP1 and GND. A voltage dividing circuit in which R is connected in series is provided, and a voltage Vm1 of an arbitrary tap can be selected by a program and connected to each + input terminal of the comparator circuits CMP1 and CMP2.

The programmable reference voltage generator (PLREF) 12 internally generates a plurality of types of reference voltages Vr that increase at a pitch of, for example, 0.004 V, and an arbitrary reference voltage (corresponding to the threshold voltage of the present invention) by a program. Vr1, Vr2, etc. are selected and can be connected to the respective -input terminals of the comparator circuits CMP1,2. Thereby, the upper limit voltage and the lower limit voltage for the monitoring target voltage V can be arbitrarily programmed (set). On the other hand, the logic block 20 includes, for example, comparator circuits CMP1 and 2, and an AND gate circuit A1 and an inverter circuit I1 are connected as shown in the figure to constitute a voltage monitoring unit that is a basic unit for voltage monitoring (programming). )is doing. Next, the operation of the voltage monitoring unit will be specifically described.

  Although the comparison voltage Vm1 in FIG. 1 is taken out through a resistance voltage dividing circuit, it is assumed here that the resistance voltage dividing circuit is not used for the sake of simplicity. Now, assuming that the comparison voltage Vm1 (= monitoring target voltage V1) is at the rated voltage 1.25V, and assuming that the lower limit voltage Vr2 = 1.2V and the upper limit voltage Vr1 = 1.3V, the comparator circuit CMP2 satisfies Vm1> Vr2. A logic 1 (high) level is output upon detection. On the other hand, the comparator circuit CMP1 outputs a logic 0 (low) level by detecting Vm1 <Vr1, but the inverter circuit I1 connected to the output outputs a logic 1 level. As a result, the AND gate circuit A1 is satisfied, and a logic 1 level (normal) is output to the monitoring output port OP1.

  However, if the comparison voltage Vm1 falls below the lower limit voltage Vr2 for some reason after that, the output of the comparator circuit CMP2 becomes a logic 0 level, and accordingly, the output of the AND gate circuit A1 also becomes a logic 0 level (abnormal). Or, conversely, when the comparison voltage Vm1 exceeds the upper limit voltage Vr1, the output of the comparator circuit CMP1 becomes a logic 1 level, and accordingly, the output of the inverter circuit I1 becomes a logic 0 level. As a result, the output of the AND gate circuit A1 also becomes a logic 0 level (abnormal). In this way, deviation from the upper limit and lower limit of the monitoring target voltage V1 can be monitored with high accuracy. The same applies to the monitoring target voltage V2. Since various types and a large number of power supply monitoring are performed in this IC chip, the circuit scale on the PCB does not change even if the voltage to be monitored increases. Further, since the monitoring locations are the same, there is no variation due to the routing of the monitoring target voltage. More specifically, since only a pattern error between pins is generated, monitoring can be performed under the same upper limit voltage and lower limit voltage environment.

  Further, the AND gate circuit A8 takes the logical product of the detection outputs of a plurality of voltage monitoring units, and therefore any one voltage to be monitored becomes abnormal (out of range) at the monitoring output port OP8. The logic level becomes 0 (abnormal), and thus, a large number of power supply voltages can be monitored efficiently.

  FIG. 2 is an operation timing chart of the power supply monitoring apparatus according to the embodiment, and shows a case where the deviation from the upper limit 1.3V and the lower limit 1.2V is monitored for the monitoring target voltage V1 = Vm1 (for example, rated voltage 1.25V). ing. The PLREF 12 outputs Vr1 = 1.3V and Vr2 = 1.2V. When the system is turned on, the comparison voltage increases towards the rated voltage of 1.25V. In this section, the output of the comparator circuit CMP1 becomes a logic 0 level due to Vm1 <Vr1, and accordingly, the output of the inverter circuit I1 becomes a logic 1 level. On the other hand, the output of the comparator circuit CMP2 is also at the logic 0 level due to Vm1 <Vr2, so that the output of the AND gate circuit A1 is at the logic 0 level (abnormal). Since the detection of an abnormality at the beginning of power-on is masked by a circuit (not shown), the system does not recognize the abnormality.

  Thus, when Vm1 eventually exceeds the lower limit voltage Vr2, there is no change in the comparator circuit CMP1, but the output of the comparator circuit CMP2 is inverted to the logic 1 level by Vm1> Vr2, thereby the output of the AND gate circuit A1. Becomes a logic 1 level (normal).

Thereafter, when the comparison voltage Vm1 exceeds the upper limit voltage Vr1 for some reason, the comparator circuit CMP2 does not change, but the output of the comparator circuit CMP1 is inverted to the logic 1 level by Vm1> Vr1, and accordingly, the inverter circuit The output of I1 becomes a logic 0 level, whereby the output of the AND gate circuit A1 detects a logic 0 level (abnormal). Conversely, the same applies to the case where the comparison voltage Vm1 is lower than the lower limit voltage Vr2. In this way, the voltage can be monitored properly after the power is turned on.

  In the above embodiment, the case where the power supply voltage is directly monitored by the power supply monitoring device of the present invention has been described, but the present invention is not limited to this. For example, the current to be monitored may be converted into a voltage by a resistor, and this voltage may be monitored.

  In the above embodiment, the AND gate circuit A1 and the inverter circuit I1 are combined. However, the present invention is not limited to this. Another combination is shown in the inset (a) of FIG. In this example, the AND gate circuit A1 itself has an inverting input terminal and operates in the same manner as described above.

  Further, although the preferred embodiment of the present invention has been described, it goes without saying that various changes in the configuration, control, processing, and combination of each part can be made without departing from the spirit of the present invention.

It is a block diagram of the power supply monitoring apparatus by embodiment. It is an operation | movement timing chart of the power supply monitoring apparatus by embodiment.

Explanation of symbols

10 Analog Block 11 Programmable Attenuator (PLATT)
12 Programmable reference voltage generator (PLREF)
20 logic block A AND gate circuit CMP comparator circuit I inverter circuit

Claims (3)

A first comparator circuit for detecting a state in which a comparison voltage proportional to the monitored voltage is higher than a first threshold voltage and outputting a logic 1 level;
A second comparator circuit for detecting a state in which the comparison voltage is higher than a second threshold voltage higher than the first threshold voltage and outputting a logic one level;
An inverter circuit for inverting the output of the second comparator circuit;
An AND circuit that takes an AND of the output of the first comparator circuit and the inverter circuit,
A voltage monitoring device that detects whether or not the comparison voltage has deviated from a range between the first and second threshold voltages based on the output of the AND circuit. A first comparator circuit for detecting a state in which a comparison voltage proportional to the monitored voltage is higher than a first threshold voltage and outputting a logic 1 level;
A second comparator circuit for detecting a state in which the comparison voltage is higher than a second threshold voltage higher than the first threshold voltage and outputting a logic one level;
An inverter circuit for inverting the output of the second comparator circuit;
A plurality of voltage monitoring units comprising a logical product circuit that takes a logical product of the outputs of the first comparator circuit and the inverter circuit;
An IC chip, wherein the first and second threshold voltages applied to the plurality of voltage monitoring units are programmable. By taking a logical product of the comparison result of the comparison voltage proportional to the monitoring target voltage with the first threshold voltage and the inverted output of the comparison result with the second threshold voltage higher than this, the comparison voltage becomes the first threshold voltage. 1. A voltage monitoring method comprising detecting whether or not a range between the first and second threshold voltages is deviated.

Images