JP2007189550A - Radio communication processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve radio communication throughput by eliminating an overhead about data transfer in a radio communication processor while suppressing power consumption by suppressing a processing load of a device side main CPU. <P>SOLUTION: In the radio communication processor 1, when transferring an Ethernet (R) packet to a memory 13, a DMA (direct memory access) controller 12 notifies a local CPU 14 of a transfer end to make the local CPU 14 prepare a radio header and controls data of the Ethernet (R) packet transferred to the memory 13 and the radio header prepared by the local CPU 14 so as to be inputted to an FIFO 16 when the transfer of the header of the Ethernet (R) packet ends. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wireless communication processing device, and more particularly to increasing the transmission speed of wireless communication.

With the development of communication technology in recent years, wireless communication technology has been further improved, and not only conventional computer networks but also various applications such as home appliances and mobile devices have been made wireless. At the same time, higher communication speeds for wireless communication are required, and the communication speeds of products that have already been commercialized and are on the market are increasing.
Usually, as a method of data transfer from the host-side CPU to the wireless network in wireless communication, after the DMA transfer from the host-side CPU to the memory in the wireless communication processing device, the wireless communication processing device modulates the communication data. And send it as radio waves. At this time, the DMA transfer time for each packet becomes an overhead, and the throughput value of the system is lowered, which hinders further improvement in communication speed.
In order to solve this problem, as a conventional technique, for example, as described in Patent Document 1, the difference between the DMA transfer rate from the host CPU to the memory in the wireless communication processing device and the network transfer rate is calculated. Based on this, data transfer to the network can be started from the point in time when the data transfer from the CPU on the host side is completed for an amount of time during which no underrun occurs. Since the data transfer to the network can be started before the DMA transfer for one packet is completed, the overhead can be further reduced.
However, the above method does not eliminate the overhead. This is because the underrun prevention time is an overhead.

In general, in the case of wireless communication, for example, in the case of an IEEE 802.11 wireless LAN that has recently become widespread, in order to perform wireless signal synchronization and frequency offset correction for each packet in addition to data transfer, a preamble signal is required, and wireless-specific CSMA A transmission interval between packets is defined for a collision prevention measure called / CA (Carrier Sense Multiple Access with Collision Avoidance). Therefore, the effective throughput of the wireless network is about half compared to the transmission speed of wireless communication. Therefore, when the DMA transfer rate from the CPU on the host side is compared with the wireless network communication rate, the DMA transfer rate is faster. For example, the DMA transfer rate is faster than the DMA transfer rate of the PCI I / F operating with a 33 MHz clock. Therefore, the effect of using the conventional underrun prevention measure is small.
To eliminate the overhead due to the DMA transfer time for each packet, double the capacity so that data for two packets can be stored in the memory area, and the host side during radio wave transmission by the modulation processing of the previous packet Generally, a double buffer structure is employed so that the next packet can be DMA-transferred from the CPU. With the double buffer structure, overhead can be eliminated except for the time for DMA transfer of the first packet.

By the way, when data is transferred using a normal network, information such as a header needs to be added before and after the transfer data, and the format differs depending on the type of network used. Also in the case of a wireless network, it is necessary to convert the format from the upper network to the wireless network. For this reason, even when the double buffer structure is used, it is necessary for the CPU to perform the header format conversion processing to the wireless network format, and it is necessary to DMA transfer the packet data after the format conversion.
However, unlike a high-performance device such as a personal computer, the CPU cannot expect performance, and the CPU capability is used preferentially for the original function of the device. As a result, it is difficult to occupy CPU processing for communication. For example, in home appliances, processing required for a wireless network such as format conversion processing as described above is not performed by the CPU on the device side, but by wireless communication. It is better to have a configuration in which a local CPU is built in the processing device and processing for wireless communication is performed on the local CPU side.
In this case, the previously transferred data is DMA-transferred from the main CPU on the device side to the memory in the wireless communication processing device during wireless transmission in the physical layer, and after that, the local CPU performs format conversion processing. It will be.
Japanese Patent No. 3127523

However, there is no problem if the DMA transfer and the format conversion process are completed before the wireless transmission of the previous packet in the physical layer is completed. However, wireless communication is originally used in a mobile environment, and power consumption has recently been increased in household appliances. Considering that the reduction of power consumption is an issue, it is necessary to reduce the power consumption of the wireless communication processing device as much as possible. For this reason, the operating frequency of the local CPU in the wireless communication processing apparatus must be lowered. As a result, the time for the format conversion process becomes longer, the next DMA transfer and the format conversion process cannot be completed before the data transfer during the previous transfer is completed, and a time lag occurs between the data transfers. This has the disadvantage of reducing the system throughput due to overhead.
In order to solve such a problem, an object of the present invention is to provide a wireless communication apparatus capable of improving the wireless communication processing capability without the overhead associated with data transfer.

In order to achieve the above object, the invention of claim 1 is a wireless communication system that connects to an external device via a connection interface, converts communication packet data from the external device into a radio wave, and transmits the radio wave. A communication processing apparatus, a first memory for storing a communication packet having a header, transfer control means for directly accessing the first memory to control data transfer, and the transfer control means Wireless header generation means for generating a wireless header based on a header of a communication packet stored in the memory, a second memory for storing the wireless header and the communication packet, and the second based on a wireless communication standard Wireless communication packet generation means for generating a wireless communication packet from data in the memory, and the transfer control means includes a communication packet in the first memory. When the transfer of the header of the communication packet is completed, the wireless header generation unit is notified of the transfer completion and the wireless header generation unit creates the wireless header, and the first header is generated. Control is performed so that the data of the communication packet transferred to the memory and the wireless header created by the wireless header generation means are input to the second memory.
According to a second aspect of the present invention, in the wireless communication processing device according to the first aspect, the transfer control unit is configured to generate the wireless header by the wireless header generation unit, and to transmit data following the header of the communication packet. Control is performed so that data is stored in one memory at the same time.

According to the present invention, the transfer control means notifies the wireless header generation means of the transfer completion when the transfer of the header of the communication packet is completed when transferring the communication packet to the first memory, and the wireless header generation means The wireless communication processing speed is generated by controlling the communication packet transferred to the first memory and the wireless header generated by the wireless header generation means to be input to the second memory. Can be improved.
In addition, according to the present invention, since the wireless header creation process is performed by the wireless header generation means, the load of wireless communication processing in the CPU of the external device can be reduced, so that the original performance can be reduced in the external device. It will be able to be demonstrated.

Hereinafter, embodiments of the wireless communication processing device of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a functional configuration of the wireless communication processing apparatus according to the present embodiment.
The wireless communication processing device 1 shown in FIG. 1 includes a connection interface 11, a DMA controller 12, a memory 13, a local CPU 14, a wireless communication controller 15, and a FIFO (First In First Out) 16. The connection interface 11, the DMA controller 12, the memory 13, the local CPU 14, the wireless communication controller 15, and the FIFO 16 constituting the wireless communication processing device 1 are formed on the same chip.
The connection interface 11 is configured by a PCI bus, for example, and is connected to the main CPU 50 of an external device such as a host computer. The connection interface 11 is not limited to the PCI bus, but may be USB, PCMCIA, or the like.
The DMA controller (transfer control means) 12 controls DMA transfer. Here, DMA (Direct Memory Access) is a method of data transfer in a computer system, and refers to a method of directly transferring data between each device and memory without using a CPU.
The memory 13 temporarily stores data transferred under the control of the DMA controller 12.
The local CPU 14 (wireless header generation means) is used for wireless communication, which will be described later, based on the Ethernet® net header of the Ethernet® packet (communication packet) stored in the memory 13 under the control of the DMA controller 12. Generate a radio header.
The wireless communication controller (wireless communication packet generation means) 15 performs transmission / reception signal modulation / demodulation processing and the like, and generates a wireless communication packet from data in the memory 13 based on the wireless communication standard.
The FIFO (second memory) 16 receives the communication packet transferred to the memory 13 and the wireless header generated by the local CPU 14.

FIG. 2 is a schematic diagram showing a frame configuration used in Ethernet (registered trademark) and a wireless LAN.
The wireless communication packet shown in FIG. 2 includes a wireless header, an Ethernet (registered trademark) packet, and an FCS (Flame Check Sequence) used for checking data consistency.
The wireless header is control information required at the time of transmission, and is added to the head of the packet.
The Ethernet (registered trademark) packet is composed of an Ethernet (registered trademark) header followed by a communication data portion of a maximum of 1.5 Kbytes. Here, the communication data part includes FCS. The Ethernet (registered trademark) header is composed of a 6-byte destination address field, followed by a 6-byte source address field, followed by a 2-byte frame length field.

Hereinafter, processing in the wireless communication processing apparatus of the present embodiment will be described with reference to FIG.
The DMA controller 12 DMA-transfers Ethernet (registered trademark) packets, which are communication packets transferred from the main CPU 101 via the connection interface, to the memory 13. At this time, if the Ethernet (registered trademark) header of the Ethernet (registered trademark) packet is transferred to the memory 13 at time t1 shown in FIG. 3, the DMA controller 12 completes the DMA transfer of the Ethernet (registered trademark) header to the local CPU 14. When the communication data following the Ethernet (registered trademark) header is transferred to the memory 13, the local CPU 14 creates a wireless header based on the information of the Ethernet (registered trademark) header. Start.
Then, the DMA controller 12 notifies the local CPU 14 at the time t2 when the FIFO 16 in the wireless communication controller 15 has free space for the wireless communication packet, DMA-transfers the MAC packet to the FIFO 16, and Ethernet (registration) of the memory 13 (Trademark) packet is transferred to the FIFO 16.
At this time, the transfer destination address of the DMA transfer by the DMA controller 12 is transferred to the memory 13 including the offset of the radio header, and after the radio header is created by the local CPU 14, it is written to the FIFO 16 by DMA transfer from the head address. Yes. Thereafter, the wireless communication controller 106 creates and transmits transmission wireless data based on these.

In this way, when the Ethernet header of the Ethernet packet is DMA-transferred to the memory 13, the local CPU 14 starts creating a wireless header. The wireless communication processing speed can be improved as compared with the case where a wireless header is created after waiting for DMA transfer of the entire registered trademark packet. In this embodiment, the creation of the wireless header in the local CPU 14 is described as starting when the Ethernet (registered trademark) header is DMA-transferred. However, the entire Ethernet (registered trademark) packet is DMA-transferred to the memory 13. If the creation of the wireless header in the local CPU 14 is started before the communication is started, the wireless communication processing speed can be improved as compared with the conventional case.
Further, in the present embodiment, since the local CPU 14 performs wireless header creation processing and the like, the load due to wireless communication processing in the main CPU 50 of the external device is reduced, and the original performance can be exhibited. There is also.
The transfer destination memory address of the DMA transfer to the memory 13 is transferred to the memory 13 including the offset of the radio header, and when the local CPU 14 finishes the creation of the radio header, the DMA transfer is performed from the head address including the created radio header by the DMA transfer. Write to the FIFO 16.
In this embodiment, the IEEE 802.11 wireless LAN is used as the wireless network and Ethernet (registered trademark) is used as the upper network. However, the wireless communication and the upper layer protocol are not limited to these, and A device to which the present invention can be applied may be a home appliance or the like.

The block diagram which shows the function structure of the radio | wireless communication processing apparatus which concerns on this embodiment. The schematic diagram which showed the flame | frame structure used by Ethernet (trademark) and wireless LAN. The figure which shows the process in the wireless communication processing apparatus of this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wireless communication processing apparatus, 11 Connection interface, 12 DMA controller, 13 Memory, 14 Local CPU, 15 Wireless communication controller, 16 FIFO, 50 Main CPU

Claims (2)

A wireless communication processing device for performing wireless communication by connecting to an external device via a connection interface, converting communication packet data from the external device into a wireless radio wave, and transmitting the wireless packet.
A first memory for storing a communication packet having a header;
Transfer control means for directly accessing the first memory and performing data transfer control;
Wireless header generation means for generating a wireless header based on a header of a communication packet stored in the first memory by the transfer control means;
A second memory for storing the wireless header and the communication packet;
Wireless communication packet generation means for generating a wireless communication packet from data in the second memory based on a wireless communication standard,
The transfer control means, when transferring the communication packet to the first memory, notifies the wireless header generation means of the transfer completion when the transfer of the header of the communication packet is completed, and the wireless header generation means And generating the wireless header and controlling the data of the communication packet transferred to the first memory and the wireless header generated by the wireless header generating means to be input to the second memory. A wireless communication processing device. The wireless communication processing device according to claim 1,
The transfer control unit performs control so that the wireless header generation processing by the wireless header generation unit and data following the header of the communication packet are stored in the first memory at the same time. Wireless communication processing device.

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