JP3753622B2 - Packet transceiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a packet transmission / reception apparatus in packet communication such as Ethernet, and more particularly to a packet transmission / reception apparatus that dynamically controls packet transmission start timing.
[0002]
[Prior art]
Communication methods such as Ethernet (registered trademark), IEEE1394, and USB communicate by transmitting and receiving data in units of packets. Ethernet is defined in the IEEE802.3 standard, and is a CSMA / CD network standard. IEEE1394 is a communication method defined by the IEEE1394 standard as the name suggests. USB is a communication method planned by the USB consortium.
[0003]
In these communication systems, variable-length packets are used. Data packets that usually have a buffer such as FIFO on a control device implemented with an application specific integrated circuit (ASIC), etc., determine the type and length of the received packet, and should be processed by the local station The data is transferred to the packet area on the main memory by DMA and processed, and conversely, the transmission is performed while transferring data from the packet area on the main memory by DMA.
[0004]
[Problems to be solved by the invention]
By the way, a problem in packet transmission is the problem of the difference between the external speed and the DMA speed. Considering the case where DMA is delayed due to the execution of other DMAs, etc., transmission starts when a sufficient amount of data enters the FIFO buffer (this is a fixed threshold for starting transmission as a practically sufficient amount). It was the usual way).
[0005]
As a result, a transmission underrun state in which DMA cannot keep up with the transmission speed is avoided. However, the packet size varies greatly from 64 bytes to 1518 bytes in the case of Ethernet (registered trademark). If a sufficient packet capacity is secured as a threshold in consideration of rare cases when the packet length is large, whether the amount of data that has entered the FIFO buffer in all packets, including short packets, exceeds the threshold, in the following cases the size of packet threshold will start transmitting when either detecting the end of packet. This means that the start of transmission is always delayed until an input corresponding to the threshold value is received, and this delay in the start of transmission is a problem.
[0006]
An object of the present invention is to solve the above-mentioned problems, to reduce a delay in transmission start due to a transmission start threshold on a FIFO buffer at the time of transmission, and to eliminate transmission overhead.
[0007]
[Means for Solving the Problems]
According to the present invention, the object is to take a part of a packet into a buffer, interpret the protocol, and when the packet is a packet to be processed by a local station from another device, the packet is stored in a packet area on an internal main memory. A packet transmission / reception device that transmits a packet from a packet area on a main memory in the device, wherein a packet data threshold value and a transmission start threshold value corresponding to the packet data threshold value are set in advance. A plurality of prepared tables and a transmission start threshold value corresponding to the minimum packet data threshold value to which the transmission packet length of a packet transmitted for each descriptor applies are selected from the table as a transmission start device. This is achieved by providing the setting means .
[0008]
Further, the object is achieved by starting packet transmission when data corresponding to the number of bytes satisfying the set transmission start value is input to the buffer after the transmission start value is set .
[0010]
The object is achieved by providing means for registering the table.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
In the following, an embodiment of the present invention will be described by taking as an example a packet transmission / reception apparatus adapted to Ethernet based on the IEEE 802.3 standard.
[0012]
FIG. 1 shows a configuration example of a packet transmission / reception system, which includes a program ROM 1, a main memory 2, a CPU 3, a network adapter 4, and a system bus 5. In this configuration example, a network adapter 4 implemented by an ASIC (Application Specific Integrated Circuit) or the like corresponds to the packet transmitting / receiving apparatus according to the embodiment of the present invention.
[0013]
The packet transmission / reception system performs transmission / reception using the function of the network adapter 4 when the program ROM 1 is activated. Packet transmission / reception is performed by DMA to the main memory 2. A packet buffer for managing a packet area to be DMA on the main memory 2 is also placed on the main memory 2, and the network adapter card reads the contents by DMA and writes back the management information.
[0014]
FIG. 2 shows the configuration of a packet transmitting / receiving apparatus (network adapter), which includes a host interface 13, FIFO RAMs 14 and 17, a transmission FIFO buffer 15, a reception FIFO buffer 16, a network management unit 18, a transmission control unit 19, an Ethernet controller 20, and a reception. A control unit 21, a clock 22, an encoder 23, a decoder 24, an AUI 25, and a twisted pair transceiver 26 are provided, and an EEPROM 11 and a boot PROM 12 are connected to the host interface 13.
[0015]
The data received by the twisted pair transceiver 26 and decoded by the decoder 24 including processing such as preamble removal, CRC check, pad removal, etc. is received by the reception controller 21 and the Ethernet (registered trademark) controller 20 according to IEEE 802.3. The prescribed reception control is performed. The Ethernet (registered trademark) controller 20 receives a data packet determined as a packet to be received by the packet transmitting / receiving apparatus, and the received data packet is copied to the reception FIFO buffer 16. The copied content is DMA-transferred by the function of the host interface 13 and DMA-transferred to the main memory 2 via the system bus 5.
[0016]
Transmission is performed by DMA by the function of the host interface 13, and packet data on the main memory 2 is DMA-transferred via the system bus 5 and sent to the transmission FIFO buffer 15. Data on the transmission FIFO buffer 15 is subjected to transmission control defined by IEEE 802.3, and after processing such as preamble addition, CRC generation, pad data generation, and the like by the encoder 23, the twisted pair transceiver 26 transmits data to the network. Sent to.
[0017]
FIG. 3 shows the configuration of the packet buffer. FIG. 4 shows the structure of a descriptor that is a component of the packet buffer.
[0018]
As shown in FIG. 3, the packet buffer is an area on the main memory for managing a packet area that is a DMA target. The embodiment of the present invention has one input packet buffer for transmission, two input packet buffers for reception, and one result holding packet buffer. The reception packet buffer manages packet areas having different lengths. The packet buffer is composed of a plurality of descriptors. The descriptor has a link that holds the address of the next descriptor and constitutes a normal ring buffer. The descriptor has a status for storing status information of the packet area, and a packet area address indicating the start address of the packet area.
[0019]
One descriptor of the packet buffer for transmission expresses one packet, and one packet may be composed of a plurality of packet areas. That is, one packet can be distributed over a plurality of areas.
[0020]
In the descriptor shown in FIG. 4, the address of the next descriptor is set in the link field. The OWN bit is included in the control bits of the status field, the number of packet areas storing one packet managed by the descriptor is set as the number of packet areas, and the data length of the packet is set as the data length. Is set. In the packet area address field, there are as many pairs of packet area length and packet area address as the packet data length, and the packet area length (size) is set in the packet area length. The start address of the packet area is set as the address.
[0021]
At the time of transmission, the host interface 13 loads the packet buffer descriptor set by software by DMA, checks the OWN bit of the control bit in the descriptor, and transmits only when the OWN bit is set. When not standing, either the polling mode in which the descriptor is re-read by DMA at a certain time interval and repeated until the OWN bit is set, or the batch mode in which the operation is stopped on the spot is taken.
[0022]
When the OWN bit is set, it is assumed that there are as many packet area addresses as the number of packet areas, and the transmission data is transferred from the packet area indicated by the packet area address to the transmission FIFO buffer 15 by the DMA. The data stored in 15 is transmitted. When transmission of data for one descriptor (that is, data for one packet) is completed, the same processing is performed for the descriptor specified by the address indicated by the descriptor link. However, if the address indicated by the link is 0, transmission is stopped (that is, a transmission end interrupt is generated for the software).
[0023]
FIG. 5 shows a processing flow at the time of transmission.
[0024]
First, a transmission data threshold / transmission start threshold correspondence table register group is set (step 511).
[0025]
An example of a transmission data threshold / transmission start threshold correspondence table register group is shown in FIG. 6 and can register a plurality of pairs of transmission start thresholds corresponding to transmission data (packet data) thresholds. A group. In the embodiment of the present invention, it is assumed that five pairs can be registered. In the example of FIG. 6, 64 bytes, 128 bytes, 512 bytes, 1024 bytes, and 2048 bytes are set as the transmission data threshold values in the transmission data threshold registers 1 to 5, respectively. 32 bytes, 64 bytes, 128 bytes, 256 bytes, and 512 bytes are set in the transmission start threshold value registers 1 to 5 that form a pair with each of.
[0026]
At the time of data transmission, the data length (packet length) of the packet to be transmitted is compared with each transmission data threshold value, and the minimum transmission data threshold value among the transmission data threshold values to which the data length applies is selected. Then, the transmission start threshold value paired with the selected transmission data threshold value is selected as the transmission start threshold value for the packet to be transmitted. The selected transmission start threshold value is set in the transmission control unit to perform a transmission operation.
[0027]
For example, if the data length of a packet to be transmitted is 800 bytes, the minimum transmission data threshold value among the applicable transmission data threshold values is 1024 bytes, and a transmission start threshold value that is paired with this transmission data threshold value Is 256 bytes, and the transmission start threshold value is 256 bytes.
[0028]
Next, the address of the first descriptor is set in the host interface (step 512).
[0029]
Next, a transmission start instruction is issued to the host interface (step 513).
[0030]
The host interface reads the address of the set descriptor and loads the descriptor by DMA using this address (step 514).
[0031]
It is determined whether the OWN bit is set in the control bit of the status field of the loaded descriptor, that is, whether the OWN bit is “1” (step 515).
[0032]
If the OWN bit is “1”, the process proceeds to step 516.
[0033]
If the OWN bit is 0, the polling waits until it becomes “1”. If it is “1”, the process proceeds to step 516.
[0034]
Next, the data length of the status field of the loaded descriptor is compared with the transmission data threshold value set in the set transmission data threshold value / transmission start threshold value correspondence table register group . Select the transmission data threshold value that is the minimum of the transmission data threshold values that apply to the data length, and set the transmission start threshold value that is paired with the selected transmission data threshold value to the transmission start threshold value for the packet to be transmitted. Select as value. The selected transmission start threshold value is set in the transmission control unit (step 516).
[0035]
Next, the data in the packet area specified by the packet area address of the loaded descriptor is transferred to the transmission FIFO buffer by DMA (517).
[0036]
When step 517 ends, the next descriptor address is set in the host interface (step 518). Then, the processing after step 514 is repeated.
[0037]
Next, packet transmission control is performed by a transmission control unit.
[0038]
Data transferred by DMA from the packet area is stored in the transmit FIFO buffer. After the DMA starts, when the number of bytes of data received in the transmission FIFO buffer exceeds the transmission start threshold set in the transmission control unit, the transmission control unit starts data transmission (step 519).
[0039]
Data transmission is performed while extracting data from the transmission FIFO buffer (step 520).
[0040]
When DMA for the specified data length is completed, data indicating the end of the packet is written to the transmit FIFO buffer. When the transmission control unit receives this packet end data, it performs packet end processing and returns to the original state.
[0041]
When the DMA ends, the host interface sets the next descriptor indicated by the descriptor and repeats the same process.
[0042]
In the description of the embodiment of the present invention, the DMA suspension or transmission error processing when a collision or error occurs during transmission is not particularly relevant to the essence of the invention itself. The description of is omitted.
[0043]
In the description of the embodiment of the present invention, the case of ethernet is described. However, it is obvious that the transmission efficiency can be increased by the same processing for other packet transmissions such as IEEE1394 and USB. .
[0044]
【The invention's effect】
According to the first aspect of the present invention, when the packet length is short, transmission can be started quickly, and performance is improved without a transmission interval.
[0045]
According to the second to third aspects of the invention, it is possible to obtain an appropriate transmission start timing according to the packet length, and the performance is improved without a transmission interval regardless of the packet length.
[0046]
In the invention according to the fourth aspect, the threshold value can be changed according to the DMA speed and the performance of the bus to set the optimum performance.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a packet transmission / reception system.
FIG. 2 is a diagram illustrating a configuration of a packet transmitting / receiving apparatus (network adapter).
FIG. 3 is a diagram illustrating a configuration of a packet buffer.
FIG. 4 is a diagram illustrating a structure of a descriptor that is a component of a packet buffer.
FIG. 5 is a diagram showing a processing flow during transmission.
FIG. 6 is a diagram illustrating an example of a transmission data threshold value / transmission start threshold value correspondence table register group ;
[Explanation of symbols]
1 Program ROM
2 Main memory 3 CPU
4 Network adapter 5 System bus 11 EEPROM
12 Boot PROM
13 Host interface 14, 17 FIFO RAM
15 Transmission FIFO buffer 16 Reception FIFO buffer 18 Network management unit 19 Transmission control unit 20 Ethernet controller 21 Reception control unit 22 Clock 23 Encoder 24 Decoder 25 AUI
26 Twisted Pair Transceiver

Claims (3)

A part of the packet is taken into the buffer , the protocol is interpreted, and when the packet is a packet to be processed by the local station from another device, the packet is transferred to the packet area on the internal main memory, and the main memory in the device A packet transmitting / receiving apparatus that transmits a packet from the upper packet area,
A table in which a plurality of pairs of packet data threshold values and corresponding transmission start threshold values are prepared in advance;
Means for selecting a transmission start threshold value corresponding to the minimum packet data threshold value to which the transmission packet length of a packet to be transmitted for each descriptor applies, and setting the transmission start threshold value as a transmission start position from the table. A packet transmitting / receiving apparatus. The packet transmitting / receiving apparatus according to claim 1,
After the transmission start value is set, the packet transmission / reception apparatus starts packet transmission when data corresponding to the number of bytes satisfying the set transmission start value is input to the buffer . The packet transmission / reception apparatus according to claim 1 or 2 ,
A packet transmitting / receiving apparatus comprising means for registering the table.

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