JP2009134635A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system that increase efficiency of data transfer between a plurality of processors. <P>SOLUTION: In a configuration having, for example, a microcomputer [1]MC1 and a system memory MEM1 thereof, and a microcomputer [2]MC2 and a system memory MEM2 thereof, a data relay device PCIC is disposed on a path of data transfer from MEM1 to MEM2. PCIC includes a first buffer BFA and a second buffer BFB, which are accessed alternately when large volume data is transferred. For example, when a DMA controller DMAC1 in MC1 stores data into BFB, a DMA controller DMAC2 in MC2 reads out data from BFA (S63), and then DMAC1 stores the subsequent data into BFA emptied (S64). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multiprocessor system, and more particularly to a technique that is useful when applied to a multiprocessor system in which each processor transfers data between processors using each DMA controller (Direct Memory Access Controller).

  For example, when data is transferred between two processors, a method of installing a shared memory on a bus connecting the processors is known. When data transfer is performed using this method, one processor writes data to the shared memory and the other processor reads data from the shared memory while arbitrating the bus use right between the two processors. Is called.

  By the way, as a result of examination of the technique of the multiprocessor system as described above by the present inventor, the following has been clarified.

  FIG. 12 is a block diagram showing an example of the configuration of a conventional multiprocessor system studied as a premise of the present invention. The multiprocessor system shown in FIG. 12 has a configuration in which a processor [1] CPU1 and a processor [2] CPU2 are connected by a common local bus LBUS, and a transfer buffer BF is connected to this LBUS. For example, when data is transferred from the system memory MEM1 for the CPU1 to the system memory MEM2 for the CPU2, the data of the MEM1 is written to the transfer buffer BF via the CPU1, and the data of this BF is written to the MEM2 via the CPU2. .

  In order to perform such an operation, each of the CPUs 1 and 2 needs to have a bus arbitration function. For example, when writing to the buffer BF, the CPU 1 needs to ensure the LBUS authority by outputting the bus right request signal BREQ to the CPU 2 in advance and receiving the bus right request permission signal BACK from the CPU 2 as a response. There is. Further, when reading from the BF, the CPU 2 needs to secure the authority of the LBUS in the reverse procedure.

  Therefore, when such a configuration is used, the resources of the processor CPU are deprived during the transfer process, and for example, when data is divided and transferred, a handshake (BREQ and BACK) is required each time. Further, the CPU 2 waits while the CPU 1 is writing data to the BF. For this reason, there is a concern that the processing procedure becomes complicated, the transfer efficiency decreases, the processor processing efficiency decreases, and the like.

  The present invention has been made in view of the above, and an object of the present invention is to provide a multiprocessor system capable of improving the data transfer efficiency between a plurality of processors. Another object of the present invention is to provide a multiprocessor system capable of improving the data transfer efficiency between a plurality of processors with a small circuit scale. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the multiprocessor system according to the embodiment of the present invention, the data transfer between the first system memory on the first processor side and the second system memory on the second processor side is controlled by the first data transfer control on the first processor side. This is performed using a second data transfer control unit on the second processor side (typically a DMA controller) and the second processor side. The data transfer path between the first system memory and the second system memory includes a data relay unit including a data buffer including N (N ≧ 2) storage areas. Yes.

  For example, when data is transferred from the first system memory to the second system memory, the first data transfer control unit controls the data transfer from the first system memory to the data buffer of the data relay unit, and the second data transfer The control unit controls data transfer from the data buffer to the second system memory. At this time, the data from the first system memory is sequentially stored in the N storage areas from the first storage area to the Nth storage area, and then stored in the Nth storage area. After that, the data is stored back to the first storage area. On the other hand, in parallel with this, the data stored in the N storage areas are sequentially read from the first storage area to the Nth storage area and read from the Nth storage area. After being issued, the data is read back to the first storage area and transferred to the second system memory each time.

  At this time, it is monitored whether each of the N storage areas is written (full state) or read (empty state). When the target storage area is empty, the data relay unit enables data transfer (that is, writing to the storage area) of the first data transfer control unit, and the target storage area is full In this case, data transfer (that is, reading from the storage area) of the second data transfer control unit is enabled.

  When such a configuration is used, for example, when a large amount of data is transferred, a write operation to one storage area and a read operation to another storage area can be performed in parallel, and high data transfer efficiency is achieved. Can be realized. At this time, since a DMA controller or the like is used, it is possible to suppress a reduction in processing efficiency without depriving processor resources. Furthermore, since the N storage areas are used while being cycled, large-capacity data transfer can be realized using a small-capacity data buffer that does not have this capacity, and the circuit scale can be reduced. As a minimum configuration, two storage areas are used and the two storage areas are alternately written or read.

  The multiprocessor system according to an embodiment of the present invention includes a data buffer as described above for transferring data from the first system memory to the second system memory and from the second system memory to the first system memory. It is characterized by having two systems by dividing it for data transfer. In this case, for example, if bidirectional data transfer is set by using a plurality of channels included in the first data transfer control unit and the second data transfer control unit, the processing of each processor is not performed in the middle of the bidirectional data transfer. Data transfer can be performed in parallel. For example, when one data buffer is bidirectionally compatible, the circuit becomes complicated and the processing of the processor intervenes during the bidirectional data transfer. Further, for example, when two systems of bidirectional data buffers are provided, there is a concern that the circuit may be complicated or the circuit scale may be increased. Therefore, by providing two unidirectional data buffers as described above, bidirectional data transfer can be efficiently performed with a small circuit scale.

  By using the multiprocessor system according to the embodiment of the present invention, it is possible to improve the data transfer efficiency between a plurality of processors. In addition, data transfer efficiency between a plurality of processors can be improved with a small circuit scale.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. The other part or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  First, a multiprocessor system, which is a comparative example studied as a premise in examining the present invention, will be described. FIG. 1 is a block diagram showing an example of the configuration of a comparative multiprocessor system examined as a premise of the present invention. In the multiprocessor system shown in FIG. 1, a microcomputer (hereinafter abbreviated as a microcomputer) [1] MC1 and a system memory MEM1 for MC1 are connected to a local bus [1] LBUS1, and a microcomputer [ 2] MC2 and system memory MEM2 for this MC2 are connected.

  Further, the multiprocessor system of FIG. 1 includes a dual port memory DPRAM having LBUS1 and LBUS2 as one port and the other port, respectively. The microcomputer [1] MC1 includes a processor [1] CPU1 and a DMA controller [1] DMAC1, and the microcomputer [2] MC2 includes a processor [2] CPU2 and a DMA controller [2] DMAC2. For example, when it is desired to transfer data from MEM1 to MEM2, DMAC1 reads desired data from MEM1 and writes it to DPRAM, and DMAC2 reads this write data from DPRAM and writes it to MEM2. Therefore, unlike the case of FIG. 12 described above, the CPU 1 and CPU 2 resources are not deprived during the data transfer, so that the processing efficiency of the processor can be ensured to some extent.

  However, in this case, the maximum data transfer amount accompanying one activation of the DMA controller DMAC is the capacity of the DPRAM. Therefore, when transferring a large amount of data, it is necessary to use one of the following methods: (1) increasing the capacity of the DPRAM, and (2) starting the DMA controller DMAC multiple times by decreasing the capacity of the DPRAM. . First, when the method (1) is used, the circuit scale naturally increases.

  On the other hand, when the method (2) is used, the burden of software for controlling the CPU 1 and the CPU 2 increases. That is, for example, when the CPU 1 performs the N-th activation for the DMAC 1, it is necessary to confirm that the operation associated with the (N-1) -th activation performed by the CPU 2 for the DMAC 2 is completed. . Therefore, for example, the software of the CPU 2 asserts the interrupt signal [A] or the like when the operation completion notification is received from the DMAC 2 (for example, by an interrupt signal or the like), and the software of the CPU 1 It is necessary to execute processing such as detecting DMA assertion and starting DMAC1. Then, the software processing becomes complicated, and there is a risk that the data transfer efficiency and the processing efficiency of the processor CPU will be reduced with the execution of such processing. In the embodiments described below, solutions are made including such problems.

(Embodiment 1)
FIG. 2 is a block diagram showing an example of the configuration of the multiprocessor system according to the first embodiment of the present invention. The multiprocessor system shown in FIG. 2 includes a microcomputer [1] MC1 connected to the local bus [1] LBUS1, a microcomputer [2] MC2 connected to the local bus [2] LBUS2, and a system memory MEM1 for MC1. , A system memory MEM2 for MC2, and the like. The microcomputer [1] MC1 includes a processor [1] CPU1 and a DMA controller [1] DMAC1, and the microcomputer [2] MC2 includes a processor [2] CPU2 and a DMA controller [2] DMAC2. The local buses LBUS1 and LBUS2 are external buses connected to the outside of the microcomputers MC1 and MC2. Each of the microcomputers MC1 and MC2 includes an internal bus (not shown) that connects the processor and the DMA controller.

  The system memory MEM1 is connected to the microcomputer [1] MC1 via the memory bus MBUS1, and the system memory MEM2 is connected to the microcomputer [2] MC2 via the memory bus MBUS2. As is widely known, the DMA controller (data transfer control unit) DMAC previously determines the address of the transfer source device (memory address, IO address, etc.), the address of the transfer destination device, the size of the transfer data, etc. by the processor CPU. When a start command is received after the setting, the function of transferring data without going through the CPU based on this setting is provided. It is also possible to specify a device with a DREQ (data transfer request signal) as a transfer source device or a transfer destination device. In this case, when the DMAC receives a DREQ from the device, the DMAC accesses the device by transmitting a data transfer acceptance signal DACK. Note that the DMAC normally includes a plurality of channels, and the above-described setting can be arbitrarily performed for each channel.

  In such a configuration, the multiprocessor system of FIG. 2 is further characterized by further including a data relay device PCIC connected to LBUS1 and LBUS2. FIG. 3 is a block diagram showing a detailed configuration example of the data relay device PCIC in FIG. The data relay device PCIC shown in FIG. 3 includes a circuit unit for channel 0 that processes data transfer from LBUS1 to LBUS2, and a circuit unit for channel 1 that processes data transfer from LBUS2 to LBUS1.

  The circuit unit for channel 0 includes a write control unit WCTL0 connected to LBUS1, a read control unit RCTL0 connected to LBUS2, a buffer [A] BFA0, a buffer [B] BFB0 having a dual port, and a counter. Part CUNT0 is included. The circuit unit for channel 1 includes a read control unit RCTL1 connected to LBUS1, a write control unit WCTL1 connected to LBUS2, a buffer [A] BFA1, a buffer [B] BFB1, and a counter having dual ports, for example. Part CUNT1. Each of the buffers BFA0, BFB0, BFA1, and BFB1 is configured to be capable of arbitrary simultaneous access by using, for example, independent storage circuits, and is not particularly limited. Here, each of the buffers BFA0, BFB0, BFA1, and BFB1 has a capacity of 128 bytes. .

  When receiving a write command from the outside, the write control unit WCTL0 (WCTL1) receives write data from the local bus LBUS1 (LBUS2), and receives the write data from the buffer [A] BFA0 or the buffer [B] BFB0 (BFA1 or Write from one port of BFB1). Also, WCTL0 (WCTL1) recognizes the states of BFA0 and BFB0 (BFA1 and BFB1) by the control signal from the counter unit CUNT0 (CUNT1), and sends the data transfer request signal DREQ0 (DREQ1) to the outside according to the state. Send. DMAC1 (DMAC2) in FIG. 2 transmits a data transfer request acceptance signal DACK0 (DACK1) in response to this DREQ0 (DREQ1). Here, this DACK0 (DACK1) corresponds to a write command from the outside. become.

  When the read control unit RCTL0 (RCTL1) receives a read command from the outside, the read control unit RCTL0 (RCTL1) reads data from the other port of the buffer [A] BFA0 or the buffer [B] BFB0 (BFA1 or BFB1), and the read data is locally Transmit to bus LBUS2 (LBUS1). Further, RCTL0 (RCTL1) recognizes the states of BFA0 and BFB0 (BFA1 and BFB1) by the control signal from the counter unit CUNT0 (CUNT1), and sends the data transfer request signal DREQ0 (DREQ1) to the outside according to the state. Send. DMAC2 (DMAC1) in FIG. 2 transmits DACK0 (DACK1) in response to this DREQ0 (DREQ1), and here, this DACK0 (DACK1) corresponds to an external read command.

  FIG. 4 is a block diagram showing a detailed configuration example of the counter units CUNT0, 1 in FIG. The counter unit (buffer management unit) CUNT shown in FIG. 4 includes a write counter WCNT, a read counter RCNT, a state machine SM, and the like. The write counter WCNT counts the write pulses from the write control unit WCTL, and when the counter value is an integral multiple of 128 bytes, which is the capacity of each buffer, or when all transfers have been completed (to a preset setting value). When the counter value is reached, a control signal (wr_end) is transmitted to the state machine SM. The write pulse is generated every time the write control unit WCTL executes one cycle of writing to the buffers [A] BFA and [B] BFB. Note that a preset transfer value for the write counter WCNT sets a single transfer size. For example, in FIG. 4, 320 bytes are set.

  The read counter RCNT counts the read pulses from the read control unit RCTL, and when the counter value is an integral multiple of 128 bytes, which is the capacity of each buffer, or when all transfers are completed (set to a predetermined set value). When the counter value is reached, a control signal (rd_end) is transmitted to the state machine SM. The read pulse is generated every time the read control unit RCTL executes one cycle of reading from the buffers [A] BFA and [B] BFB. Note that a preset transfer value for the read counter RCNT sets a single transfer size.

  The state machine SM transitions to the full state (Not EMP) when the initial state is the empty state (EMP) and the control signal (wr_end) is received in this state. On the contrary, when the control signal (rd_end) is received in the full state (Not EMP), the state transits to the empty state (EMP). The determination of the empty state (EMP) or the full state (Not EMP) is performed for each of the buffers [A] BFA and [B] BFB. Then, the state machine SM is directed to the read control unit RCTL and the write control unit WCTL and each buffer [A] BFA, [B] BFB is in an empty state (EMP) or full state (for each cycle). (Not EMP).

  FIGS. 5A and 5B show examples of operations of the read control unit RCTL and the write control unit WCTL in FIG. 4. FIG. 5A is an operation explanatory diagram of the read control unit, and FIG. 5B is an operation explanatory diagram of the write control unit. . As shown in FIG. 5A, the read control unit RCTL receives the output signal from the state machine SM described above, and only when the buffer [A] BFA and the buffer [B] BFB are both empty (EMP). Disabled, otherwise enabled. On the other hand, as shown in FIG. 5B, the write control unit WCTL receives the output signal from the state machine SM described above, and both the buffer [A] BFA and the buffer [B] BFB are in the full state (Not EMP). Only disabled if disabled, otherwise enabled.

  The full state (Not EMP) means a state where the buffer is completely filled (FULL), or a state where the effective data of the buffer is less than 128 bytes (HALF) which is the capacity of each buffer. This state (HALF) is used when the count values of the write counter WCNT and the read counter RCNT become less than 128 bytes as described above.

  FIG. 6 is an explanatory diagram showing an example of the operation outline in the multiprocessor system of FIG. Here, it is assumed that the data in the MC1 system memory MEM1 in FIG. 2 is transferred to the MC2 system memory MEM2, and accordingly, the circuit unit for channel 0 in the data relay device PCIC in FIG. 3 is used. . Here, it is assumed that the local buses LBUS1 and LBUS2 operate at the same frequency.

  In S61 of FIG. 6, first, the CPU 1 sets the transfer source to MEM1 and the transfer destination to the PCIC for the DMAC1, and the CPU 2 sets the transfer source to the PCIC and the transfer destination to the MEM2 for the DMAC2. Each transfer size is set to 320 bytes here. Thereafter, CPU1 and CPU2 activate DMAC1 and DMAC2. The sizes of the buffer [A] BFA and the buffer [B] BFB are each 128 bytes. In the initial state, since both BFA and BFB are empty (EMP), the data transfer request signal DREQ is enabled for DMAC1 and DREQ is disabled for DMAC2.

  Next, in S62, the DMAC1 writes the data of the MEM1 from, for example, the port [1] of the buffer [A] BFA when the DREQ is enabled. On the other hand, the DMAC 2 enters a standby state when DREQ is disabled. Here, when 128 bytes of data are transferred to the BFA, the BFA is in a full state (FULL). When the BFA becomes full (FULL), the DREQ for the DMAC 2 transitions to enable.

  Subsequently, in S63, the DMAC1 writes the data of MEM1 from the port [1] of the buffer [B] BFB. On the other hand, the DMAC 2 reads the data in the buffer [A] BFA to the MEM 2 via the port [2] in accordance with the enablement of the DREQ. Here, when data of 128 bytes (that is, a total of 256 bytes) is transferred to the BFB, the BFB is in a full state (FULL). On the other hand, the BFA was originally in a full state (FULL), but transitions to an empty state (EMP) when a 128-byte transfer is performed along with DMAC2. Thereby, both the DREQ on the DMAC1 side and the DMAC2 side are kept enabled.

   Subsequently, in S64, the DMAC1 writes the data of MEM1 to the buffer [A] BFA that has become empty (EMP) in S63 via the port [1]. On the other hand, the DMAC 2 reads the data in the buffer [B] BFB to the MEM 2 via the port [2]. Here, when data of 64 bytes (that is, a total of 320 bytes) is transferred to the BFA, the BFA is in a full state (HALF). On the other hand, the BFB was originally full (FULL), but transitions to an empty state (EMP) when 128 bytes are transferred by the DMAC 2. Then, the transfer on the DMAC 1 side is completed, and the DMAC 1 notifies the CPU 1 of the completion of the data transfer using an interrupt signal or the like.

  Finally, in S65, the DMAC 2 reads the data in the buffer [A] BFA to the MEM 2 via the port [2]. Here, when 64 bytes of data are transferred from the BFA, the BFA transitions from the full state (HALF) to the empty state (EMP). The transfer on the DMAC 2 side is also completed, and the DMAC 2 notifies the CPU 2 of the completion of the data transfer using an interrupt signal or the like.

  FIG. 7 is an explanatory diagram showing an example of logical address assignment of the buffers BFA0, BFB0, BFA1, and BFB1 in the data relay device PCIC of FIG. As shown in FIG. 7, for example, 32 Mbytes of the base address + “h′000 0000 to h′1FF FFFF” is set as an apparent address space of the channel 0 buffer, and the base address + “h′200 0000 to h′3FF” “FFFF” of 32 Mbyte is assumed to be an apparent address space of the channel 1 buffer. For example, 32 MByte is the maximum data size that can be continuously transferred by the DMA controller DMAC, and a different DMA controller can be adopted to select a data size according to the application.

  Here, what actually physically exists as a buffer for channel 0 is a 128-byte buffer [A] BFA0 that becomes “h′000 0000 to h′000 007F”, and a 128-byte buffer [B] that follows this 128-byte buffer [B]. BFB0. Thereafter, the shadows of the buffer [A] and the shadows of the buffer [B] that do not exist physically continue alternately. On the other hand, what actually physically exists as a buffer for channel 1 is a 128-byte buffer [A] BFA1 that becomes “h′200 0000 to h′200 007F”, and a continuous 128-byte buffer [B] BFB1. It is. Thereafter, the shadows of the buffer [A] and the shadows of the buffer [B] that do not exist physically continue alternately.

  In other words, although only 256 bytes are provided as a buffer for channel 0 and 256 bytes are provided as a buffer for channel 1, each operation is performed by performing two alternate operations of buffer [A] and buffer [B] as described in FIG. Continuous data transfer of 32 MByte is possible for each channel. As can be seen from FIG. 6, in principle, the data is not limited to 32 MByte, and it is of course possible to transfer more data than that.

  Since the DMA controller DMAC normally has a specification for accessing a continuous address space, for example, immediately after accessing “h′000 00FF” serving as the buffer [B], it becomes a shadow of the buffer [A]. h'000 0100 "is accessed. However, this is an apparent access. In this case, the address actually accessed in the data relay device PCIC is “h′000 0000” which is the buffer [A]. Such a two-alternating operation method can be easily realized, for example, when an address “h′xxx xxxyy” is inputted and accessed only at the last two digits “yy”.

  As described above, by using the multiprocessor system of FIG. 2, (1) high data transfer efficiency can be realized, (2) processor processing efficiency at the time of data transfer can be improved, and (3) on a small circuit scale Data transfer efficiency or processor processing efficiency can be improved. That is, for example, as compared with the configuration example of FIG. 12, it is not necessary to provide each processor CPU with a bus arbitration function to perform the arbitration operation, and while the data transfer from one system memory MEM is performed, the other Data transfer can also be performed toward the system memory MEM. Further, for example, as compared with the configuration example of FIG. 1, continuous data transfer exceeding the capacity can be performed using a small capacity buffer BF. Further, since intervention of the processor CPU (DMAC operation using CPU software, etc.) is not required during the data transfer, a parallel operation of desired program processing by the CPU and data transfer between the system memories. Can be done efficiently.

  In the description of FIG. 3, etc., each buffer BFA0, BFB0, BFA1, BFB1 is a dual port memory. However, as can be seen from the description of FIG. 6, a write command and a read command are simultaneously issued to a certain buffer. It does not occur. Therefore, each buffer does not require an arbitration function at the time of simultaneous access, and the size of each buffer can be reduced. Further, for example, when the frequencies of the port [1] and the port [2] are the same or when a frequency difference can be allowed, each buffer can be a single port memory. Can be further reduced.

  FIG. 8 is an operation explanatory diagram supplementing FIG. In FIG. 6, it is assumed that the local buses LBUS1 and LBUS2 operate at the same frequency, but here, LBUS1 (that is, port [1] of the buffer BF) is twice that of LBUS2 (that is, port [2] of BF). Assume a case of operating at a frequency.

  In this case, for example, when the buffer [A] BFA is full (FULL) by the write operation from the port [1] side at t = t2 in FIG. 8, the data transfer request signal DREQ on the port [2] side is enabled. The BFA read operation is started from the port [2] side. After that, at t = t4, the buffer [B] BFB is filled (FULL) by the write operation from the port [1] side, but the BFA read operation from the port [2] side is only half completed. Therefore, both BFA and BFB are in a full state (FULL), and the DREQ on the port [1] side changes to disabled.

  At t = t5, with the DREQ on the port [1] side disabled, the DMAC that performs the write operation from the port [1] side is in a standby state, and only the read operation by the DMAC on the port [2] side is performed. Thereafter, when the BFA read operation from the port [2] side is completed at t = t6, the BFA transitions to an empty state (EMP), and the DREQ on the port [1] side transitions to enable. At t = t7, the write operation to the BFA by the DMAC on the port [1] side is resumed.

  When the frequencies of the local buses LBUS1 and LBUS2 are different as in t = t4 to t6, a standby state may occur in the DMAC on the local bus side with a fast frequency. However, since this is performed by hardware processing by the DMAC determining DREQ, the processing of the processor CPU does not intervene. In this embodiment, such a standby state occurs because the buffer BF is changed two times. For example, three buffers BFA, BFB, and BFC are changed three times, or N ( Such a standby state can be avoided to some extent by performing N alternation operation with N> 3) buffers. However, in this case, as a matter of course, the buffer capacity increases and various control circuits associated therewith are required. From this point of view, it is desirable to perform the two-shift operation.

  FIG. 9 is an explanatory diagram showing an operation example of the data relay device PCIC in FIG. As described above, the data relay device PCIC in FIG. 3 includes the channel 0 that handles transfer from the local bus LBUS1 to LBUS2, and the channel 1 that handles transfer from LBUS2 to LBUS1. Therefore, as shown in FIG. 9, for example, the process of transferring the storage area AR11 in the system memory MEM1 to the storage area AR21 in the system memory MEM2, and the storage area AR22 in the MEM2 is transferred to the storage area AR12 in the MEM1. Processing can be executed in parallel.

  In this case, for example, in channel 0 of DMAC1, the transfer source is set to AR11, the transfer destination is set to the PCIC channel 0 buffer, and in channel 1, the transfer source is set to the PCIC channel 1 buffer and the transfer destination is set to AR12. Set. On the other hand, in DMAC2 channel 0, the transfer source is set to the PCIC channel 0 buffer, the transfer destination is set to AR21, and in channel 1, the transfer source is set to AR22 and the transfer destination is set to the PCIC channel 1 buffer. To do.

  When the CPU 1 and the CPU 2 start up the DMAC 1 and the DMAC 2 after performing such setting, the bidirectional data transfer as described above can be performed without going through the CPU. For example, when each channel of DMAC1 and DMAC2 operates in a so-called round robin mode (a method in which the priority of the channel becomes the lowest when the transfer of one transfer unit is completed), each DMAC writes to the PCIC. The operation and the read operation are alternately performed in time series.

  Such bidirectional data transfer is useful, for example, when executing a program in which data processed by the CPU 1 is processed by the CPU 2 and data processed by the CPU 2 is further processed by the CPU 1. Although details will be described later, as in the case of the PCIC in FIG. 3, one of the two channels is used for data transfer of LBUS1 → LBUS2, and the other is used for data transfer of LBUS2 → LBUS1, so that the circuit scale is small or easy. An efficient bidirectional data transfer can be realized with a simple configuration.

  As described above, when the typical effect of using the multiprocessor system of the first embodiment is described, the data transfer efficiency between a plurality of processors can be improved. In addition, data transfer efficiency between a plurality of processors can be improved with a small circuit scale.

(Embodiment 2)
FIG. 10 is a block diagram showing a detailed configuration example of the data relay device PCIC in FIG. 2 in the multiprocessor system according to the second embodiment of the present invention. The data relay device PCIC shown in FIG. 10 includes a buffer [A] BFA and a buffer [B] BFB, and a counter unit CUNT, as in FIG. RWCTLa is configured to include a read / write control unit RWCTLb on the local bus LBUS2 side. That is, unlike FIG. 3, it is configured such that bidirectional data transfer is possible with one channel.

  For example, when data transfer from LBUS1 to LBUS2 is set by each DMAC, the read / write control unit RWCTLa operates as the write control unit WCTL as described above, and RWCTLb serves as the read control unit RCTL as described above. Operate. Conversely, when data transfer from LBUS2 to LBUS1 is set by each DMAC, RWCTLa operates as a read control unit RCTL, and RWCTLb operates as a write control unit WCTL.

  Even when such a configuration is used, various effects as described in the first embodiment can be obtained to some extent. However, in this case, the read / write control units RWCTLa and RWCTLb need to use control signals such as read enable and write enable for the buffer BF according to the transfer direction, and also transfer data to the DMA controller DMAC. It is necessary to use the logic of the request signal DREQ properly. Therefore, a large number of signal selection circuits are required, resulting in an increase in circuit scale and complication of control. In addition, if the operating frequencies of LBUS1 and LBUS2 are different, synchronization processing is also required depending on signal selection in some cases. Sometimes.

  Further, from the viewpoint of operation, when performing bidirectional data transfer as described in FIG. 9 by the configuration example of FIG. 10, first, the storage area AR11 of MEM1 is transferred to the storage area AR21 of MEM2, and then each CPU is transferred. The transfer from the storage area AR22 of the MEM2 to the storage area AR12 of the MEM1 is performed through the resetting and activation to each DMAC. In this case, data transfer efficiency and CPU processing efficiency are reduced as compared with the case of FIG. On the other hand, for example, if the configuration example shown in FIG. 10 is provided for two channels, the data transfer efficiency and CPU processing efficiency equivalent to those in FIG. However, in this case, as described above, there is a concern about an increase in circuit scale or complicated control. Further, for example, when two channels are activated at the same time and both of them are used for data transfer from LBUS1 to LBUS2, the merit in practical use is small.

  Therefore, from such a viewpoint, it is desirable to use the configuration example as shown in FIG. The configuration example as shown in FIG. 10 is useful when the number of channels that can be used in the DMA controller DMAC is limited (for example, one).

(Embodiment 3)
FIG. 11 is a schematic diagram showing an example of the configuration of a multiprocessor system according to Embodiment 3 of the present invention. The multiprocessor system shown in FIG. 11 includes a personal computer PC and an image processing board BD connected to, for example, a PCI Express slot terminal included in the PC. The PC includes a processor CPU1, a system memory MEM1, a DMA controller DMAC1, a controller CTL1, and the like, and can communicate with the board BD from the CTL1 through a slot terminal.

  The board BD is equipped with a microcomputer MC including a processor CPU2 and a DMA controller DMAC2, a system memory MEM2 for the microcomputer, a data relay device PCIC as described in the first and second embodiments, a controller CTL2, and the like. . The PCIC is connected to the microcomputer MC through a local bus LBUS1, and is connected to the controller CTL2 through a local bus LBUS2. The CTL2 has a communication function of, for example, PCI Express, and the board BD can communicate with the PC via the CTL2. Although not particularly limited, LBUS1 operates at 66 MHz, for example, and LBUS2 operates at 50 MHz, for example.

  In such a multiprocessor system, for example, relatively large-capacity image data processed by the CPU 1 of the PC is transmitted to the board BD, and the transferred image data is processed by the microcomputer MC of the board BD. The operation of returning to the PC is repeated. Therefore, how much the data transfer efficiency between the system memory MEM1 in the PC and the system memory MEM2 in the board BD can be increased is important in determining the performance of image processing. In recent years, the miniaturization of the board BD has become an important factor due to the spread of mobile terminals. Under such circumstances, it is possible to obtain a beneficial effect for the above-described requirements by mounting the data relay device PCIC as described above on the board BD.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  For example, in FIG. 2, a configuration example using a microcomputer is used as an example, but of course, it is not necessary to be a microcomputer, and the processor CPU and the DMA controller DMAC may be configured as separate chips, such as a personal computer. . In FIG. 2, the system memory MEM is an external memory, but, of course, it may be a built-in memory in a microcomputer. That is, the processor CPU, the DMA controller DMAC, and the system memory MEM are connected by a plurality of buses via one bus or a bus controller, and the CPU can set and start the DMAC. Any configuration that allows MEM access is acceptable.

  The multiprocessor system according to the present embodiment is a general multiprocessor system including a plurality of processors and a plurality of DMA controllers, such as an image processing system that performs desired processing while frequently exchanging data between the processors. Widely applicable.

1 is a block diagram showing an example of the configuration of a comparative multiprocessor system studied as a premise of the present invention. FIG. 1 is a block diagram showing an example of the configuration of a multiprocessor system according to Embodiment 1 of the present invention. FIG. 3 is a block diagram illustrating a detailed configuration example of a data relay device in FIG. 2. It is a block diagram which shows the detailed structural example of the counter part in FIG. FIGS. 4A and 4B show an operation example of the read control unit and the write control unit in FIG. 4. FIG. 4A is an operation explanatory diagram of the read control unit, and FIG. FIG. 3 is an explanatory diagram showing an example of an operation outline in the multiprocessor system of FIG. 2. FIG. 4 is an explanatory diagram showing an example of logical address assignment of each buffer in the data relay device of FIG. 3. It is operation | movement explanatory drawing which supplements FIG. FIG. 4 is an explanatory diagram showing an operation example in the data relay device of FIG. 3. 3 is a block diagram illustrating a detailed configuration example of a data relay device in FIG. 2 in a multiprocessor system according to a second embodiment of the present invention. FIG. It is the schematic which shows an example of the structure in the multiprocessor system by Embodiment 3 of this invention. 1 is a block diagram showing an example of the configuration of a conventional multiprocessor system studied as a premise of the present invention. FIG.

Explanation of symbols

MC Microcomputer CPU Processor DMAC DMA Controller MEM System Memory LBUS Local Bus DPRAM Dual Port Memory PCIC Data Relay Device MBUS Memory Bus WCTL Write Controller RCTL Read Controller BF, BFA, BFB Buffer CUNT Counter WCNT Write Counter RCNT Read Counter SM State Machine RWCTL Read / write control unit CTL controller PC Personal computer BD board

Claims (4)

A first bus and a second bus;
A first processor and a second processor;
A first memory accessed by the first processor;
According to the setting from the first processor, the first memory is accessed without going through the first processor, the read data is transferred to the first bus, or the write data from the first bus is transferred to the first memory. A first data transfer control unit for controlling transfer to one memory;
A second memory accessed by the second processor;
According to the setting from the second processor, the second memory is accessed without going through the second processor, the read data is transferred to the second bus, or the write data from the second bus is A second data transfer control unit that controls transfer to the two memories;
A data relay unit including a data buffer connected to the first bus and the second bus and including N (N ≧ 2) storage areas;
The data relay unit
A buffer management unit for managing whether each of the N storage areas is full corresponding to written or empty corresponding to read;
An enable signal is output to the first or second data transfer control unit according to whether or not the N storage areas are empty, and the data transferred from the first memory to the first bus or the second A write control unit for sequentially writing data transferred from the memory to the second bus from the first storage area as the first of the N storage areas to the Nth storage area as the Nth;
Depending on whether the N storage areas are full or not, an enable signal is output to the second or first data transfer control unit, and the data written in the N storage areas is transferred to the first storage area. A read control unit for sequentially reading from the first to the Nth storage area and transferring the read data to the second bus or the first bus,
The write control unit writes the data following the data in the Nth storage area back to the first storage area when the writing of the Nth storage area is completed and the first storage area is empty,
When the read of the Nth storage area is completed and the first storage area is full, the read control unit returns to the first storage area and reads. The multiprocessor system of claim 1, wherein
The data relay unit
First and second data buffers to be the data buffers;
First and second buffer managers serving as the buffer manager;
First and second light control units serving as the light control unit;
A first and second lead control unit serving as the lead control unit;
The first buffer management unit manages the N storage areas of the first data buffer;
The second buffer management unit manages the N storage areas of the second data buffer;
The first write control unit outputs an enable signal to the first data transfer control unit according to whether or not the N storage areas in the first data buffer are empty, and the first data control unit outputs the enable signal from the first memory. Write the data transferred to the bus to the first data buffer;
The first read control unit outputs an enable signal to the second data transfer control unit according to whether or not the N storage areas in the first data buffer are full, and is written to the first data buffer. Transfer the data to the second bus,
The second write control unit outputs an enable signal to the second data transfer control unit according to whether or not the N storage areas in the second data buffer are empty, and outputs the enable signal from the second memory. Write the data transferred to the bus to the second data buffer;
The second read control unit outputs an enable signal to the first data transfer control unit according to whether or not the N storage areas in the second data buffer are full, and is written to the second data buffer. A multiprocessor system, wherein the data is transferred to the first bus. The multiprocessor system of claim 1, wherein
2. The multiprocessor system according to claim 1, wherein the N storage areas are two storage areas. The multiprocessor system according to claim 3, wherein
The multi-processor system is characterized in that the two storage areas are realized by two storage circuits formed independently of each other.

Images