JP2007173658A - Method for manufacturing wiring board - Google Patents

Method for manufacturing wiring board Download PDF

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JP2007173658A
JP2007173658A JP2005371360A JP2005371360A JP2007173658A JP 2007173658 A JP2007173658 A JP 2007173658A JP 2005371360 A JP2005371360 A JP 2005371360A JP 2005371360 A JP2005371360 A JP 2005371360A JP 2007173658 A JP2007173658 A JP 2007173658A
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wiring
core
support substrate
wiring board
insulating layer
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JP5042495B2 (en
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Hiroichi Yamada
博一 山田
Naoki Miyoshi
直樹 三好
Masaharu Yasuda
正治 安田
Itsuro Shishido
逸朗 宍戸
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a thin wiring board with high mounting density. <P>SOLUTION: The manufacturing method for the wiring board 100 includes a process of alternately laminating insulating layers 11 to 15 and wiring conductors 21 to 24 on the main surface of a support board 1, to form a core lamination 10 composed of the insulating layers 11 to 15 and the wiring conductors 21 to 24; a process of peeling the core lamination 10 off the support board 1; and a process of laminating respective wiring conductors 25 to 28 and insulating layers 16 to 19 alternately on both surfaces of the core lamination 10. In easily peeling the core lamination 10 off the support board 1 without damaging the core lamination 10, the process of forming the core lamination 10 includes a process of interposing a given adhesive between the support board 1 and the core lamination 10, and, preferably, the process of peeling the core lamination 10 of the support board 1 is carried out after the adhesion of the adhesive is lessened or eliminated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子等の電子部品を搭載するために用いられる配線基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a wiring board used for mounting electronic components such as semiconductor elements.

従来から、半導体素子等の電子部品を搭載するために用いられる高密度多層配線基板として、ビルドアップ配線基板がある。図5は、一般的なビルドアップ配線基板を示す概略断面図である。同図に示すように、このビルドアップ配線基板80は、厚みが0.2〜2.0mm程度のガラス−樹脂板81の両面に銅箔から成る配線導体82を有するコア基板83と、このコア基板83の両面に、それぞれの厚みが10〜100μm程度の樹脂から成る絶縁層84と、めっき膜から成る配線導体85とを交互に積層して成る。このようなビルドアップ配線基板80は、例えば下記の方法により製作される。   Conventionally, there is a build-up wiring board as a high-density multilayer wiring board used for mounting electronic components such as semiconductor elements. FIG. 5 is a schematic cross-sectional view showing a general build-up wiring board. As shown in the figure, the build-up wiring board 80 includes a core board 83 having wiring conductors 82 made of copper foil on both surfaces of a glass-resin plate 81 having a thickness of about 0.2 to 2.0 mm, and the core. Insulating layers 84 made of a resin having a thickness of about 10 to 100 μm and wiring conductors 85 made of a plating film are alternately laminated on both surfaces of the substrate 83. Such a build-up wiring board 80 is manufactured by, for example, the following method.

まず、ガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた絶縁シートを準備する。次に、この絶縁シートの両面に銅箔を貼着するとともに、絶縁シート中の熱硬化性樹脂を熱硬化させて両面銅張り板を得る。この両面銅張り板に、その上下面を貫通するスルーホールを穿孔するとともに、前記スルーホール内壁にめっき膜を被着させて、上下面の銅箔をスルーホール内のめっき膜で電気的に接続する。そして、スルーホール内を樹脂で充填した後、上下面の銅箔を所定パターンにエッチングすることにより、ガラス−樹脂板81の両面に銅箔から成る配線導体82を有するコア基板83を得る。   First, an insulating sheet in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is prepared. Next, copper foil is stuck on both sides of the insulating sheet, and the thermosetting resin in the insulating sheet is thermoset to obtain a double-sided copper-clad plate. This double-sided copper-clad plate is drilled with through-holes that penetrate the upper and lower surfaces, and a plating film is deposited on the inner wall of the through-hole, and the copper foils on the upper and lower surfaces are electrically connected by the plating film in the through-holes. To do. Then, after filling the through hole with resin, the upper and lower copper foils are etched into a predetermined pattern to obtain a core substrate 83 having wiring conductors 82 made of copper foil on both surfaces of the glass-resin plate 81.

次に、このコア基板83の上下面にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂に無機絶縁性フィラーを分散させた樹脂フィルムを貼着するとともに、樹脂フィルム中の熱硬化性樹脂を熱硬化させて絶縁層84を形成する。この絶縁層84に、レーザ加工によりビアホールを穿孔するとともに、ビアホール内を含む絶縁層84の表面に、セミアディティブ法で、めっき膜から成る配線導体85を上下面同時に形成する。そして、次層の絶縁層84や配線導体85の形成を複数回繰り返すことにより、ガラス−樹脂板81の両面に銅箔から成る配線導体82を有するコア基板83と、このコア基板83の両面に樹脂から成る絶縁層84と、めっき膜とから成る配線導体85とを交互に積層して成るビルドアップ配線基板80が製作される。   Next, a resin film in which an inorganic insulating filler is dispersed in a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is attached to the upper and lower surfaces of the core substrate 83, and the thermosetting resin in the resin film is attached. The insulating layer 84 is formed by heat curing. A via hole is drilled in the insulating layer 84 by laser processing, and a wiring conductor 85 made of a plating film is simultaneously formed on the surface of the insulating layer 84 including the inside of the via hole by a semi-additive method. Then, by repeating the formation of the next insulating layer 84 and the wiring conductor 85 a plurality of times, a core substrate 83 having wiring conductors 82 made of copper foil on both surfaces of the glass-resin plate 81 and both surfaces of the core substrate 83 are formed. A build-up wiring board 80 is produced in which insulating layers 84 made of resin and wiring conductors 85 made of a plating film are alternately laminated.

しかしながら、このようなビルドアップ配線基板80は、高密度配線が可能であるものの、コア基板83として厚みが0.2〜2.0mm程度のガラス−樹脂板81を使用することから、配線基板80の全体厚みを薄くすることが困難であるという問題点があった。   However, although such a build-up wiring board 80 enables high-density wiring, the glass-resin plate 81 having a thickness of about 0.2 to 2.0 mm is used as the core board 83. There is a problem that it is difficult to reduce the overall thickness of the film.

そこで、特許文献1には、金属板の一面側に配線導体と絶縁層とを、半導体素子搭載面側から外部接続端子装着面側に向けて順次多層に形成した後、前記金属板をエッチング除去することにより半導体装置用の多層基板を製造する方法が記載されている。この特許文献1に示された方法によれば、半導体素子搭載面が平坦であり、且つ薄型の半導体装置用の多層基板を提供できるとしている。   Therefore, in Patent Document 1, a wiring conductor and an insulating layer are sequentially formed on one surface side of a metal plate from the semiconductor element mounting surface side to the external connection terminal mounting surface side, and then the metal plate is etched away. Thus, a method for manufacturing a multilayer substrate for a semiconductor device is described. According to the method disclosed in Patent Document 1, a semiconductor device mounting surface is flat and a thin multilayer substrate for a semiconductor device can be provided.

しかしながら、この方法によると、半導体装置用の多層基板を構成する配線導体と絶縁層とを、金属板の一面側に、半導体素子搭載面側から外部接続端子装着面側に向けて1層ずつ順次積層していく必要があるとともに、最終的に金属板をエッチングで除去する必要があることから、その製造工程が極めて煩雑であるという解決すべき問題点を有していた。さらに、前記金属板を除去した際には、基板に残留応力による反りや、うねりが発生するおそれがある。
特許第3635219号公報
However, according to this method, the wiring conductor and the insulating layer constituting the multilayer substrate for the semiconductor device are sequentially layered one by one from the semiconductor element mounting surface side to the external connection terminal mounting surface side on one surface side of the metal plate. Since it is necessary to stack the layers and finally the metal plate needs to be removed by etching, there is a problem to be solved that the manufacturing process is extremely complicated. Further, when the metal plate is removed, the substrate may be warped or wavy due to residual stress.
Japanese Patent No. 3635219

本発明の課題は、薄型で高密度な配線基板を効率よく製造することが可能な配線基板の製造方法を提供することにある。   The subject of this invention is providing the manufacturing method of the wiring board which can manufacture a thin and high-density wiring board efficiently.

本発明者らは、上記課題を解決すべく鋭意研究を重ねた結果、以下の構成からなる解決手段を見出し、本発明を完成するに至った。
(1)支持基板の主面上に絶縁層と配線導体とを交互に積層して前記絶縁層と前記配線導体とから成るコア積層体を形成する工程と、前記支持基板から前記コア積層体を剥離する工程と、剥離した前記コア積層体の上下両面上に、それぞれ配線導体と絶縁層とを交互に積層する工程とを含むことを特徴とする配線基板の製造方法。
(2)前記支持基板の主面が平坦である前記(1)記載の配線基板の製造方法。
(3)前記配線導体がセミアディティブ法で形成される前記(1)または(2)記載の配線基板の製造方法。
(4)前記コア積層体を形成する工程は、前記支持基板とコア積層体との間に所定の接着層を介在させる工程を含み、前記支持基板から前記コア積層体を剥離する工程は、前記接着層の接着力を低下もしくは消失させた後、前記支持基板から前記コア積層体を剥離する工程である前記(1)〜(3)のいずれかに記載の配線基板の製造方法。
(5)前記コア積層体を形成する工程が、前記支持基板の上下両面上に、それぞれ絶縁層と配線導体とを交互に積層して前記絶縁層と前記配線導体とから成るコア積層体を形成する工程である前記(1)〜(4)のいずれかに記載の配線基板の製造方法。
As a result of intensive studies to solve the above-mentioned problems, the present inventors have found a solution means having the following constitution and have completed the present invention.
(1) forming a core laminate comprising the insulating layer and the wiring conductor by alternately laminating insulating layers and wiring conductors on a main surface of the support substrate; and forming the core laminate from the support substrate. A method for manufacturing a wiring board, comprising: a step of peeling, and a step of alternately laminating wiring conductors and insulating layers on both upper and lower surfaces of the peeled core laminate.
(2) The method for manufacturing a wiring board according to (1), wherein a main surface of the support substrate is flat.
(3) The method for manufacturing a wiring board according to (1) or (2), wherein the wiring conductor is formed by a semi-additive method.
(4) The step of forming the core laminate includes a step of interposing a predetermined adhesive layer between the support substrate and the core laminate, and the step of peeling the core laminate from the support substrate includes the step of The method for manufacturing a wiring board according to any one of (1) to (3), which is a step of peeling the core laminate from the support substrate after reducing or eliminating the adhesive strength of the adhesive layer.
(5) The step of forming the core laminated body forms a core laminated body composed of the insulating layer and the wiring conductor by alternately laminating insulating layers and wiring conductors on the upper and lower surfaces of the support substrate. The manufacturing method of the wiring board in any one of said (1)-(4) which is a process to perform.

前記(1)によれば、支持基板の主面上に絶縁層と配線導体とを交互に積層してコア積層体を形成した後、前記支持基板から剥離したコア積層体の上下両面上に、それぞれ配線導体と絶縁層とを交互に積層することから、ガラス−樹脂板を使用することによる配線基板の全体厚みを薄くすることができないという問題がなく、薄型で高密度の配線基板を提供することができる。しかも、コア積層体の上下面に配線導体を形成する際に、上下の配線導体同士を同時に加工することができるので、薄型で高密度な配線基板を効率よく製造することができるとともに、加工に伴う反りや、うねりの発生を抑制することができ、その結果、平坦度が高く実装性に優れる配線基板を提供することができる。   According to (1), after forming a core laminate by alternately laminating insulating layers and wiring conductors on the main surface of the support substrate, on both upper and lower surfaces of the core laminate peeled from the support substrate, Since wiring conductors and insulating layers are alternately laminated, there is no problem that the entire thickness of the wiring board cannot be reduced by using a glass-resin plate, and a thin and high-density wiring board is provided. be able to. Moreover, when forming the wiring conductors on the upper and lower surfaces of the core laminate, the upper and lower wiring conductors can be processed at the same time, so that a thin and high-density wiring board can be efficiently manufactured and processed. It is possible to suppress the accompanying warpage and undulation, and as a result, it is possible to provide a wiring board having high flatness and excellent mountability.

前記(2)によれば、本発明にかかる配線基板の平坦度をより高くすることができる。前記(3)によれば、本発明にかかる配線導体を簡単に効率よく形成することができる。前記(4)によれば、コア積層体を破損することなく簡単に支持基板から剥離することができる。前記(5)によれば、コア積層体を効率よく形成することができる。   According to said (2), the flatness of the wiring board concerning this invention can be made higher. According to said (3), the wiring conductor concerning this invention can be formed easily and efficiently. According to said (4), it can peel easily from a support substrate, without damaging a core laminated body. According to said (5), a core laminated body can be formed efficiently.

本発明における配線基板の製造方法の一例について、図面を参照して詳細に説明する。図1〜図3は、本発明の配線基板の製造方法を説明するための工程毎の概略断面図である。これらの図面うち、図1(a)〜(d)は、コア積層体を形成する工程を示す概略断面図であり、図2は、支持基板からコア積層体を剥離した状態を示す概略断面図であり、図3(a)〜(c)は、コア積層体の上下両面に配線導体と絶縁層とを交互に積層する工程を示す概略断面図である。   An example of a method for manufacturing a wiring board according to the present invention will be described in detail with reference to the drawings. 1 to 3 are schematic cross-sectional views for each process for explaining a method of manufacturing a wiring board according to the present invention. Among these drawings, FIGS. 1A to 1D are schematic cross-sectional views showing a process of forming a core laminate, and FIG. 2 is a schematic cross-sectional view showing a state in which the core laminate is peeled from a support substrate. FIGS. 3A to 3C are schematic cross-sectional views showing a process of alternately laminating wiring conductors and insulating layers on the upper and lower surfaces of the core laminate.

まず、図1(a)に示すように、平坦な主面を有する支持基板1を準備する。支持基板1は、その主面上に下記で説明するコア積層体10を仮支持するための仮支持体として機能する。このため、例えばガラスやセラミックス、硬質樹脂、金属等の硬質材料から成るのが好ましい。また、支持基板1は厚みが0.2〜2.0mm程度で、1辺の長さが300〜1000mm程度の略四角形の平板で構成されているが、これに限定されるものではない。   First, as shown in FIG. 1A, a support substrate 1 having a flat main surface is prepared. The support substrate 1 functions as a temporary support for temporarily supporting the core laminate 10 described below on the main surface. For this reason, it is preferable that it consists of hard materials, such as glass, ceramics, hard resin, a metal. Moreover, although the support substrate 1 is comprised by the substantially rectangular flat plate whose thickness is about 0.2-2.0 mm and the length of one side is about 300-1000 mm, it is not limited to this.

次に、図1(b)に示すように、支持基板1の主面に第1の絶縁層11を積層する。具体的には、まず、エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂に、無機絶縁性フィラーを分散させた樹脂フィルムを、支持基板1の主面に貼着する。前記樹脂フィルムの厚みは10〜100μm程度であるのが好ましい。ついで、貼着された樹脂フィルム中の熱硬化性樹脂を熱硬化させることにより、絶縁層11が積層される。   Next, as shown in FIG. 1B, the first insulating layer 11 is laminated on the main surface of the support substrate 1. Specifically, first, a resin film in which an inorganic insulating filler is dispersed in a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is attached to the main surface of the support substrate 1. The thickness of the resin film is preferably about 10 to 100 μm. Subsequently, the insulating layer 11 is laminated | stacked by thermosetting the thermosetting resin in the stuck resin film.

次に、図1(c)に示すように、第1の絶縁層11の表面に第1の配線導体21を積層する。この第1の配線導体21は、例えば銅めっき膜等のめっき膜から成り、セミアディティブ法で形成するのが好ましい。セミアディティブ法は、微細配線化に優れるので、本発明にかかる配線導体を簡単に効率よく形成することができる。具体的には、まず、第1の絶縁層11の表面を必要に応じて粗化し、その表面に無電解銅めっき膜を0.1〜2.0μm程度の厚みで被着させる。   Next, as shown in FIG. 1C, the first wiring conductor 21 is laminated on the surface of the first insulating layer 11. The first wiring conductor 21 is made of a plating film such as a copper plating film and is preferably formed by a semi-additive method. Since the semi-additive method is excellent in miniaturization, the wiring conductor according to the present invention can be formed easily and efficiently. Specifically, first, the surface of the first insulating layer 11 is roughened as necessary, and an electroless copper plating film is deposited on the surface with a thickness of about 0.1 to 2.0 μm.

前記無電解銅めっき膜の表面に、配線導体21に対応した開口部を有するめっきレジスト層を形成する。このめっきレジスト層は、感光性の樹脂フィルムを前記無電解銅めっき膜上に貼着するとともに、その樹脂フィルムにフォトリソグラフィー技術を採用して、露光・現像処理を施すことにより、前記開口部を有するように形成される。   A plating resist layer having an opening corresponding to the wiring conductor 21 is formed on the surface of the electroless copper plating film. The plating resist layer is formed by adhering a photosensitive resin film on the electroless copper plating film, and adopting a photolithographic technique for the resin film to perform exposure / development treatment, thereby opening the opening. Formed to have.

そして、めっきレジスト層の開口部内に露出する前記無電解銅めっき膜上に電解銅めっき膜を5〜30μm程度の厚みで被着させた後、めっきレジスト層を剥離する。最後に、前記無電解銅めっき膜および電解銅めっき膜の露出部を、配線導体21間の無電解銅めっき膜が消失するまで全体的にエッチングして、配線導体21が形成される。この配線導体21の厚みは5〜30μm程度であるのが好ましい。   Then, after the electrolytic copper plating film is deposited with a thickness of about 5 to 30 μm on the electroless copper plating film exposed in the opening of the plating resist layer, the plating resist layer is peeled off. Finally, the electroless copper plating film and the exposed portion of the electrolytic copper plating film are entirely etched until the electroless copper plating film between the wiring conductors 21 disappears, whereby the wiring conductor 21 is formed. The thickness of the wiring conductor 21 is preferably about 5 to 30 μm.

次に、図1(d)に示すように、第1の絶縁層11および第1の配線導体21上に第2の絶縁層12および第2の配線導体22を積層し、その上に第3の絶縁層13および第3の配線導体23を積層し、その上に第4の絶縁層14および第4の配線導体24を積層し、さらにその上に第5の絶縁層15を積層する。これにより、支持基板1の表面上に絶縁層11、12、13、14、15と、配線導体21、22、23、24とを交互に積層して成るコア積層体10が形成される。   Next, as shown in FIG.1 (d), the 2nd insulating layer 12 and the 2nd wiring conductor 22 are laminated | stacked on the 1st insulating layer 11 and the 1st wiring conductor 21, and 3rd on it. The fourth insulating layer 13 and the third wiring conductor 23 are stacked, the fourth insulating layer 14 and the fourth wiring conductor 24 are stacked thereon, and the fifth insulating layer 15 is further stacked thereon. Thereby, the core laminated body 10 formed by alternately laminating the insulating layers 11, 12, 13, 14, 15 and the wiring conductors 21, 22, 23, 24 is formed on the surface of the support substrate 1.

第2〜第5の絶縁層12〜15は、第1の絶縁層11と同様の材料から成るのが好ましく、第1の絶縁層11の場合と同様の樹脂フィルムを下層となる絶縁層および配線導体の上に貼着するとともに、それを熱硬化させることによって形成される。このとき、第2〜第4の絶縁層12〜14には、下層の配線導体と上層の配線導体とを電気的に接続するための通路となるビアホールVHをレーザ加工やフォトリソグラフィー加工等により穿孔しておく。また、第2〜第4の配線導体22〜24は、第1の配線導体21と同様のめっき膜から成るのが好ましく、第1の配線導体21と同様のセミアディティブ法で形成されるのが好ましい。   The second to fifth insulating layers 12 to 15 are preferably made of the same material as that of the first insulating layer 11, and an insulating layer and a wiring having a resin film similar to that of the first insulating layer 11 as a lower layer. It is formed by sticking on a conductor and thermosetting it. At this time, via holes VH serving as paths for electrically connecting the lower wiring conductor and the upper wiring conductor are drilled in the second to fourth insulating layers 12 to 14 by laser processing, photolithography processing, or the like. Keep it. The second to fourth wiring conductors 22 to 24 are preferably made of the same plating film as the first wiring conductor 21 and are formed by the same semi-additive method as the first wiring conductor 21. preferable.

ここで、各絶縁層12〜15の厚みは、第1の絶縁層11で例示した厚みと同じ厚みを例示することができ、各配線導体22〜24の厚みは、第1の配線導体21で例示した厚みと同じ厚みを例示することができる。そして、コア積層体10の厚みは100〜500μm程度であるのが好ましく、コア積層体10の厚みがこの範囲となるように、各絶縁層11〜15および各配線導体21〜24の厚みを上記範囲内で調整するのがよい。
一方、コア積層体10の厚みが500μmを超えると、配線基板の全体厚みを薄くすることが困難となり、100μmより薄いと、コア積層体10の強度が低下するので好ましくない。
Here, the thickness of each insulating layer 12-15 can illustrate the same thickness as the thickness illustrated by the 1st insulating layer 11, and the thickness of each wiring conductor 22-24 is the 1st wiring conductor 21. The same thickness as illustrated can be illustrated. And it is preferable that the thickness of the core laminated body 10 is about 100-500 micrometers, and the thickness of each insulating layer 11-15 and each wiring conductor 21-24 is mentioned above so that the thickness of the core laminated body 10 may become this range. It is better to adjust within the range.
On the other hand, if the thickness of the core laminate 10 exceeds 500 μm, it is difficult to reduce the overall thickness of the wiring board, and if it is less than 100 μm, the strength of the core laminate 10 is not preferable.

次に、図2に示すように、コア積層体10を支持基板1から剥離する。コア積層体10を支持基板1から剥離する方法としては、特に限定されるものではないが、本発明では、支持基板1とコア積層体10との間に特定の接着層を介在させるのが好ましい。これによると、コア積層体10を破損することなく簡単に支持基板1から剥離することができる。具体的には、支持基板1の主面上に第1の絶縁層11を形成する際に、支持基板1と第1の絶縁層11との間に、例えば熱の印加や紫外線の照射等により、接着力が低下もしくは消失する接着層(不図示)を予め介在させておき、コア積層体10の完成後にその接着層に熱の印加や紫外線の照射を行って接着層の接着力を低下もしくは消失させた後、支持基板1からコア積層体10を引き剥がす。これにより、コア積層体10を破損することなく簡単に剥離することができる。   Next, as shown in FIG. 2, the core laminate 10 is peeled from the support substrate 1. The method of peeling the core laminate 10 from the support substrate 1 is not particularly limited, but in the present invention, it is preferable to interpose a specific adhesive layer between the support substrate 1 and the core laminate 10. . According to this, it can peel from the support substrate 1 easily, without damaging the core laminated body 10. FIG. Specifically, when the first insulating layer 11 is formed on the main surface of the support substrate 1, for example, by application of heat or irradiation of ultraviolet rays between the support substrate 1 and the first insulating layer 11. An adhesive layer (not shown) in which the adhesive strength is reduced or disappeared is interposed in advance, and after the core laminate 10 is completed, the adhesive layer is subjected to heat application or ultraviolet irradiation to reduce the adhesive strength of the adhesive layer or After the disappearance, the core laminate 10 is peeled off from the support substrate 1. Thereby, it can peel easily, without damaging the core laminated body 10. FIG.

熱の印加により接着力が低下もしくは消失する前記接着層としては、例えば粘着剤中に、加熱により容易にガス化して膨張する物質を、弾性を有する殻内に内包させた熱膨張性微小球を配合した接着性樹脂材料等が例示できる。ここで、前記粘着剤としては、例えばゴム系粘着剤、アクリル系粘着剤、ビニルアルキルエーテル系粘着剤、シリコーン系粘着剤、ポリエステル系粘着剤、ポリアミド系粘着剤、ウレタン系粘着剤、スチレン−ジエンブロック共重合体系粘着剤等が挙げられ、前記加熱により容易にガス化して膨張する物質としては、例えばイソブタン、プロパン、ペンタン等が挙げられ、前記弾性を有する殻を構成する組成としては、例えば塩化ビニリデン−アクリロニトリル共重合体、ポリビニルアルコール、ポリビニルブチラール、ポリメチルメタクリレート、ポリアクリロニトリル、ポリ塩化ビニリデン、ポリスルホン等が挙げられる。   As the adhesive layer whose adhesive strength is reduced or disappeared by application of heat, for example, a thermally expandable microsphere in which a substance that easily expands by gasification by heating in an adhesive is encapsulated in an elastic shell. Examples thereof include blended adhesive resin materials. Here, examples of the pressure-sensitive adhesive include rubber-based pressure-sensitive adhesives, acrylic pressure-sensitive adhesives, vinyl alkyl ether-based pressure-sensitive adhesives, silicone-based pressure-sensitive adhesives, polyester-based pressure-sensitive adhesives, polyamide-based pressure-sensitive adhesives, urethane-based pressure-sensitive adhesives, and styrene-diene. Examples of the material that easily gasifies and expands by heating include isobutane, propane, pentane, etc., and the composition constituting the elastic shell includes, for example, chloride. Examples include vinylidene-acrylonitrile copolymer, polyvinyl alcohol, polyvinyl butyral, polymethyl methacrylate, polyacrylonitrile, polyvinylidene chloride, polysulfone and the like.

また、紫外線の照射により接着力が低下もしくは消失する接着層としては、アクリル系粘着ポリマー(例えば、アクリル酸2−エチルヘキシルおよびアクリル酸)、紫外線硬化型オリゴマー(例えばウレタンアクリエートオリゴマー)、光開始剤(例えば1-ヒドロキシシクロヘキシルフェニルケトン)などを含有させた接着性樹脂材料等が例示できる。前記接着層の厚さは、特に限定されないが、通常5〜30μm程度である。   In addition, as an adhesive layer whose adhesive strength is reduced or disappeared by irradiation with ultraviolet rays, an acrylic pressure-sensitive adhesive polymer (for example, 2-ethylhexyl acrylate and acrylic acid), an ultraviolet curable oligomer (for example, urethane acrylate oligomer), a photoinitiator Examples thereof include an adhesive resin material containing (for example, 1-hydroxycyclohexyl phenyl ketone). Although the thickness of the said adhesive layer is not specifically limited, Usually, it is about 5-30 micrometers.

上記のようにして得られたコア積層体10の上下両面上に、それぞれ配線導体と絶縁層とを交互に積層する。これにより、ガラス−樹脂板を使用することによる配線基板の全体厚みを薄くすることができないという問題がなく、薄型で高密度な配線基板を効率よく製造することができると共に、加工に伴う反りや、うねりの発生を抑制することができる。これに対し、コア積層体10の片面のみに配線導体と絶縁層とを交互に積層すると、前記効率が低下するだけでなく、配線基板に反りや、うねりが発生するおそれがある。   Wiring conductors and insulating layers are alternately laminated on the upper and lower surfaces of the core laminate 10 obtained as described above. As a result, there is no problem that the entire thickness of the wiring board cannot be reduced by using a glass-resin plate, and a thin and high-density wiring board can be efficiently manufactured, and warping and The occurrence of swell can be suppressed. On the other hand, when wiring conductors and insulating layers are alternately laminated on only one side of the core laminate 10, not only the efficiency is lowered, but also the wiring board may be warped or swelled.

具体的には、まず、図3(a)に示すように、剥離したコア積層体10の表層に位置する第1の絶縁層11および第5の絶縁層15にビアホールVHを形成する。ついで、第1の絶縁層11上に第5の配線導体25を積層し、第5の絶縁層15上に第6の配線導体26を積層する。   Specifically, first, as shown in FIG. 3A, via holes VH are formed in the first insulating layer 11 and the fifth insulating layer 15 located on the surface layer of the peeled core laminated body 10. Next, a fifth wiring conductor 25 is stacked on the first insulating layer 11, and a sixth wiring conductor 26 is stacked on the fifth insulating layer 15.

なお、絶縁層11、15のビアホールVHは、絶縁層12〜14の場合と同様のレーザ加工やフォトリソグラフィー加工等により形成される。配線導体25、26は配線導体21〜24と同様のめっき膜から成るのが好ましく、配線導体21〜24と同様のセミアディティブ法で形成するのが好ましい。また、配線導体25、26の各厚みは、第1の配線導体21で例示した厚みと同じ厚みを例示することがでる。このとき、配線導体25と26は、同時に形成することができる。したがって、本発明における配線基板の製造効率が高いものとなる。   The via holes VH in the insulating layers 11 and 15 are formed by the same laser processing, photolithography processing, or the like as in the case of the insulating layers 12 to 14. The wiring conductors 25 and 26 are preferably made of a plating film similar to that of the wiring conductors 21 to 24, and are preferably formed by a semi-additive method similar to that of the wiring conductors 21 to 24. In addition, each thickness of the wiring conductors 25 and 26 can be exemplified as the same thickness as the thickness exemplified for the first wiring conductor 21. At this time, the wiring conductors 25 and 26 can be formed simultaneously. Therefore, the manufacturing efficiency of the wiring board in the present invention is high.

次に、図3(b)に示すように、第1の絶縁層11および第5の配線導体25上に第6の絶縁層16および第7の配線導体27を形成し、第5の絶縁層15および第6の配線導体26上に第7の絶縁層17および第8の配線導体28を形成する。第6の絶縁層16と第7の絶縁層17は、他の絶縁層11〜15と同様の材料から成るのが好ましく、絶縁層11〜15の場合と同様の樹脂フィルムを、配線導体25、26が形成されたコア積層体10の上下面に貼着するとともに、該樹脂フィルムを熱硬化させることにより形成される。このとき、絶縁層16と絶縁層17は、樹脂フィルムの貼着や熱硬化等を両者同時に行うことができる。したがって、本発明における配線基板の製造効率が高いものとなる。形成された絶縁層17、18の各厚みは、第1の絶縁層11で例示した厚みと同じ厚みを例示することができる。   Next, as shown in FIG. 3B, the sixth insulating layer 16 and the seventh wiring conductor 27 are formed on the first insulating layer 11 and the fifth wiring conductor 25, and the fifth insulating layer is formed. A seventh insulating layer 17 and an eighth wiring conductor 28 are formed on the 15 and sixth wiring conductors 26. The sixth insulating layer 16 and the seventh insulating layer 17 are preferably made of the same material as the other insulating layers 11 to 15, and the same resin film as that of the insulating layers 11 to 15 is used as the wiring conductor 25, It is formed by adhering to the upper and lower surfaces of the core laminated body 10 having 26 formed thereon and thermosetting the resin film. At this time, the insulating layer 16 and the insulating layer 17 can perform both adhesion of a resin film, thermosetting, etc. simultaneously. Therefore, the manufacturing efficiency of the wiring board in the present invention is high. The thicknesses of the formed insulating layers 17 and 18 can be the same as the thicknesses exemplified for the first insulating layer 11.

絶縁層16および絶縁層17には、ビアホールVHを他の絶縁層11〜15の場合と同様の方法で形成しておく。第7の配線導体27と第8の配線導体28は、他の配線導体21〜26と同様のめっき膜から成るのが好ましく、配線導体21〜26の場合と同様のセミアディティブ法で形成するのが好ましい。また、第7の配線導体27と第8の配線導体28の各厚みは、第1の配線導体21で例示した厚みと同じ厚みを例示することができる。このとき、配線導体27と配線導体28は同時に形成することができる。したがって、本発明における配線基板の製造効率が高いものとなる。   Via holes VH are formed in the insulating layers 16 and 17 in the same manner as in the other insulating layers 11 to 15. The seventh wiring conductor 27 and the eighth wiring conductor 28 are preferably made of the same plating film as the other wiring conductors 21 to 26, and are formed by the same semi-additive method as the wiring conductors 21 to 26. Is preferred. In addition, each thickness of the seventh wiring conductor 27 and the eighth wiring conductor 28 can be exemplified by the same thickness as the thickness exemplified for the first wiring conductor 21. At this time, the wiring conductor 27 and the wiring conductor 28 can be formed simultaneously. Therefore, the manufacturing efficiency of the wiring board in the present invention is high.

最後に、図3(c)に示すように、第6の絶縁層16および第7の配線導体27上に第8の絶縁層18を形成し、第7の絶縁層17および第8の配線導体28上に第9の絶縁層19を形成する。第8および第9の絶縁層18、19は、表層の配線導体27、28の電気的な絶縁信頼性を高めるとともに、半田付け時の短絡を防止するための保護層として機能する。   Finally, as shown in FIG. 3C, an eighth insulating layer 18 is formed on the sixth insulating layer 16 and the seventh wiring conductor 27, and the seventh insulating layer 17 and the eighth wiring conductor are formed. A ninth insulating layer 19 is formed on 28. The eighth and ninth insulating layers 18 and 19 increase the electrical insulation reliability of the surface wiring conductors 27 and 28 and function as a protective layer for preventing a short circuit during soldering.

第8および第9の絶縁層18、19は、例えばアクリル変性エポキシ樹脂等の感光性樹脂と光重合開始剤等とからなる混合物にシリカやタルク等の無機絶縁性フィラーを含有させた感光性樹脂ペーストをスクリーン印刷やロールコート法により10〜30μm程度の厚みに塗布し、しかる後、フォトリソグラフィー技術を採用して所定のパターンに露光・現像した後、それを紫外線硬化および熱硬化させることにより形成される。あるいは、前記感光性樹脂ペーストを厚みが10〜30μm程度のフィルム状に加工した感光性樹脂フィルムを真空ラミネート装置により貼着した後、同様に露光・現像・硬化させることにより形成される。   The eighth and ninth insulating layers 18 and 19 are, for example, photosensitive resins in which an inorganic insulating filler such as silica or talc is contained in a mixture of a photosensitive resin such as an acrylic-modified epoxy resin and a photopolymerization initiator. Formed by applying paste to a thickness of about 10 to 30 μm by screen printing or roll coating, and then exposing and developing to a predetermined pattern using photolithography technology, followed by UV curing and heat curing Is done. Alternatively, a photosensitive resin film obtained by processing the photosensitive resin paste into a film having a thickness of about 10 to 30 μm is pasted by a vacuum laminating apparatus, and then exposed, developed and cured in the same manner.

上記のようにして、本発明の製造方法による配線基板100が完成する。この配線基板100は、厚さが200〜500μm程度であり、加工に伴う反りや、うねりの発生が抑制されているので、平坦度が高く実装性に優れる。   As described above, the wiring substrate 100 according to the manufacturing method of the present invention is completed. The wiring board 100 has a thickness of about 200 to 500 μm and suppresses the occurrence of warpage and waviness due to processing, and thus has high flatness and excellent mountability.

次に、本発明の配線基板の製造方法における他の例について、図面を参照して詳細に説明する。図4は、この例にかかるコア積層体を形成する工程を示す概略断面図であり、上記で説明した図1(d)に相当する。なお、図4においては、前述した図1〜3の構成と同一または同等な部分には同一の符号を付して説明は省略する。   Next, another example of the method for manufacturing a wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 4 is a schematic cross-sectional view showing the process of forming the core laminate according to this example, and corresponds to FIG. 1 (d) described above. In FIG. 4, the same or equivalent parts as those in FIGS.

図4に示すように、この例では、コア積層体10を形成する工程が、支持基板1の上下両面上に、それぞれ絶縁層と配線導体とを交互に積層して前記絶縁層と前記配線導体とから成るコア積層体10を形成する工程である。これにより、上記で説明した支持基板1の主面にコア積層体10を形成する場合と比較して、コア積層体10を形成する効率を約2倍に高めることができる。
ここで、支持基板1は平坦な主面(上面)を有するが、この例の場合には、支持基板1の下面も平坦、すなわち支持基板1の上下両面が平坦であるのが好ましい。
As shown in FIG. 4, in this example, the step of forming the core laminated body 10 is performed by alternately laminating insulating layers and wiring conductors on the upper and lower surfaces of the support substrate 1, respectively. Is a step of forming a core laminate 10 composed of Thereby, compared with the case where the core laminated body 10 is formed in the main surface of the support substrate 1 demonstrated above, the efficiency which forms the core laminated body 10 can be improved about 2 times.
Here, although the support substrate 1 has a flat main surface (upper surface), in this example, it is preferable that the lower surface of the support substrate 1 is also flat, that is, the upper and lower surfaces of the support substrate 1 are flat.

なお、本発明は上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば、種々の変更は可能である。例えば上述の実施の形態例では、コア積層体10を構成する絶縁層の数は5層であり、その上に積層する絶縁層の数が上下2層ずつの場合について説明したが、本発明はこれに限定されるものではなく、コア積層体10を構成する絶縁層の数やその上に積層される絶縁層の数等は配線基板に要求される仕様等に応じて適宜変更可能である。また、コア積層体10の上下面のうち、いずれの面が電子部品の搭載面側となっても良い。   Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the number of insulating layers constituting the core laminated body 10 is five, and the number of insulating layers stacked on the core laminated body 10 has been described as two upper and lower layers. However, the number of insulating layers constituting the core laminate 10 and the number of insulating layers laminated thereon can be appropriately changed according to specifications required for the wiring board. Further, any one of the upper and lower surfaces of the core laminate 10 may be the electronic component mounting surface side.

(a)〜(d)は、本発明の配線基板の製造方法にかかるコア積層体を形成する工程を示す概略断面図である。(A)-(d) is a schematic sectional drawing which shows the process of forming the core laminated body concerning the manufacturing method of the wiring board of this invention. 支持基板からコア積層体を剥離した状態を示す概略断面図である。It is a schematic sectional drawing which shows the state which peeled the core laminated body from the support substrate. (a)〜(c)は、コア積層体の上下両面に配線導体と絶縁層とを交互に積層する工程を示す概略断面図である。(A)-(c) is a schematic sectional drawing which shows the process of laminating | stacking a wiring conductor and an insulating layer alternately on the upper and lower surfaces of a core laminated body. 本発明の他の例にかかるコア積層体を形成する工程を示す概略断面図である。It is a schematic sectional drawing which shows the process of forming the core laminated body concerning the other example of this invention. 一般的なビルドアップ配線基板を示す概略断面図である。It is a schematic sectional drawing which shows a general buildup wiring board.

符号の説明Explanation of symbols

1・・・支持基板
10・・・コア積層体
11〜19・・・絶縁層
21〜28・・・配線導体
100・・・配線基板
DESCRIPTION OF SYMBOLS 1 ... Support substrate 10 ... Core laminated body 11-19 ... Insulating layer 21-28 ... Wiring conductor 100 ... Wiring board

Claims (5)

支持基板の主面上に絶縁層と配線導体とを交互に積層して前記絶縁層と前記配線導体とから成るコア積層体を形成する工程と、
前記支持基板から前記コア積層体を剥離する工程と、
剥離した前記コア積層体の上下両面上に、それぞれ配線導体と絶縁層とを交互に積層する工程とを含むことを特徴とする配線基板の製造方法。
A step of alternately laminating insulating layers and wiring conductors on the main surface of the support substrate to form a core laminate composed of the insulating layers and the wiring conductors;
Peeling the core laminate from the support substrate;
And a step of alternately laminating a wiring conductor and an insulating layer on both upper and lower surfaces of the peeled core laminate.
前記支持基板の主面が平坦である請求項1記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 1, wherein a main surface of the support substrate is flat. 前記配線導体がセミアディティブ法で形成される請求項1または2記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 1, wherein the wiring conductor is formed by a semi-additive method. 前記コア積層体を形成する工程は、前記支持基板とコア積層体との間に所定の接着層を介在させる工程を含み、
前記支持基板から前記コア積層体を剥離する工程は、前記接着層の接着力を低下もしくは消失させた後、前記支持基板から前記コア積層体を剥離する工程である請求項1〜3のいずれかに記載の配線基板の製造方法。
The step of forming the core laminate includes a step of interposing a predetermined adhesive layer between the support substrate and the core laminate,
The process of peeling the said core laminated body from the said support substrate is a process of peeling the said core laminated body from the said support substrate, after reducing or lose | eliminating the adhesive force of the said contact bonding layer. The manufacturing method of the wiring board as described in 2 ..
前記コア積層体を形成する工程が、前記支持基板の上下両面上に、それぞれ絶縁層と配線導体とを交互に積層して前記絶縁層と前記配線導体とから成るコア積層体を形成する工程である請求項1〜4のいずれかに記載の配線基板の製造方法。
The step of forming the core laminate is a step of forming a core laminate comprising the insulating layer and the wiring conductor by alternately laminating insulating layers and wiring conductors on the upper and lower surfaces of the support substrate. The manufacturing method of the wiring board in any one of Claims 1-4.
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