JP2007164472A - Arithmetic device with queuing mechanism - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic device locally performing queuing of a plurality of pieces of data input to each processor element, and not requiring consideration about synchronization of the data in time of programming. <P>SOLUTION: This arithmetic device has one or more first processor elements, one or more second processor elements, and a queuing means. The queuing means has: a payload holding holding the data output by the first processor elements; and a flag corresponding to the payload, and showing an effective state or an ineffective state of the corresponding payload. The flag comes into the effective state when the first processor element writes the data into the corresponding payload, and comes into the ineffective state when all the second processor elements with the data as input reads the data from the payload. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an arithmetic unit having a waiting mechanism between processor elements or between functional blocks constituting each stage of a pipeline.

  In Patent Literature 1, a plurality of processor elements (Processor Elements: hereinafter referred to as PEs) are arranged in a matrix, and the operation contents in each PE and the connection between the PEs are changed by a program. An arithmetic unit that realizes data processing is described.

  FIG. 8 is a diagram illustrating the arithmetic device described in Patent Document 1. In FIG. 8, PE 72 and PE 73 perform multiplication of values input to inputs 61 and 62, respectively, PE 71 is programmed to perform addition of values input to inputs 61 and 62, and The output is programmed to connect to the input 61 of PE 71 and the output of PE 73 to the input 62 of PE 71. That is, the value inputted to the input 61 of the PE 72 is a, the value inputted to the input 62 of the PE 72 is b, the value inputted to the input 61 of the PE 73 is c, and the value inputted to the input 62 of the PE 73. If d is d, the output of PE 71 is a * b + c * d.

  In FIG. 8, values “3”, “5”, and “7” are sequentially input to the input 61 of the PE 72, and values “2”, “4”, and “1” are sequentially input to the input 62 of the PE 72. The values “1”, “4”, and “4” are sequentially input to the input 61 of the data, the values “3”, “3”, and “1” are sequentially input to the input 62 of the PE 73. “9”, “32”, and “11” are sequentially output.

  In the arithmetic device described in Patent Document 1, it is necessary to perform synchronous control on the timing between a plurality of data input to each PE. For example, in FIG. 8, it is necessary to control so that the value “4” is input to the input 62 while the value “5” is input to the input 61 of the PE 72, and the value “20” is input to the input 61 of the PE 71. It is necessary to control the arithmetic unit so that the value “12” is input to the input 62 while “” is being input. Without this synchronous control, the arithmetic unit does not operate correctly.

  Patent Document 1 does not describe the configuration of this synchronization control. However, the synchronization control in the entire arithmetic device complicates the configuration of the arithmetic device, and the burden on the programmer becomes heavy when the synchronization is ensured by programming.

  There is a similar problem in the RISC processor pipeline. FIG. 9 is a diagram showing the pipeline structure of the RISC processor. According to FIG. 9, in the RISC processor, an instruction fetch unit 81, an instruction decode unit 82, an instruction execution unit 83, and a write back unit 84 constitute a 4-stage pipeline. In an ideal pipeline configuration, each instruction that enters the pipeline is executed sequentially as a flow work, but in reality, it is executed by various hazards such as data hazards and control hazards, or instruction execution. It is necessary to stall due to the presence of an instruction that requires several stages. A stall is a functional block that constitutes a pipeline stage, that is, in the example of FIG. 9, an instruction that has finished processing in any of the instruction fetch unit 81, instruction decode unit 82, instruction execution unit 83, and write back unit 84 However, the process waits until the next functional block can be processed without proceeding to the next functional block. For example, even if the decoding of a certain instruction ends in the instruction decoding unit 82, This occurs when the instruction execution unit 83 does not finish executing the instruction.

  For this reason, the RISC processor includes a pipeline control unit 9, and performs a stall, that is, a standby instruction for processing, to each unit based on the processing status of each unit.

JP 2001-314881 A

  As described above, in the arithmetic device of Patent Document 1, the synchronization control in the entire arithmetic device complicates the configuration of the arithmetic device, and the burden on the programmer becomes heavy when synchronization is guaranteed by programming.

  Further, in the pipeline structure shown in FIG. 9, for example, when a design change involving a change in the number of pipeline stages, such as a plurality of instruction execution units 93, is performed, the entire processor including the pipeline control unit 9 is designed. There is a problem that changes are required.

  Accordingly, an object of the present invention is to provide an arithmetic device that waits for a plurality of data input to each PE with a simple configuration and does not need to consider data synchronization when programming.

  Another object of the present invention is to provide an arithmetic unit having a pipeline configuration that does not require a pipeline control unit for managing and controlling the whole in order to facilitate design changes of the arithmetic unit.

According to the arithmetic device of the present invention,
An arithmetic device having one or more first processor elements, one or more second processor elements, and a waiting means, wherein the waiting means holds data output from each of the first processor elements. A payload field and a flag field corresponding to the payload field and indicating a valid state or invalid state of the corresponding payload field, and the flag field when the first processor element writes data to the corresponding payload field All the second processor elements that are in the valid state and input the data are in the invalid state when the data is read from the payload field.

According to another embodiment of the arithmetic device of the present invention,
The first processor element also preferably writes new data to the corresponding payload field only when the flag field is in an invalid state.

According to another embodiment of the arithmetic device of the present invention,
The flag field corresponds to the second processor element, and includes a flag indicating whether or not the corresponding second processor element has read the data in the payload field. The second processor element holds data to be input. It is also preferable to read out the input data only when all of the flags corresponding to the flag field corresponding to the payload field being read indicate that the data has not been read out.

Furthermore, according to another embodiment of the arithmetic unit of the present invention,
Each input of the second processor element is provided with a FIFO buffer that holds one or more data, and the newly written data in the payload field is all the second processors that receive the data at the same time. Is output to the FIFO buffer of the element. The FIFO buffer sets the full flag valid when the stored data reaches its capacity, otherwise invalid, and the first processor element outputs the data to be output. It is also preferable to write new data into the payload field only when all the input FIFO buffers have the full flag disabled.

Furthermore, according to another embodiment of the arithmetic unit of the present invention,
An arithmetic unit having a queuing unit between each stage constituting a pipeline, wherein the queuing unit determines a payload field that holds an instruction or data that is an output of each stage, and a valid state or invalid state of the payload field. The flag field becomes valid when an instruction or data is written in the payload field, becomes invalid when an instruction or data is read from the payload field, and each stage has a flag field. The command or data is written to the payload field of the waiting means downstream only when the flag is invalid, and the command or data is read from the payload field of the waiting means upstream only when the flag field is valid. .

  Synchronize input data to each processor element with a simple configuration of local control between processor elements that input and output data, without performing synchronization control of the entire arithmetic unit or programming that is conscious of input data synchronization Can be realized. Further, by providing a FIFO buffer at the input of each processor element, it is possible to reduce the cycle in which the processor element located upstream writes data to the waiting means.

  An arithmetic unit having a pipeline configuration eliminates the need for a pipeline control unit, and stall control between each stage is performed locally independently, so even if the number of pipeline stages is increased or decreased There is an advantage that it can be dealt with by a design change.

  The best mode for carrying out the present invention will be described in detail below with reference to the drawings.

  FIG. 1 is a diagram showing a connection configuration between PEs included in an arithmetic device according to the present invention. The operation content of the PE in FIG. 1 is defined by a program. According to FIG. 1, each PE does not acquire its input directly from another PE, but always acquires it via the queuing unit 5. That is, the PEs 10, 20, and 30 write the output data to the waiting unit 5, and the PEs 11, 21, and 31 read the input data from the waiting unit 5 and acquire it. In addition, the number of rows and the number of columns of PE are merely examples, and the present invention can be applied to any number of rows of 1 or more and any number of columns of 2 or more.

  FIG. 2 is a diagram illustrating a configuration of the meeting unit 5. The queuing unit 5 has n registers denoted by reference numerals 51 to 5n, and each register includes a connection flag field, a status flag field, and a payload field. The PE that writes data to each register is determined by a program or by a hardware configuration. Further, the PE for reading data from each register is determined by a program.

  Each of the connection flag fields of the registers 51 to 5n is composed of a plurality of bits corresponding to the PE from which data is read. For example, “1” is set in the bit corresponding to the PE that actually needs to read data. , “0” is set to the bits corresponding to the other PEs. The PE that actually needs to read data is determined according to the program, and is written in the connection field as an initial setting when the program is executed.

  The payload fields of the registers 51 to 5n have an arbitrary bit length and hold data input / output between PEs. Each of the status flag fields includes a plurality of bits corresponding to the PE from which data is read. For example, when data is written in the payload field, all bits are set to “1”. Further, when data is read from the payload field, the bit position corresponding to the PE from which the data has been read is controlled to be “0”.

  The PE that reads data indicates that the input data is set in the payload field when the bit corresponding to itself in the status flag field is “1”, and indicates that the payload is “0”. Recognize that the input data is not yet set in the field. Setting or changing the value of the status flag field can be performed by a PE that reads and writes data, or can be configured by a control unit of the queuing unit 5 (not shown). In addition, the logical product of the bits corresponding to the same processor element in the connection flag field and the status flag field is all “0”, which means that all the PEs using the written data as input are data. Means that the data has been read. Therefore, the PE that writes data in the payload field is a new data payload field only when the logical product of the bits corresponding to the same PE in the connection flag field and the status flag field is all "0". Write to.

  The operation for inputting / outputting data between PEs will be specifically described with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing a data input / output relationship between PEs used for explanation. According to FIG. 3, the data output from the PE 10 is written to the register 51 of the waiting unit 5 and is input to the PEs 11 and 21, and the data output from the PE 20 is written to the register 52 of the waiting unit 5 and stored in the PEs 11 and 31. Data that is input and output from the PE 30 is written in the register 53 of the queuing unit 5 and is input to the PEs 21 and 31.

  FIG. 4 is a diagram for explaining the transition of the connection flag field and the status flag field of the queuing unit 5 in the input / output relationship of FIG. As shown in FIG. 3, the PE 10 writes to the register 51 in FIG. 4, the PE 20 writes to the register 52, and the PE 30 writes to the register 53. The left 3 bits of each register is a connection flag field, the right 3 bits are a status flag field, the first bit of the connection flag field and the status flag field corresponds to PE11, and the second bit corresponds to PE21. The third bit corresponds to PE31.

  4A to 4D, the first, second, and third bits of the connection flag field of the register 51 are “1”, “1”, and “0”, respectively. Corresponds to the input of PE11 and PE21. Similarly, the first, second, and third bits of the connection flag field of the register 52 are “1”, “0”, and “1”, respectively. This indicates that the data output by the PE 20 is the input of the PEs 11 and 31. The first, second, and third bits of the connection flag field of the register 53 are “0”, “1”, and “1”, respectively. And 31 are input.

  First, it is assumed that each of the PEs 10, 20, and 30 has written output data to the corresponding register of the waiting unit 5. FIG. 4A shows the state of each register at that time, and all bits in all the status flag fields are set to “1”.

  From which register each of the PEs 11, 21, and 31 reads data is determined by a program. That is, PE11 reads data from registers 51 and 52, PE21 reads data from registers 51 and 53, and PE31 reads data from registers 52 and 53. For example, PE11 stores data in register 53. Unlike this, the PE itself can be recognized by the value of the connection flag field.

  FIG. 4B shows the state of each register when the PE 11 reads data from the registers 51 and 52 and the PE 21 reads data from the registers 51 and 53. As shown in FIG. 4B, when the PE 11 reads data from the registers 51 and 52, the first bit corresponding to the PE 11 in the status flag field of the registers 51 and 52 is changed to “0”, and the PE 21 is set in the register. By reading data from 51 and 53, the second bit corresponding to PE21 in the status flag field of the registers 51 and 53 is changed to “0”.

  In the state shown in FIG. 4B, the logical product of the same bit positions of the connection flag field and the state flag field of the register 51 is “0” for all bits. This is because the data output from the PE 10 is input. This means that all the PEs to be executed, that is, the PEs 11 and 21 have read the data, and therefore the PE 10 can write new data to the register 51.

  On the other hand, the logical product of the same bit positions in the connection flag field and the status flag field of the registers 52 and 53 is not “0” for all bits, and this is the value of the processor element that receives the data output from PE20 and PE30. This means that the data has not yet been read out, and therefore the PEs 20 and 30 cannot write new data into the registers 52 and 53.

  FIG. 4C shows the state of each register when the PE 10 writes new data to the register 51 and the PE 31 reads data from the registers 52 and 53. As shown in FIG. 4C, when the PE 10 writes data to the register 51, all the status flag fields of the register 51 become “1”, and when the PE 31 reads data from the registers 52 and 53, the register The third bit corresponding to PE31 in the status flag fields 52 and 53 is changed to “0”.

  In the state of FIG. 4C, the logical product of the same bit positions of the connection flag field and the status flag field of the registers 52 and 53 becomes “0” for all bits. New data can be written to 53. In PE11, since the first bits corresponding to the registers 51 and 52 are “1” and “0”, respectively, data is already set in the register 51, but the register 52 has Recognizing that data has not been set yet, that is, data necessary for processing is not prepared, and therefore it is recognized that data cannot be read out.

  FIG. 4D shows the state of each register when the PEs 20 and 30 write new data into the registers 52 and 53. As shown in FIG. 4D, the PEs 20 and 30 write data in the registers 52 and 53, respectively, and the status flag fields of the registers 52 and 53 are all “1”.

  In the state of FIG. 4D, since the logical product of the same bit positions of the connection flag field and the status flag field of the registers 51 to 53 does not become “0” for all bits, the PEs 10, 20 and 30 have new data. Cannot be written. In addition, regarding the reading of data of PEs 11, 21, and 31, since all the bits corresponding to the state flag field of each register to be read are “1”, PEs 11, 21, and 31 can read the data. Recognize that.

  FIG. 5 is a state transition diagram of each register of the waiting unit 5. In FIG. 5, the invalid state is a case where the logical product of the bit positions corresponding to the same PE in the connection flag field and the state flag field is all “0”, and the upstream PE, that is, the PE to be written to the register. Can write new data to the payload field only in the invalid state, and transition to the valid state by writing. While in the valid state, the upstream PE cannot write new data into the payload field.

  When it is in the valid state, every time the PE that is downstream, that is, the PE that reads from the register, reads the data, the corresponding bit position of the status flag field is changed to “0”, and the connection flag field and the status flag field When the logical product of the bit positions corresponding to the same PE of all becomes “0”, that is, when all the downstream PEs that use data as input read out the data. Transition to.

  As described above, synchronization of input data to each PE can be achieved with a simple configuration of local control between PEs that input and output data without performing synchronization control of the entire device or programming that is conscious of synchronization of input data. realizable.

  In the queuing unit 5 described above, a connection flag field is provided to indicate a PE from which data is read. When data is written, all the status flag fields are set to “1”, but a connection flag field is provided. Instead, when data is written, the configuration may be such that “1” is set only to the bit corresponding to the PE from which the data in the status flag field is read. Regardless of the configuration, the data in one register is branched as input data to a plurality of PEs by managing the read state of the PE that reads data by each bit in the connection flag field and / or the status flag field. Can be made.

  In addition, when the data output by the PE is not input to two or more PEs, that is, in the configuration of one PE, the connection flag field is not necessary, and only one bit of the status flag field may be provided.

  In the configuration shown in FIG. 3, for example, when the PE 10 writes data in a certain cycle, the PEs 11 and 21 can read the data in the next cycle, but the PE 10 cannot write the data. Therefore, the PE 10 can only write data at a rate of once every two cycles. For this reason, a FIFO buffer is arranged at each input portion of each PE.

  FIG. 6 is a configuration diagram in which a FIFO buffer is arranged, and only the portions related to PEs 10, 11 and 21 in FIG. 3 are displayed.

  According to FIG. 6, the PE 11 acquires input data from the FIFO buffer 110, and the PE 21 acquires input data from the FIFO buffer 210. The FIFO buffer 110 and the FIFO buffer 210 can hold one or more data, and when data output is possible, the output enable flags 111 and 211 are set to be valid. When the output enable flags of all the FIFO buffers corresponding to the inputs necessary for the calculation are set to be valid, the PEs 11 and 21 read the data from the FIFO buffer and start the calculation.

  When the PE 10 writes data to the register 51, the written data is simultaneously output to the FIFO buffers 110 and 210. Note that the connection flag field and / or the status flag field of the register 51 have the same configuration as described above, and by outputting data to the FIFO buffer, the corresponding bit of the status flag field is changed to “0”. The

  The FIFO buffers 110 and 210 respectively set the FULL flags 111 and 211 to be valid when the stored value reaches its capacity and new input becomes impossible, respectively. If it is possible, the FULL flags 111 and 211 are set invalid.

  The PE 10 writes data to the register 51 only when the FULL flag of all the FIFO buffers that receive the data output from the PE 10 is invalid.

  As described above, by providing the FIFO buffers 111 and 211 at the inputs of the PEs 11 and 21, it is possible to reduce the cycle in which the upstream PE 10 writes data to the waiting unit 5.

  Next, another embodiment of the arithmetic device according to the present invention will be described with reference to FIG. According to FIG. 7, the queuing unit 4 is inserted between the instruction fetch unit 81, the instruction decode unit 82, the instruction execution unit 83, and the write back unit 84 that constitute each stage of the pipeline. Although the description will be made using a four-stage pipeline configuration, the number of stages is an example, and the present invention can be applied to a pipeline having an arbitrary number of stages.

  Since the pipeline configuration is equivalent to the case where the number of rows is 1 in the arithmetic unit shown in FIG. 1, the queuing unit 4 of this embodiment omits the connection flag field of the queuing unit 5 shown in FIG. The status flag field may be one bit. Hereinafter, a state in which the value “1” is set in the state flag field is referred to as a valid state, and a state in which the value “0” is set is referred to as an invalid state.

  Each functional block constituting the pipeline receives the processing result, for example, the fetched instruction for the instruction fetch unit 81, the decoded instruction for the instruction decode unit 82, and the execution result data for the instruction execution unit 83. The data is written in the payload field of the waiting unit 4 downstream, and the state flag field of the waiting unit 4 is set to the valid state by writing. Each functional block recognizes that the processing in the upstream stage has ended by the status flag field of the queuing unit 4 upstream is valid, and only when the queuing unit 4 is in the valid state. A command or data is read from the payload field and processing is started. Further, the status flag field of the queuing unit 4 is set to an invalid state when an instruction or data is read from the corresponding payload field. Each functional block constituting the pipeline can write data or an instruction into the payload field only when the status flag field of the downstream waiting unit 4 is invalid.

For example, in the arithmetic unit shown in FIG.
add R0, # 1, R1
Think about performing. Here, add is an unsigned addition instruction, and the above operation indicates that the value stored in the register R0 and the immediate value “1” are added and the result is stored in the register R1.

  First, the instruction fetch unit 81 fetches an instruction from an instruction memory (not shown) and writes the fetched instruction in the payload field of the waiting unit 4 when the downstream waiting unit 4 is in an invalid state. Although the status flag field of the queuing unit 4 is set to the valid state by writing, the instruction fetch unit 81 or the queuing unit 4 itself may set the valid state.

  The decoding unit 82 decodes the instruction in the payload field because the status flag field of the queuing unit 4 located upstream is valid. As a result, the status flag field of the queuing unit 4 located upstream is set to an invalid state, but the decoding unit 82 or the queuing unit 4 itself may set the invalid state. Further, when the downstream waiting unit 4 is in an invalid state, the decoding unit 82 writes the decoding result in the payload field of the waiting unit 4. If it is in the valid state, it waits until it becomes invalid and writes the decoding result after it becomes invalid. By writing, the status flag field of the waiting unit 4 becomes valid. Here, in this example, the decoding result includes the microcode for causing the instruction execution unit 83 to perform addition, the value held by the register R0, the immediate value “1”, and the register R1 for storing the operation result. The value to specify.

  The instruction execution unit 83 sets itself to an addition operation based on the microcode stored in the payload field of the queuing unit 4 located upstream because the status flag field of the queuing unit 4 located upstream becomes valid. Subsequently, the value stored in the payload field of the waiting unit 4 located upstream is added. Finally, when the downstream queuing unit 4 is in an invalid state, the instruction execution unit 83 obtains the result of addition and a value specifying the register R1 stored in the payload field of the upstream queuing unit 4 , And writes in the payload field of the waiting unit 4 downstream. By writing from the instruction execution unit 83, the status flag field of the waiting unit 4 becomes valid.

  Since the status flag field of the upstream queuing unit 4 becomes valid, the write-back unit 84 also specifies the value of the addition result stored in the payload field of the upstream queuing unit 4 in the same payload field. Stored in the register R1.

  The above configuration eliminates the need for a pipeline control unit, and stall control between each functional block is performed locally independently, so even if the number of pipeline stages is increased or decreased, local design changes are possible. There is an advantage that it can cope.

  Note that the values written in the connection flag field and the status flag field of the queuing unit 4 or 5 in the above description, that is, “1” or “0” are examples and are not limited to the values used in the description.

It is a figure which shows the connection structure between processor elements which the arithmetic unit by this invention has. It is a figure which shows the structure of a waiting part. It is a figure which shows the data input / output relationship between processor elements. It is a figure explaining the transition of the connection flag field and state flag field of the waiting part in the input / output relationship of FIG. It is a state transition diagram of each register of the queuing unit. It is the block diagram which has arrange | positioned FIFO buffer. It is a figure which shows the pipeline structure which the arithmetic unit by this invention has. It is a figure explaining the arithmetic unit by a prior art. It is a figure explaining the pipeline structure by a prior art.

Explanation of symbols

10, 20, 30, 11, 21, 31, 71, 72, 73 Processor element 4, 5 Waiting section 9 Pipeline control section 51, 52, 53, 5n Register 61, 62 Input 81 Instruction fetch section 82 Instruction decoding section 83 Instruction execution unit 84 Write back unit 110, 210 FIFO buffer 111, 211 Output enable flag 112, 212 FULL flag

Claims (5)

An arithmetic device having one or more first processor elements, one or more second processor elements, and a waiting means,
The queuing means has a payload field that holds data output by each of the first processor elements, and a flag field that corresponds to the payload field and indicates a valid state or invalid state of the corresponding payload field,
The flag field becomes valid when the first processor element writes data to the corresponding payload field, and all the second processor elements that receive the data read data from the payload field. To become invalid,
An arithmetic unit characterized by the above. The first processor element writes new data to the corresponding payload field only when the flag field is invalid;
The arithmetic unit according to claim 1, wherein: The flag field corresponds to the second processor element, and includes a flag indicating whether or not the corresponding second processor element has read the data in the payload field.
The second processor element inputs only when all the flags corresponding to itself in the flag field corresponding to the payload field holding the input data indicate that the data is not read out. To read the data
The arithmetic unit according to claim 2, wherein: Each input of the second processor element is provided with a FIFO buffer that holds one or more data, and the newly written data in the payload field is all the second processors that receive the data at the same time. Output to the FIFO buffer of the element,
The FIFO buffer enables the full flag when the stored data reaches its capacity, and disables it otherwise.
The first processor element writes new data to the payload field only when all FIFO buffers that receive output data have the full flag disabled.
The arithmetic unit according to claim 1, wherein: An arithmetic unit having a waiting means between each stage constituting a pipeline,
The queuing means has a payload field that holds an instruction or data that is an output of each stage, and a flag field that indicates a valid state or invalid state of the payload field, and the instruction or data is written to the payload field in the flag field. Becomes invalid when an instruction or data is read from the payload field,
Each stage writes an instruction or data into the payload field of the queuing means downstream only when the flag field is in an invalid state, and writes an instruction or data from the payload field of the queuing means upstream only when the flag field is valid. Reading,
An arithmetic unit characterized by the above.

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