JP2007156557A - Parallel processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the using efficiency of the instruction memory of parallel processors which allows a plurality of processors to operate in parallel according to an extended instruction. <P>SOLUTION: An operation mode and instruction length are designated by a branch instruction, and an instruction fetch/instruction data supply unit 500 is controlled based on the operation mode information and the instruction length information so that when a core processor 200 operates, it is not necessary to embed any non-operation(NOP) instruction to non-operating core processor #1(300) and/or core processor #2(400) in an instruction memory 100, and that even when a processor 1 is put in a parallel operation mode, it is not necessary to embed the NOP instruction to the non-parallel operating core processor #1(300) and/or core processor #2(400) in the instruction memory 100. Furthermore, it is possible to improve the using efficiency of the instruction memory 100 by selecting the instruction of instruction length capable of designating the parallel operation of the core processor #1(300) and/or core processor #2(400) in a range necessary for processing under an extended instruction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a parallel processor in which a plurality of processors are operated in parallel by an extension instruction. In particular, the present invention relates to a technique for improving instruction memory utilization efficiency for instructions in a processing mode by a single processor operation and a processing mode by a parallel operation of a plurality of processors.

  In recent years, high performance has been achieved by incorporating a processor in an electronic device. However, since the processing capability required for such an electronic device is increasing year by year, the processing capability of the embedded processor itself is also increasing year by year. Has come to be required. For this reason, techniques such as a superscalar architecture that improves instruction level parallelism (ILP) and a very long instruction word (VLIW) architecture are adopted for recent embedded processors. There is something that is.

  On the other hand, on the device side where the embedded processor is mounted, it is required to reduce the cost of the device and reduce the power consumption of the device. For this reason, when the superscalar architecture is adopted for the embedded processor, a mechanism for checking the dependency relation of instructions at the time of instruction execution and a mechanism for dynamically controlling the execution order are required. There is a problem that the size is increased, the cost is increased, and the power consumption is increased. Further, when the VLIW architecture is adopted for the embedded processor, it is necessary to arrange a no operation (NOP) instruction that does not perform data processing or the like in the corresponding instruction slot when there is no instruction to be executed simultaneously in parallel. For this reason, there is a problem in that the use efficiency of the instruction memory is lowered.

  On the other hand, a processor technology of the VLIW architecture in which instruction delimiter information is provided and the instruction memory is variable length to improve the use efficiency of the instruction memory is known (see, for example, Patent Document 1).

Further, a technique for improving the use efficiency of the instruction memory by providing an operation mode in the processor of the VLIW architecture so that the NOP instruction for the other processor that does not perform the instruction processing is not arranged in the instruction memory in the mode in which the single processor operates. (For example, refer to Patent Document 2).
JP 2001-100997 A (page 3-4, FIG. 3) Japanese Patent No. 3616556 (page 4-11, FIG. 3)

  However, the method of adding instruction delimiter information to each instruction disclosed in Patent Document 1 has a problem that the use efficiency of the instruction memory is lowered because information other than the processing instruction is arranged in the instruction memory. Further, the parallel processor disclosed in Patent Document 2 can improve instruction use efficiency by eliminating the need for NOP instructions for other processors in a mode in which a single processor operates. However, a parallel processor that incorporates multiple types of processors suitable for processing applications and operates them in parallel as appropriate to reduce power consumption and improve processing performance. When a parallel operation is instructed, a NOP instruction is required for a processor that is not operated, and there is a problem in that the use efficiency of the instruction memory is reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a parallel processor having a high instruction memory utilization efficiency by providing an operation mode and changing the instruction length of an extended instruction in the VLIW operation mode. And

   In order to achieve the above object, a parallel processor of the present invention is a parallel processor that includes at least a first processor and a second processor and pipelines instructions executed in each processor in parallel in the same cycle, A first instruction execution unit and an instruction fetch supply unit provided in the first processor; a second instruction execution unit provided in the second processor; the first instruction execution unit and / or the second An instruction memory for storing instructions to be executed by the instruction execution unit, wherein the instruction fetch supply unit includes counter means for designating an address for reading the instructions from the instruction memory, and the instructions read from the instruction memory Instruction buffer means for holding the first instruction execution unit and the second instruction in response to a read operation of the instruction memory. A first operation mode for operating the execution unit; an operation mode control means for outputting control information for the second operation mode for operating the second instruction execution unit; and a NOP instruction for generating a NOP instruction having a predetermined bit length Based on the control information of the operation mode from the generation unit and the operation mode control unit, in the case of the first operation mode, a part of the instruction from the instruction buffer unit is sent to the first instruction execution unit. And an instruction consisting of the remaining part of the instruction and the NOP instruction from the NOP instruction generation means to the second instruction execution unit. And in the second operation mode, an instruction supply means for supplying a part or all of the instructions from the instruction buffer means to the second instruction execution section. The features.

  According to the present invention, in a parallel processor in which a plurality of processors are operated in parallel by an extension instruction, it is not necessary to embed a no-operation (NOP) instruction to be supplied to a processor that is not operated in the instruction memory, and an extension instruction during parallel operation In the processing of functions that require high processing performance by making the instruction length variable, multiple processors can operate in parallel, and in other functions, instructions that operate as many processors as necessary in parallel By selecting a long instruction and describing a program, it is possible to provide a parallel processor with high instruction memory utilization efficiency.

  Examples of the present invention will be described below.

  A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram of a processor incorporating a parallel processor according to the first embodiment. FIG. 2 is a diagram showing an instruction format of an “extended instruction” for operating the parallel processor. FIG. 3 is a diagram illustrating an instruction sequence including an “extended instruction”. FIG. 4 is a diagram showing a state of arrangement of “extension instructions” on the instruction memory. FIG. 5 is a diagram showing a stage configuration of the pipeline processor. FIG. 6 is a block diagram showing the configuration of the instruction fetch / instruction supply unit.

  The processor 1 shown in FIG. 1 is a parallel processor that includes an instruction memory 100 and includes, for example, a core processor 200, a coprocessor # 1 (300), and a coprocessor # 2 (400). Then, the core operation mode in which the core processor 200 operates alone, and the VLIW (parallel) in which the core processor 200 and the coprocessor # 1 (300) and / or the coprocessor # 2 (400) operate as one VLIW processor. ) It has an operation mode.

  The instruction memory 100 includes “basic instructions” that are decoded and executed by the core processor 200 and “extended instructions” that are decoded and executed by the core processor 200 and the coprocessor # 1 (300) and / or the coprocessor # 2 (400). Stored (object) program. Although not shown, the program is appropriately loaded into the instruction memory 100 from an external storage device connected to the processor 1.

  The core processor 200 outputs the memory address of the next instruction to be executed to the instruction memory 100 to read (fetch) the instruction, and read the read instruction to the core processor 200 and the coprocessor # 1 (300) and / or the coprocessor # 2. An instruction fetch / instruction data supply unit 500 to be supplied to (400), a control information storage unit 600 for storing operation control information of the instruction fetch / instruction data supply unit 500, and a decode execution unit 700 for decoding and executing the read instruction. Is a pipeline processor consisting of

  The instruction fetch / instruction data supply unit 500 generates or selects a memory address of an instruction to be executed next, outputs it to the instruction memory 100, and reads the instruction. At this time, if the control information from the control information storage unit 600 is the core operation mode, the instruction read from the instruction memory 100 is the “basic instruction”, and the “basic instruction” is supplied to the decode execution unit 700 of the core processor 200. .

  If the control information from the control information storage unit 600 is the parallel operation mode, the instruction of the size (length) specified by the control information read from the instruction memory 100 is an “extended instruction”. The instruction based on the contents of the instruction field (co-pro) for the coprocessor of “instruction” is supplied to the decode execution unit 710 of the coprocessor # 1 (300) and / or the decode execution unit 720 of the coprocessor # 2 (400). At the same time, if the “extended instruction” includes an instruction field (core) for the core processor 200, an instruction based on the contents of the instruction field is supplied to the decode execution unit 700 of the core processor 200.

  The control information storage unit 600 is executed by the operation mode of the processor 1 set by the instruction executed by the decode execution unit 700, the core processor 200, the coprocessor # 1 (300), and / or # 2 (400). Control information of the instruction length of the extended instruction is stored, and the control information is output to the instruction fetch / instruction data supply unit 500 in the instruction read operation of the processor 1. The stored contents of the control information storage unit 600 are initialized by power-on, reset signal, etc., and the control information of the core operation mode for reading and executing the basic instruction is output. However, the stored contents by the interrupt processing based on the interrupt signal etc. Is initialized, the storage contents of the control information storage unit 600 are stored in a specific storage unit (not shown) so that the process can be returned from the interrupt process.

  The decode execution unit 700 decodes and executes the instruction supplied from the instruction fetch / instruction data supply unit 500. This instruction includes an instruction of a general embedded processor, and the decode execution unit 700 reads / writes data from / to a data port or data memory provided in the processor 1, data arithmetic processing, etc. I do. In addition to this, reading and writing are performed with respect to the storage unit such as various registers and flags for controlling the program processing order and processing state of the processor 1.

  The decode execution unit 710 of the coprocessor # 1 (300) and the decode execution unit 720 of the coprocessor # 2 (400) decode and execute an instruction supplied from the instruction fetch / instruction data supply unit 500 of the core processor 200. With such a configuration, the processor 1 executes specific data processing suitable for the application of the device on which the processor 1 is mounted (for example, to realize data processing at high speed, high accuracy, and low power consumption). The processor is realized (using a coprocessor having a simple circuit).

  Although not shown, the coprocessor # 1 (300) and / or # 2 (400) outputs a signal such as an interrupt to the core processor 200, and also from the core processor 200 to the coprocessor # 1 (300) and / or #. 2 (400) is connected by a bus capable of inputting / outputting data to / from a register or the like. In the following description, it is assumed that each coprocessor reads and operates a 32-bit instruction.

  The instruction format of the “extended instruction” stored in the instruction memory 100 shown in FIG. 2 includes a type having a different instruction length and a type having a different instruction field configuration. For example, the instruction F1a (800) and the instruction F2a (810) are extended instruction formats having an instruction length of 32 bits. The instruction F1b (820) and the instruction F2b (830) are extended instruction formats having an instruction length of 64 bits.

  Further, the extended instruction format of the instruction F1a (800) and the instruction F1b (820) includes a “core” instruction field and a “co-pro” instruction field, and the core processor 200 decodes the “core” instruction field. The instruction to be executed is set. As a result, the core processor 200 and the coprocessors # 1 (300) and / or # 2 (400) can simultaneously perform data processing and the like.

  On the other hand, the extended instruction format of the instruction F2a (810) and the instruction F2b (830) includes only a “co-pro” instruction field, and the decoding execution unit 710 of the coprocessor # 1 (300) and / or An instruction to be decoded and executed by the decode execution unit 720 of the coprocessor # 2 (400) is set.

  Next, a detailed configuration of the instruction fetch / instruction data supply unit 500 shown in FIG. 6 will be described. Instruction fetch / instruction data supply unit 500 includes program counter 510, memory request control unit 520, instruction buffer 530, instruction data supply unit 540, NOP instruction generation circuit 550, instruction length / operation mode control circuit 560, addition circuit 570, selection A circuit 580 and the like are included.

  Program counter 510 stores the address of the instruction to be read next by processor 1 and outputs the read address to instruction memory 100 and addition circuit 570. The memory request control unit 520 outputs an instruction fetch request to the instruction memory 100 in the instruction fetch operation of the processor 1. In the instruction fetch operation of the processor 1, although the control unit and signals are not shown, the instruction buffer 530 inputs an instruction read from the instruction memory 100, and the program counter 510 reads the output of the selection circuit 580 next. As input. The instruction buffer 530 holds the instruction read from the instruction memory 100 and outputs it to the instruction data supply unit 540. The NOP instruction generation circuit 550 outputs the generated NOP instruction to the instruction data supply unit 540.

  The instruction data supply unit 540 outputs the instruction input from the instruction buffer 530 and / or the NOP instruction from the NOP instruction generation circuit 550 to the core processor 200, coprocessor # 1 (300) and / or # 2 (400). The instruction length / operation mode control circuit 560 controls the instruction length and operation mode of the instruction data supply unit 540 based on an instruction from the control information storage unit 600, and also outputs the instruction length information to the addition circuit 570. The adder circuit 570 receives the instruction length information from the instruction length / operation mode control circuit 560, adds a predetermined value to the address value of the program counter 510, generates a next read address, and outputs the next read address to the selection circuit 580. The selection circuit 580 receives the address from the adder circuit 570 and the branch destination address output from the decode execution unit 700, and selects one next read address based on the branch establishment information output from the decode execution unit 700. To the program counter 510.

  Next, the details of the operation of the instruction fetch / instruction data supply unit 500 that supplies an instruction read from the instruction memory 100 to each processor will be described with reference to FIGS.

  The programs constituting the program sequence shown in FIG. 3 are described using “basic instructions” or “extended instructions” and executed by the core processor 200 of the processor 1 and the coprocessors # 1 (300) and / or # 2 (400). It is processed.

  The “basic instruction 2” of this program is a subroutine branch instruction (JSRV) for changing the operation mode from the core operation mode to the parallel operation mode, with the contents of the register designated by the instruction being the branch destination address. In addition, the instruction length of the “extended instruction” of the branch destination address is specified using the least significant bit that is not used for specifying the branch destination address in the contents of the register serving as the branch destination address. That is, when the least significant bit in the branch destination address of the branch instruction is “1”, the “extended instruction” of the branch destination address has a 64-bit length (instruction F1b or F2b in FIG. 2) and the least significant bit. When the bit is “0”, the “extended instruction” of the branch destination address is a 32-bit type (instruction F1a or F2a in FIG. 2).

  Furthermore, in this program example, since the least significant bit in the branch destination address of “basic instruction 2” is set to “1”, the instruction before “basic instruction 1” is set. The instruction length of the instruction after "instruction 1" is a 64-bit type.

  Here, even if the instruction word length of the “extended instruction” at the branch destination is specified using the least significant bit in the branch destination address of the branch instruction, the instruction memory 100 has 8 bits (bytes). ) In a processor in which an address is assigned in units and the basic instruction with the shortest instruction length is 16 bits, generally, the address at which the instruction is loaded is limited to an even address. This is because the bit is not used for addressing.

  The instruction arrangement state on the instruction memory 100 shown in FIG. 4 shows a state when the program sequence shown in FIG. 3 is converted into a machine language and loaded into the instruction memory 100.

  Next, the operation when the “basic instruction 1” is read from the instruction memory 100 will be described. The processor 1 is assumed to be a processor having a five-stage pipeline configuration shown in FIG. 5A, for example, and in order to further simplify the description, an instruction executed by the decode execution unit 700 when the “basic instruction 1” is read. The “basic instruction” and the “extended instruction” other than “basic instruction 2” shown in FIG. 3 are not instructions accompanied by a branch operation, and an interrupt or the like does not occur during the following operation explanation period.

  In the first cycle of FIG. 5A, an address value “0x100” (0x indicates hexadecimal display) is set in the program counter 510 of the instruction fetch / instruction data supply unit 500, and this program counter 510 The address value is output to the instruction memory 100, and then a read signal is output from the memory request control unit 520 to the instruction memory 100 as a fetch request.

  As a result, the instruction memory 100 outputs the contents at the address 0x100 to the instruction buffer 530, and the instruction buffer 530 reads “basic instruction 1”.

  Next, since the operation mode information output from the control information storage unit 600 at this time is the core operation mode, the instruction data supply unit 540 converts the “basic instruction 1” read into the instruction buffer 530 into the core processor 200. The NOP instruction (non-operation instruction) generated by the NOP instruction generation circuit 550 is supplied to the decoder execution unit 700, and the decode execution unit 710 of the coprocessor # 1 (300) and the decode execution unit of the coprocessor # 2 (400) 720.

  When reading “basic instruction 1”, the instruction length / operation mode control circuit 560 is the core operation mode and the instruction length of “basic instruction 1” is 16 bits (2 bytes). Instruction length information for adding “2” to 570 is output. Then, the adder circuit 570 generates an address value “0x102” by adding “2” to the address value of the program counter 510. This address value is input to the program counter 510 via the selection circuit 580 because the instruction being executed by the decode execution unit 700 is not a branch instruction, and the program counter 510 is read together with the operation of reading “basic instruction 1” into the instruction buffer 530. Is output to the instruction memory 100 as the memory address of the next instruction to be read.

  Next, in the second cycle of FIG. 5A, as in the first cycle, “basic instruction 2” read from the address “0x102” in the instruction memory 100 to the instruction buffer 530 is an instruction fetch / instruction data supply unit. 500 is supplied to the decoder execution unit 700 of the core processor 200 and the NOP instruction generated by the NOP instruction generation circuit 550 is sent to the decode execution unit 710 of the coprocessor # 1 (300) and the coprocessor # 2 (400). The data is supplied to the decoding execution unit 720. Similarly, the address value “0x104” generated by the addition circuit 570 is set in the program counter 510 via the selection circuit 580 because “basic instruction 1” decoded and executed by the decode execution unit 700 is not a branch instruction. The address value is output to the instruction memory 100.

  Next, in the third cycle of FIG. 5A, “basic instruction 3” read from the address “0x104” of the instruction memory 100 to the instruction buffer 530 is transferred from the instruction fetch / instruction data supply unit 500 to the core processor 200. In addition to being supplied to the decoder execution unit 700, the NOP instruction generated by the NOP instruction generation circuit 550 is supplied to the decode execution unit 710 of the coprocessor # 1 (300) and the decode execution unit 720 of the coprocessor # 2 (400). The At the same time, the decode execution unit 700 decodes (interprets) the “basic instruction 2” (JSRV) read in the second cycle and executes it.

  Since this “basic instruction 2” (JSRV) is not a conditional branch instruction but a branch instruction in which a branch is established, the decode execution unit 700 stores it in a register designated by the basic instruction 2 (usually a general-purpose register of the core processor 200). The determined value (here, “0x409”) is used as a branch destination address, and branch establishment information is output to the instruction fetch / instruction data supply unit 500 as branch establishment information. At this time, the selection circuit 580 receives the address value “0x408” in which the least significant bit of the register value “0x409” is “0” as the branch destination address, and the branch establishment is input to the selection control input of the selection circuit 580. The As a result, the selection circuit 580 outputs the branch destination address “0x408” to the program counter 510 as the next read address. The branch destination address “0x408” is written to the program counter 510 together with the read operation of “basic instruction 3” to the instruction buffer 530, and is output to the instruction memory 100 as the memory address of the next instruction to be read. In addition, the control information of the operation mode of the control information storage unit 600 is changed from the core operation mode to the parallel operation mode, and the instruction length control information of the control information storage unit 600 includes the lowest address of the branch destination address stored in the register. The value of the bit (here “1”) is written.

  Since the branch instruction that establishes the branch is executed, the pipeline operation of “basic instruction 3” read from the instruction memory 100 and supplied to the decode execution unit 700 in the third cycle is canceled (discarded). The subroutine branch instruction performs an operation of storing the address value of the program counter 510, which is a generally known operation in the execution of the subroutine instruction, so that the return operation from the subroutine can be normally performed. The operation mode and instruction length information is saved when the branch instruction is executed. The return operation from the subroutine is performed by a return instruction (RET). This return instruction is stored in the control information storage unit 600 in addition to a generally known return operation such as setting an address value stored in the program counter 510. Set the saved operation mode and instruction length information. In this way, the instruction immediately after the subroutine branch instruction to be executed after the return operation is executed in the operation mode and instruction length when the subroutine branch instruction is executed.

  Next, in the fourth cycle, the instruction fetch / instruction data supply unit 500 operates in the parallel operation mode of the instruction length of 64 bits set in the third cycle, and the “expansion” from the address “0x408” of the instruction memory 100 is performed. Read instruction 1 ”into instruction buffer 530. Since the instruction format of the read “extended instruction 1” is the F1b type in FIG. 2, the instruction data supply unit 540 converts the instruction based on the 16-bit length “core” field into the decode execution unit 700 of the core processor 200. And an instruction based on the 48-bit “co-pro” field is supplied to the decode execution unit 710 of the coprocessor # 1 (300) and the decode execution unit 720 of the coprocessor # 2 (400).

  Here, the instruction data supply unit 540 decodes (interprets) the instruction read from the instruction buffer 530 within a range necessary for instruction supply control based on the instruction length from the control information storage unit 600 and the control information of the operation mode. The instruction field of the read instruction and the output of the NOP instruction generation circuit 550 are combined to generate instruction data, and includes a decoding circuit and a selection (selector) circuit.

  The “extended instruction 1” is a type of instruction that individually designates instructions to the coprocessor # 1 (300) and the coprocessor # 2 (400). An 8-bit NOP instruction (all “0”) from the NOP instruction generation circuit 550 is added to 24 bits to generate 32-bit instruction data and supply it to the coprocessor # 1 (300). Similarly, an 8-bit NOP instruction is added to the lower 24 bits of the “co-pro” field to generate 32-bit instruction data, which is supplied to the coprocessor # 2 (400).

  Next, when “extension instruction 1” is read in the fourth cycle, the control information storage unit 600 stores that the next operation mode is the parallel operation mode and the instruction length is 64 bits (8 bytes). . In response to this, the instruction length / operation mode control circuit 560 outputs instruction length information for adding “8” to the adder circuit 570. As a result, the adder circuit 570 generates an address value “0x410” obtained by adding “8” to the address value from the program counter 510, and sets it in the program counter 510 via the selection circuit 580. Then, along with the operation of reading “extended instruction 1” to the instruction buffer 530, the program counter 510 outputs the instruction address to the instruction memory 100 as the memory address of the next instruction to be read.

  Next, in the fifth cycle, as in the fourth cycle, the instruction fetch / instruction data supply unit 500 operates to read “extended instruction 2” from the address “0x410” of the instruction memory 100 into the instruction buffer 530. Since the instruction format of the read “extended instruction 2” is the F2b type of FIG. 2, the instruction data supply unit 540 decodes the 16-bit length NOP instruction from the NOP instruction generation circuit 550 to the decode execution unit of the core processor 200. And two instructions based on the 64-bit long “co-pro” field are supplied to the decode execution units 710 and 720 of the coprocessors # 1 (300) and # 2 (400), respectively.

  That is, since the “extended instruction 2” is a type of instruction that individually designates instructions to the coprocessor # 1 (300) and the coprocessor # 2 (400), the instruction data supply unit 540 has a 64-bit “copro”. The upper 32 bits of the field are supplied as instruction data to the coprocessor # 1 (300), and the lower 32 bits are supplied as instruction data to the coprocessor # 2 (400).

  Next, when the “extension instruction 2” of the fifth cycle is read, the control information storage unit 600 stores that the operation mode is the parallel operation mode and the instruction length is 8 bytes. In response to this, the instruction length / operation mode control circuit 560 outputs instruction length information for adding “8” to the adder circuit 570. As a result, the adder circuit 570 generates an address value “0x418” obtained by adding “8” to the address value of the program counter 510, and sets it in the program counter 510 via the selection circuit 580. Then, along with the operation of reading “extended instruction 2” into the instruction buffer 530, the memory address of the instruction to be read next is output from the program counter 510 to the instruction memory 100.

  Next, in the sixth cycle, as in the fourth cycle, the instruction fetch instruction / data supply unit 500 operates and “extended instruction 3” is read from the address “0x418” of the instruction memory 100 into the instruction buffer 530. Since the instruction format of the read “extended instruction 3” is the F1b type in FIG. 2, the instruction data supply unit 540 converts the instruction based on the 16-bit length “core” field into the decode execution unit 700 of the core processor 200. And an instruction based on the 48-bit “co-pro” field is supplied to the decode execution units 710 and 720 of the coprocessors # 1 (300) and # 2 (400).

  The “extended instruction 3” is an instruction data supply unit because it is a type of instruction that individually designates an instruction to the coprocessor # 1 (300) and the coprocessor # 2 (400), similarly to the “extended instruction 1”. 540 adds the 8-bit NOP instruction pattern from the NOP instruction generation circuit 550 to the upper 24 bits of the “co-pro” field, generates 32-bit instruction data, and supplies it to the coprocessor # 1 (300). . Similarly, an 8-bit NOP instruction pattern is added to the lower 24 bits of the “co-pro” field to generate 32-bit instruction data, which is supplied to the coprocessor # 2 (400).

  In the above description, the instruction supply status to each processor in the parallel operation mode has been described by using the example of the 64-bit “extended instruction”. However, the processor 1 determines the branch address of the branch instruction JSRV of the “basic instruction 2”. By setting the least significant bit to “0”, a parallel operation program can be created using an “extended instruction” having a 32-bit length.

  When a 32-bit “extended instruction” is read, the instruction fetch / instruction data supply unit 500 determines that the “co-pro” field is 16 bits or 32 bits long from the F1a type or F2a type shown in FIG. To do. Therefore, the instruction fetch / instruction data supply unit 500 adds the 16-bit NOP instruction pattern from the NOP instruction generation circuit 550 when it is 16 bits long, and sends the 32-bit instruction of the coprocessor when it is 32 bits long. Supply to one (eg, coprocessor # 1 (300)) and operate to supply the other coprocessor (eg, coprocessor # 2 (400)) with a 32-bit NOP instruction from the NOP instruction generation circuit 550 To do.

  In the above description, a subroutine branch instruction is used as an instruction for changing the operation mode of the processor 1. This is because a problem arises when the operation mode is changed by an instruction 1 that is not a branch instruction in the following program sequence sequence.

::
Instruction 1 Basic instruction Instruction 2 Basic instruction Instruction 3 Extended instruction Instruction 4 Extended instruction::
In the example of the above program sequence, for example, in a processor having a five-stage pipeline configuration, the basic instruction of “instruction 1” read in the first cycle is decoded and executed in the second cycle to control the operation mode, as described above. The register is written, but the instruction read operation mode is switched from the third cycle. “Instruction 2” read in the second cycle is read as a basic instruction, “Instruction 3” is read as an extension instruction in the subsequent third cycle, and “Instruction 3” includes a coprocessor in the fourth cycle. Decoded and parallel operation is performed.

  However, in a pipelined processor, the number of pipeline stages is increased to improve performance. For example, in a processor used in a system that requires time for memory access, the pipeline stage configuration is changed from a five-stage configuration shown in FIG. 5A to a seven-stage configuration shown in FIG. Improvement is achieved.

  If the processor pipeline configuration is changed to a seven-stage configuration in order to use a low-speed memory, unlike the five-stage pipeline processor, “instruction 1” of the operation mode change instruction read in the first cycle is decoded. The third cycle is executed and the operation mode is changed from the fourth cycle. For this reason, the “instruction 3” read in the third cycle is read as a basic instruction rather than an extension instruction, causing a problem that compatibility at the object level is lost.

  As in the first embodiment described above, the operation mode is changed by the subroutine branch instruction, so that the parallel operation control program part can be described like a function and the prospect of program description is good. In addition, compatibility at the object level can be maintained.

  Furthermore, since instructions are supplied as described above and the parallel processor operates, it is not necessary to place a NOP instruction corresponding to a non-operating processor in the parallel processor in the instruction memory, and a plurality of coprocessors can be simultaneously parallelized. When a program that requires high processing performance and a program that can achieve processing performance by operating one coprocessor are mixed, the program can be described by selecting an extension instruction with an appropriate instruction length. A parallel processor with high instruction memory utilization efficiency can be provided.

  In the above description, the least significant bit in the branch destination address of the branch instruction specifies the instruction length of the branch destination “extended instruction”. However, a branch instruction that specifies the instruction length (for example, a 32-bit length) May be defined as JSRV32, or JSRV64 in the case of a 64-bit length, and specify the instruction length of the “extended instruction” at the branch destination.

   Furthermore, in the above description, when supplying a co-profile of a 64-bit extended instruction to two co-processors, the “co-pro” field is divided evenly, and the NOP instruction pattern is added to the shortage portion to 32 bits each. Although a long instruction is supplied, the “co-pro” field is divided into different lengths according to the processing functions of the coprocessor # 1 (300) and the coprocessor # 2 (400), the instruction designation contents, etc. The instructions for each coprocessor may be generated and supplied. In the case of an extended instruction having a 32-bit length, an operation designation instruction is supplied to one coprocessor. However, the “co-pro” field may be divided and supplied to two coprocessors as instructions. Although individual instructions are supplied to the two coprocessors, instructions having the same contents may be supplied to the two coprocessors.

  Next, a parallel processor according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram of the processor 2 according to the second embodiment. FIG. 8 is a block diagram showing the configuration of the instruction fetch / instruction supply unit 501. FIG. 9 is a diagram illustrating a configuration of command supply pattern information set in the control information storage unit 601.

  In the instruction fetch / instruction supply unit 501 according to the second embodiment shown in FIG. 8, the same parts as those in the instruction fetch / instruction data supply unit 500 of the processor 1 according to the first embodiment are denoted by the same reference numerals. Detailed description will be omitted.

  The difference between the processor 2 and the instruction fetch / instruction data supply unit 501 of the second embodiment from the processor 1 and the instruction fetch / instruction data supply unit 500 of the first embodiment is that an instruction is supplied to the control information storage unit 601. The pattern information is stored, and the instruction supply pattern information is output from the control information storage unit 601 to the instruction fetch / instruction data supply unit 500 in addition to the instruction length and operation mode information. That is, the command length / operation mode / command supply pattern control circuit 561 receives command supply pattern information in addition to the command length and operation mode information to the command data supply unit 541.

  In the processor 2, the instruction supply pattern information is set in the control information storage unit 601 with the instruction before entering the parallel operation mode. The instruction supply pattern information is composed of a 2-bit length field for each coprocessor as shown in FIG. In the parallel operation mode, the instruction data supply unit 541 configures the value of the “co-pro” field of the extended instruction as an instruction according to the instruction supply pattern, and performs the decode execution unit 710 of the coprocessor # 1 (300) and the coprocessor # 2. (400) to the decode execution unit 720.

  For example, when the instruction supply pattern corresponding to each coprocessor is “00”, the NOP instruction generated by the NOP instruction generation circuit 550 is supplied to the decode execution unit of each coprocessor. Further, when the instruction supply pattern corresponding to each coprocessor is “01”, each instruction composed of the divided latter half pattern of the “copro” field of the extended instruction and the NOP instruction pattern having an insufficient number of bits Supplied to the decode execution unit of the coprocessor. Further, when the instruction supply pattern corresponding to each coprocessor is “10”, each instruction composed of the divided first half pattern of the “copro” field of the extended instruction and the NOP instruction pattern having an insufficient number of bits Supplied to the decode execution unit of the coprocessor. When the instruction supply pattern corresponding to each coprocessor is “11”, an instruction composed of the entire “copro” field of the extended instruction and the NOP instruction pattern having an insufficient number of bits is a decode execution unit of each coprocessor. The command data supply unit 541 is controlled so as to be supplied to.

  As described above, since the instruction supply to the coprocessor # 1 (300) and the coprocessor # 2 (400) can be flexibly controlled, it is not necessary to provide coprofiles corresponding to the number of built-in coprocessors. Further, when either one of the coprocessors is operated and operated in parallel, the coprofiled can be used as an instruction for each coprocessor, and a parallel processor with high use efficiency of the instruction memory can be provided.

  The present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the spirit of the invention.

  For example, a signal for stopping instruction execution may be supplied instead of generating and supplying a NOP instruction to a non-operating processor. In this way, not only the use efficiency of the instruction memory is high, but also the operation of the instruction supply circuit, the decode circuit, etc. to the coprocessor can be stopped, and a low power consumption processor can be provided.

The block diagram which shows the structure of the 1st Example of the processor by this invention. The figure which shows the format of the extension instruction | indication of a 1st Example. The figure which shows the command sequence containing the extended command of 1st execution example. The figure which shows arrangement | positioning of the instruction | command on the instruction | command memory of a 1st Example. The figure which shows the stage structure of the pipeline processor of a 1st Example. 1 is a block diagram showing a configuration of an instruction fetch / instruction data supply unit according to a first embodiment of the present invention; FIG. The block diagram which shows the structure of the 2nd Example of the processor by this invention. The block diagram which shows the structure of the instruction fetch and instruction data supply unit of 2nd Example by this invention. The figure which shows the structure of the command supply pattern information set to the control information storage part 601 of 2nd Example.

Explanation of symbols

1, 2 Parallel processor 100 Instruction memory 200 Core processor 300 Coprocessor # 1
400 coprocessor # 2
500, 501 Instruction fetch / instruction data supply unit 510 Program counter 520 Memory request control unit 530 Instruction buffer 540, 541 Instruction data supply unit 550 NOP instruction generation circuit 560 Instruction length / operation mode control circuit 561 Instruction length / operation mode / instruction supply Pattern control circuit 570 Adder circuit 580 Select circuit 600, 601 Control information storage unit 700, 710, 720 Decode execution unit

Claims (5)

A parallel processor configured by at least a first processor and a second processor, and executing pipeline processing of instructions executed by the processors in parallel in the same cycle;
A first instruction execution unit and an instruction fetch supply unit provided in the first processor;
A second instruction execution unit provided in the second processor;
An instruction memory for storing instructions executed by the first instruction execution unit and / or the second instruction execution unit;
The instruction fetch supply unit
Counter means for designating an address for reading the instruction from the instruction memory;
Instruction buffer means for holding the instruction read from the instruction memory;
A first operation mode for operating the first instruction execution unit and the second instruction execution unit in response to a read operation of the instruction memory; and a second operation mode for operating the second instruction execution unit. Operation mode control means for outputting control information;
NOP instruction generation means for generating a NOP instruction having a predetermined bit length;
Based on the control information of the operation mode from the operation mode control means, in the case of the first operation mode, a part of the instruction from the instruction buffer means and the NOP instruction are sent to the first instruction execution unit. Supplying an instruction comprising the NOP instruction from the generating means, and supplying an instruction comprising the remaining part of the instruction and the NOP instruction from the NOP instruction generating means to the second instruction execution unit; In the second operation mode, a parallel processor comprising: an instruction supply means for supplying a part or all of the instructions from the instruction buffer means to the second instruction execution unit. The instruction fetch supply unit
The control information of the operation mode control means is set by a branch instruction, and the first and second operation modes in the first and second operation modes according to information specifying an instruction length included in a part of a branch destination address defined by the branch instruction. 2. The parallel processor according to claim 1, wherein the instruction length of the instruction is switched. The instruction fetch supply unit
The control information of the operation mode control means is set by a branch instruction that specifies the instruction length of the branch destination instruction, and the first and second operation modes are set according to the information that specifies the instruction length specified by the branch instruction. The parallel processor according to claim 1, wherein the instruction length of the instruction is switched. A parallel processor configured by at least a first, a second and a third processor and pipelined in parallel in the same cycle for instructions executed by each processor;
A first instruction execution unit and an instruction fetch supply unit provided in the first processor;
A second instruction execution unit provided in the second processor;
A third instruction execution unit provided in the third processor;
An instruction memory for storing instructions executed by the first instruction execution unit, the second instruction execution unit, and / or the third instruction execution unit;
The instruction fetch supply unit
Counter means for designating an address for reading the instruction from the instruction memory;
Instruction buffer means for holding the instruction read from the instruction memory;
A first operation mode for operating the first instruction execution unit and the second instruction execution unit and / or the third instruction execution unit in accordance with a read operation of the instruction memory; and the second instruction execution unit. And an operation mode control means for outputting control information of the second operation mode for operating the third instruction execution unit,
NOP instruction generation means for generating a NOP instruction having a predetermined bit length;
Based on the control information of the operation mode from the operation mode control means, in the case of the first operation mode, a part of the instruction from the instruction buffer means is supplied to the first instruction execution unit. , Supplying the second and / or the third instruction execution unit with an instruction comprising the remaining part of the instruction and the NOP instruction from the NOP instruction generation means, and in the case of the second operation mode, And a command supply means for supplying a part of the instructions from the instruction buffer means to the second instruction processing section and supplying the remainder of the instructions to the third instruction execution section. Processor. A parallel processor configured by at least a first and a second processor and pipelined in parallel in the same cycle for instructions executed by each processor;
A first instruction execution unit and an instruction fetch supply unit provided in the first processor;
A second instruction execution unit provided in the second processor;
An instruction memory for storing instructions executed by the first instruction execution unit and / or the second instruction execution unit;
The instruction fetch supply unit
Counter means for designating an address for reading the instruction from the instruction memory;
Instruction buffer means for holding the instruction read from the instruction memory;
A first operation mode for operating the first instruction execution unit and the second instruction execution unit in response to a read operation of the instruction memory; and a second operation mode for operating the second instruction execution unit. Control means for outputting operation mode control information and pattern control information defining a method of supplying the instruction to the first and second instruction execution units;
NOP instruction generation means for generating a NOP instruction having a predetermined number of bits;
Based on the operation mode control information and the pattern control information from the control means, in the case of the first operation mode, a part of the instructions from the instruction buffer means and the part of the instructions from the instruction buffer means An instruction consisting of the NOP instruction from the NOP instruction generation means is supplied, and an instruction consisting of the remaining part of the instruction and the NOP instruction from the NOP instruction generation means is supplied to the second instruction execution unit. And in the second operation mode, a parallel processor comprising: an instruction supply means for supplying a part or all of the instructions from the instruction buffer means to the second instruction execution unit. .

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