JP2007142379A - Analog/digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain an analog/digital converter in which an area occupied on a semiconductor substrate decreases and which, moreover, obtains a high precision. <P>SOLUTION: An analog switch having a P-channel transistor 104a is formed on the semiconductor substrate 200. Comb-shaped electrodes 401, 402, and 501, 502 are formed on an overlap region to the analog switch in the upper layer of the analog switch, and a capacitor is constituted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an analog-digital converter that converts an analog signal into a digital signal.

  In order to obtain a large capacitance while reducing the area occupied by a capacitor on a semiconductor substrate, a technique is known in which wirings close to each other are formed in the same wiring layer and a fringe capacitance between these wirings is used ( For example, see Patent Documents 1 and 2.)

  Further, when an analog-digital converter is configured using the above-described capacitors, for example, as shown in FIG. 1, a capacitor array block 902 in which unit capacitors 901 having a predetermined capacity are arranged densely and vertically is formed. Is done. A dummy capacitor 903 is disposed around the capacitor array block 902 in order to suppress variation in the capacitance of each unit capacitor 901.

  One electrode of each unit capacitor 901 has an individual wiring (16C_Lin, 8C_Lin, 4C_Lin, 2C_Lin, 1C_Lin_a to 1C_Lin_f) for each group of a predetermined number (for example, 16, 8, 4, 2, 1) of unit capacitors 901. Connected to. Each individual wiring is connected to an analog switch 904a of a voltage switching circuit 904 disposed in the vicinity of the capacitor array block 902, and a predetermined reference voltage, a voltage divided by the R-2R resistor array 905, or An analog input voltage is selectively applied.

  The other electrode of each unit capacitor 901 is connected to the comparator 906 via a common wiring (com_Lin). The output of the comparator 906 is input to the control circuit 907 and converted into, for example, 10-bit digital values D0 to D9.

Further, as another technique for a circuit having a transistor and a capacitor, when a capacitor is connected between a source region and a drain region like a transistor constituting a power amplifier, each electrode is placed on each electrode. A technique is known in which wirings having the same pattern are stacked to form the capacitor (see, for example, Patent Document 3).
JP-A 61-263251 Japanese Patent No. 2700959 US Pat. No. 6,747,307

  However, in the analog-digital converter in which the voltage switching circuit 904 is disposed in the vicinity of the capacitor array block 902 as described above, the area occupied by the capacitor array block 902 can be reduced by using the fringe capacitance. The area occupied by the voltage switching circuit 904 cannot be reduced. Therefore, it is difficult to reduce the area of the entire analog-digital converter.

  In addition, since the layout of the individual wiring is different for each group of unit capacitors 901 and it is difficult to avoid crossing between the individual wirings and the common wiring, it is difficult to increase the relative capacitance ratio of each group with high accuracy. In addition, it is difficult to reduce the influence of crosstalk. Therefore, it is difficult to obtain a highly accurate analog-digital converter.

  In addition, the configuration in which the capacitor is formed by stacking wirings in the source region and the drain region of the transistor cannot arbitrarily set the polarity of the transistor and the connection relationship between the transistor and the capacitor, and the size and shape of the transistor. Accordingly, the arrangement of each electrode is determined, so that a desired capacity is not always obtained.

  In view of the above points, the present invention aims to reduce the area occupied by an analog-digital converter on a semiconductor substrate. Another object of the present invention is to make it possible to easily improve the accuracy of an analog-digital converter.

In order to solve the above problems, the present invention provides:
An analog switch having a P-channel transistor and an N-channel transistor formed on a semiconductor substrate;
A capacitive element having first and second electrodes;
Have
The source region of the P-channel transistor is connected to the drain region of the N-channel transistor, and the source region of the N-channel transistor is connected to the drain region of the P-channel transistor. An analog-to-digital converter to which a plurality of electrodes are connected,
The first and second electrodes are
It is formed in a region overlapping with the analog switch in a layer different from the analog switch,
The p-channel transistor and the n-channel transistor are formed in a comb pattern different from the arrangement pattern of the source region and the drain region.

  As a result, the capacitor element is formed in a region overlapping with the analog switch in a layer different from the analog switch, so that the area required for forming the analog switch and the capacitor element can be easily reduced. In addition, it is easy to connect the analog switch and the capacitive element over a short distance, so that the generation of parasitic capacitance and crosstalk can be suppressed, the change in capacitance ratio and the influence of noise can be reduced, and high accuracy can be achieved. It is easy to make analog-to-digital conversion.

  According to the present invention, the area occupied by the analog-digital converter on the semiconductor substrate can be easily reduced. Further, it is possible to easily improve the accuracy of the analog-digital converter.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each of the following embodiments, components having functions similar to those of the other embodiments are denoted by the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
(Circuit configuration)
Regarding the example of the 10-bit successive approximation type analog-digital converter of the first embodiment, first, the circuit configuration of the analog-digital converter 100 will be described with reference to FIG. The analog-digital converter 100 includes a capacitor array block 101 including capacitors 16C, 8C, 4C, 2C, and 1C having a capacitance ratio of 16: 8: 4: 2: 1. (Six capacitors 1C are provided, and five of them serve as capacitance ratios of 1/2, 1/4, 1/8, 1/16, 1/32 by using the R-2R resistor array 102. It has been done.)
One electrode of each capacitor is connected to, for example, three analog switches 104 provided in the analog switch group 103. These analog switches 104 selectively apply a high potential reference voltage VrefH, a low potential reference voltage VrefL, a voltage obtained by dividing these voltages by the R-2R resistor array 102, or an analog input voltage Ain to each capacitor. To do.

  The other electrode of each capacitor is connected to the comparator 105. The output of the comparator 105 is converted into a 10-bit digital value D0 to D9 by the control circuit 106.

(Capacitor structure)
Each of the capacitors is configured by combining one or a plurality of unit capacitors 201 as shown in FIGS. Each unit capacitor 201 is configured by providing first to third metal wiring layers (M1 layer 300 to M3 layer 500) made of, for example, aluminum on a semiconductor substrate 200 on which the analog switch 104 is formed.

  As shown in FIG. 3, the semiconductor substrate 200 is made of, for example, a P-type semiconductor, and a P-channel transistor 104a and an N-channel transistor 104b constituting the analog switch 104 are formed. More specifically, an N well 210 is formed on the semiconductor substrate 200, and P + regions 211 and 212 (source and drain) and a polysilicon gate 213 are formed in the N well 210, whereby the P channel transistor 104a is formed. Is formed. Further, the N + regions 221 and 222 (source and drain) and the polysilicon gate 223 are formed directly on the semiconductor substrate 200, whereby the N-channel transistor 104b is formed. An N + diffusion layer 214 and a P + diffusion layer 224 (guard band) are formed around each transistor 104a and 104b so as to surround them.

  In the M1 layer 300, as shown in FIG. 3, a switch wiring 301 that connects the P + region 211 and the N + region 221 of the transistors 104a and 104b is formed. In addition, a switch wiring 302 is formed to connect the P + region 212, the N + region 222, and the circuit outside the unit capacitor 201 of the transistors 104a and 104b. Further, power supply wirings 311 and 312 (guard band) for connecting the N + diffusion layer 214 to the high potential source and power supply wirings 321 and 322 (guard band) for connecting the P + diffusion layer 224 to the low potential source are formed. Further, shields 313 and 323 covering the transistors 104a and 104b are formed integrally with the power supply wirings 311 and 312.

  The switch wiring 301 and the source and drain regions of the transistors 104a and 104b, the switch wiring 302 and the source and drain regions of the transistors 104a and 104b, the power wirings 311 and 312, the shield 313, the N + diffusion layer 214, and the power wirings 321 and 322 The shield 323 and the P + diffusion layer 224 are connected via contacts 314 and 324, respectively.

  As shown in FIG. 6, the M2 layer 400 includes a pair of comb-shaped electrodes 401 and 402 that have parallel portions 401a and 402a and connecting portions 401b and 402b, respectively, and generate capacitance. One comb-shaped electrode 402 is connected to the switch wiring 301 of the M1 layer 300 through a contact 409.

  Further, shields 403 to 408 (guard bands) for reducing crosstalk with the other unit capacitors 201 are formed around the comb electrodes 401 and 402, and are connected to a high potential source or a low potential source. It has become so. The shields 405 to 408 are preferably formed to have the same line width and pitch as the comb electrodes 401 and 402 (dummy wiring) in order to suppress the etching variation of the comb electrodes 401 and 402 at the time of manufacture (limited to this). It is not a thing. Here, as described above, shields 405 and 407 are arranged instead of the comb-shaped electrodes 401 and 402 in the region overlapping the switch wiring 301 and the switch wiring 302 of the M1 layer 300, so that the switch wiring 301 or the switch wiring 302 Generation of parasitic capacitance between the comb electrodes 401 and 402 can be suppressed.

  As shown in FIG. 7, the M3 layer 500 includes comb-shaped electrodes 501 and 502 having parallel portions 501a and 502a and connecting portions 501b and 502b, and shields 503 to 508 (guard bands) as in the M2 layer 400. Formed and connected to the comb electrodes 401 and 402 of the M2 layer 400 and the shields 403 to 408 through the contacts 509, respectively. Here, the comb-shaped electrode 501 overlaps the comb-shaped electrode 402, and the comb-shaped electrode 502 is formed to overlap the comb-shaped electrode 401, so that a capacitance is generated in a direction perpendicular to the semiconductor substrate 200. Further, the connecting portions 501b and 502b are extended to the peripheral portion of the unit capacitor 201, and can be easily connected to the connecting portions 501b and 502b of other unit capacitors 201 arranged adjacent to each other.

(Layout of unit capacitor 201 etc.)
Next, an example of a layout when the unit capacitor 201 formed as described above, the comparator 105, the control circuit 106, and the like are arranged on a semiconductor substrate will be described with reference to FIG.

  A total of 36 unit capacitors 201 are arranged adjacent to each other in one direction between the dummy wiring regions 111 and 111. Of these, the unit capacitors 201 of 16, 8, 4, and 2 groups are connected to form capacitors 16C, 8C, 4C, and 2C (the order of arrangement is not particularly limited). More specifically, the connecting portions 501b of the comb electrodes 501 in all the unit capacitors 201 are connected to each other and used as a common wiring (com_Lin). On the other hand, the connecting portion 502b of the comb electrode 502 is connected for each unit capacitor 201 of each group.

  As described above, the capacitor is formed by forming the comb-shaped electrodes 401, 402, 501, and 502 in the overlapping region in a different layer from the transistors 104a and 104b, thereby easily reducing the area required for forming the capacitor and the analog switch. can do. In addition, the source or drain regions of the transistors 104a and 104b and the comb-shaped electrodes 402 and 502 can be connected to each other at a very short distance (for example, the shortest distance) via the contacts 409 and 509, so that parasitic capacitance and crosstalk are generated. By suppressing the above, it is possible to easily perform analog-digital conversion with high accuracy by reducing the change in capacitance ratio and the influence of noise.

  In addition, when the shields 313 and 323 are provided in the M1 layer 300 between the transistors 104a and 104b and the comb electrodes 401 and 402 as described above, it is easy to reduce the influence of switching noise of the transistors 104a and 104b. Can be.

  In addition, when the shields 313 and 323 are formed in a planar shape, the layout accuracy of the upper comb electrodes 401 and 402 and the like can be easily kept high, so that the analog-digital conversion accuracy can be easily increased. . Further, it becomes easy to further miniaturize the wiring pattern. However, the shields 313 and 323 are not limited to a planar shape. For example, the shields 313 and 323 have the same wiring width and pitch as the parallel parts 401a and the like of the comb-shaped electrode 401 as in the shields 313 ′ and 323 ′ shown in FIGS. Or may be formed.

<< Embodiment 2 of the Invention >>
As shown in FIGS. 11 to 13, dummy wirings 411 and 511 are formed on the outer sides of the shields 403, 404, 503, and 504 in the M2 and M3 layers 400 and 500. The dummy wirings 411 and 511 have portions having the same width and pitch as the parallel portions 401a and 402a of the comb electrodes 401 and 402. As a result, variations in the degree of etching can be suppressed in the manufacturing process, so that the shape accuracy of the parallel portions 401a and 402a, and thus the A / D conversion accuracy can be easily increased.

  For example, the R-2R resistance array 102 and the control circuit 106 are formed in a region overlapping the dummy wirings 411 and 511 in the semiconductor substrate 200 (a region including at least a part of the overlapping region). As a result, the area occupied by the analog-digital converter on the semiconductor substrate can be further reduced.

  The M2 and M3 layers 400 and 500 are not limited to the dummy wirings 411 and 511. For example, as shown in FIG. 12, a wiring pattern 412 connected to the switch wiring 302 via a contact 409 is provided, and M1 The layer 300 may be used for wiring of the control circuit 106 or the like. Even when the wiring pattern 412 is provided in this way, it is easy to configure the control circuit 106 and the like while maintaining high A / D conversion accuracy by keeping the wiring width and pitch uniform. The dummy wirings 411 and 511 themselves may be used as a wiring pattern.

<< Embodiment 3 of the Invention >>
As described in the first embodiment, it is suitable to use the M1 layer 300 as the shields 313 and 323 in that the influence of the switching noise of the transistors 104a and 104b can be easily reduced. 300 may also be used as an electrode constituting a capacitor to reduce the area or increase the capacity.

  Specifically, in the example of FIGS. 14 and 15, comb electrodes 351 and 352 having parallel portions 351 a and 352 a and connecting portions 351 b and 352 b are formed on the M1 layer 300 in the same manner as the comb electrodes 501 and 502. Yes. The comb electrodes 351 and 352 are connected to comb electrodes 401 and 402 formed on the M2 layer 400 via contacts 409, respectively. The comb electrode 351 is formed so as to overlap the comb electrode 402, and the comb electrode 352 is formed so as to overlap the comb electrode 401. One of the parallel portions 352a also serves as a switch wiring that connects one source region and the other drain region of the transistors 104a and 104b via contacts 314 and 324, respectively.

  By forming in this way, the capacitance of the unit capacitor 201 is increased by the capacitance generated between the comb electrodes 351 and 352 and the capacitance generated between the comb electrodes 351 and 352 and the comb electrodes 401 and 402. Can do. Alternatively, the area of the unit capacitor 201 can be reduced.

  In the example shown in the figure, the power supply wirings 311 ′, 312 ′, 321 ′, and 322 ′ are formed with the same wiring width and pitch as the parallel portions 351 a and 352 a of the comb-shaped electrodes 351 and 352. When formed in this way, the shape accuracy of the parallel portions 351a and 352a can be easily increased as described for the comb-shaped electrodes 401 and 402 in the second embodiment.

<< Embodiment 4 of the Invention >>
The transistors formed on the semiconductor substrate 200 are not limited to one analog switch 104, and other one or more analog switches 604, one or more single transistors, and the like are formed to form various circuits. It may be. For example, as shown in FIGS. 16 and 17, P + regions 611 and 612 (source and drain) and a polysilicon gate 613 are formed in the N well 210, thereby forming a P channel transistor 604a. Further, the N + regions 621 and 622 (source and drain) and the polysilicon gate 623 (gate) are directly formed on the semiconductor substrate 200, whereby an N-channel transistor 604b is formed.

  In the M1 layer 300, a switch wiring 701 that connects the P + region 611, the N + region 621, and the circuit outside the unit capacitor 201 of the transistors 604a and 604b is formed. In addition, a switch wiring 702 that connects the P + region 612 and the N + region 622 of the transistors 604a and 604b and a circuit outside the unit capacitor 201 is formed.

  Further, shields 313 ′ and 323 ′ are formed on the M1 layer 300. The shields 313 ′ and 323 ′ may be formed in a planar shape in a region that avoids the switch wirings 701 and 702. However, as shown in FIGS. 16 and 17, the power supply wirings 311 ′, 312 ′, 321 ′, 322 ′, shields 313 ′, 323 ′, and switch wirings 301, 302, 701, 702 are parallel to the comb-shaped electrode 401. If formed with the same wiring width and pitch as the portion 401a and the like, the similarity of the wiring patterns of the M1 layer 300 and the M2 layer 400 increases, so that the shape accuracy of the parallel portion 401a and the like of the comb electrode 401 can be easily increased. Can be.

<< Embodiment 5 of the Invention >>
In the first embodiment, the parallel portions 401 a and 502 a of the comb-shaped electrode 401 and the comb-shaped electrode 502, and the parallel portions 402 a and 501 a of the comb-shaped electrode 402 and the comb-shaped electrode 501 are formed so as to overlap each other, and in a direction perpendicular to the semiconductor substrate 200. Although an example in which capacitance is generated is shown, the capacitance may be generated only in a direction parallel to the semiconductor substrate 200. Specifically, for example, as illustrated in FIGS. 18 to 21, the comb electrodes 401 ′ and 402 ′ of the M2 layer 400 are formed so as to overlap the comb electrodes 501 and 502 of the M3 layer 500, respectively.

  When formed in this way, capacitance is generated only between the parallel portions 401a 'and 402a' and between the parallel portions 501a and 502a, and thus the capacitance generated in the same wiring pattern area is reduced. However, even if the mask for forming the M2 layer 400 and the mask for forming the M3 layer 500 are shifted in the manufacturing process, the capacitance does not change due to the shift. The accuracy can be easily increased.

  In the example shown in the figure, the shields 313 ′ and 323 ′ have the same wiring width and the same width as the parallel part 401a ′ of the comb-shaped electrode 401 ′ as described in the modification of the first embodiment (FIGS. 9 and 10). Although an example in which the pitch is formed is shown, it may be formed in a planar shape as shown in the first embodiment (FIGS. 3 to 5).

Embodiment 6 of the Invention
(Other layouts such as unit capacitor 201)
The unit capacitors 201 as described in the first embodiment are not limited to being arranged in one row on the semiconductor substrate, but may be arranged in two rows as shown in FIG. 22, for example.

  A total of 36 unit capacitors 201 are arranged adjacent to each other in two rows. Of these, the unit capacitors 201 of 16, 8, 4, and 2 groups are connected to form capacitors 16C, 8C, 4C, and 2C (the order of arrangement is not particularly limited). More specifically, for example, in the capacitor 16C, eight unit capacitors 201 are arranged in line symmetry. The connecting portion 502b of the comb electrode 502 is connected for each unit capacitor 201 of each group. On the other hand, the connecting portions 501b of the comb electrodes 501 in all the unit capacitors 201 are connected to each other, and a U-shaped common wiring (com_Lin) is formed near the outer periphery so as to surround the group of unit capacitors 201.

  Even in this arrangement, the area required for forming the capacitor and the analog switch can be easily reduced as in the first embodiment. Also, the connection lines between the source or drain regions of the transistors 104a and 104b and the comb-shaped electrodes 402 and 502 and the wirings connecting the connecting portions 502b of the unit capacitors 201 of each group are prevented from crossing the common wiring. Thus, the generation of parasitic capacitance and crosstalk can be suppressed, and analog-digital conversion can be easily performed with high accuracy.

<< Embodiment 7 of the Invention >>
(Layout on LSI chip)
The layout in which the analog-digital converter 100 as described in the first and sixth embodiments is arranged on the LSI chip is not particularly limited. For example, the layout can be as follows.

  When the unit capacitors 201 are arranged in one row as in the first embodiment, it is relatively easy to keep the size of the analog-digital converter 100 in the width direction small. For example, as shown in FIG. The analog / digital converter 100 and the input / output cells 802 (cells including the terminal pads 802a) arranged in the peripheral part of the LSI chip 801 may be designed to have the same size in the width direction and arranged side by side. As a result, when there is a margin (dead space) in the terminal pad region, it is possible to easily reduce the LSI chip area by effectively utilizing the region.

  On the other hand, when the unit capacitors 201 are arranged in two rows as in the sixth embodiment, for example, they may be arranged in the internal region 803 of the LSI chip 801 as shown in FIG.

<< Embodiment 8 of the Invention >>
(Design method of analog-digital converter)
As described in the first embodiment (FIG. 8) and the sixth embodiment (FIG. 22), by arranging a predetermined number of unit capacitors 201, combinations of capacitors having various capacitances and analog switches can be configured. . Therefore, by registering the unit capacitor 201 in the library as a cell and creating arrangement data in which the unit capacitors 201 are arranged side by side, the LSI chip area is small as described above, and the accuracy of the capacitance ratio is high and the influence of crosstalk. Therefore, it is possible to easily design an analog-digital converter having a high quality of analog-digital conversion with a certain quality and with a small number of man-hours.

  In addition, if a plurality of types of unit capacitors 201 having various accuracy levels, sizes, areas, and the like are registered in the library, it is possible to easily design and change the analog-digital converter according to the required specifications. Furthermore, analog / digital converters of various conversion bit lengths such as 8 bits and 10 bits can be designed by arranging a predetermined number of unit capacitors 201.

<< Other Embodiments >>
An analog-digital converter may be configured by using a unit capacitor in which only the capacitive element is formed and the analog switch 104 is not formed together with the unit capacitor 201. That is, if the analog switch 104 included in one or several unit capacitors 201 is sufficient for the required number of analog switches, the analog switches 104 may not necessarily be formed in other unit capacitors. Further, even if the analog switch 104 is formed, it may not be actually used. Furthermore, the formed analog switch 104 may be used for another circuit.

  In the example of FIG. 25, in the capacitors 16C and 8C, the analog switch 104 provided in each of the three unit capacitors 201 is used for selecting the reference voltage VrefH, the reference voltage VrefL, etc., and the other n unit capacitors An analog switch 104 provided in 201 is used to select any one of n analog input voltages Ain_1 to Ain_n. As a result, an analog-to-digital converter in which voltages input from a plurality of analog input voltage terminals are switched by an analog selector can be obtained without providing an analog switch particularly in an area outside the unit capacitor 201.

  The analog-digital converter according to the present invention has an effect that the area occupied by the analog-digital converter on the semiconductor substrate can be easily reduced, and the high-accuracy of the analog-digital converter can be easily achieved. It is useful as an analog-digital converter for converting an analog signal into a digital signal.

It is a top view which shows the circuit arrangement | positioning of the conventional analog-digital converter. 2 is a circuit diagram illustrating a circuit configuration of the analog-digital converter according to Embodiment 1. FIG. FIG. 3 is a horizontal sectional view showing the configuration of the unit capacitor. FIG. It is another vertical sectional view of the same. It is another horizontal sectional view of the same. It is another horizontal sectional view of the same. It is a top view which shows the circuit arrangement | positioning of an analog-digital converter same as the above. It is a horizontal sectional view which shows the structure of the unit capacitor of a modification. FIG. FIG. 6 is a horizontal cross-sectional view illustrating a configuration of a unit capacitor according to a second embodiment. It is another horizontal sectional view of the same. It is another horizontal sectional view of the same. 6 is a horizontal cross-sectional view illustrating a configuration of a unit capacitor according to Embodiment 3. FIG. FIG. 6 is a horizontal cross-sectional view illustrating a configuration of a unit capacitor according to Embodiment 4. FIG. FIG. FIG. 10 is a horizontal cross-sectional view illustrating a configuration of a unit capacitor according to a fifth embodiment. FIG. It is another horizontal sectional view of the same. It is another horizontal sectional view of the same. FIG. 10 is a plan view showing a circuit arrangement of an analog-digital converter according to a sixth embodiment. FIG. 10 is a plan view showing an arrangement on an LSI chip of an analog-digital converter according to a seventh embodiment. It is a top view which shows other arrangements similarly. It is a circuit diagram which shows the circuit structure of the analog / digital converter of a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Analog-digital converter 101 Capacitance array block 102 R-2R resistance array 103 Analog switch group 104 Analog switch 104a P channel transistor 104b N channel transistor 105 Comparator 106 Control circuit 200 Semiconductor substrate 201 Unit capacitor 210 N well 211 * 212 P + area 213 Polysilicon gate 214 N + diffusion layer 221 and 222 N + region 223 Polysilicon gate 224 P + diffusion layer 300 M1 layer 301 and 302 Switch wiring 311 and 312 Power supply wiring 313 and 323 Shield 314 and 324 Contact 321 and 322 Power supply wiring 351 and 352 Comb-shaped electrodes 351a and 352a Parallel portions 351b and 352b Connecting portions 400 M2 layers 401 and 402 Comb-shaped electrodes 401a and 4 02a Parallel part 401b / 402b Connecting part 403-408 Shield 409 Contact 411/511 Dummy wiring 412 Wiring pattern 500 M3 layer 501/502 Comb electrode 501a / 502a Parallel part 501b / 502b Connecting part 503-508 Shield 509 Contact 604 Analog switch 604a P channel transistor 604b N channel transistor 611/612 P + region 613 Polysilicon gate 621/622 N + region 623 Polysilicon gate 701/702 Switch wiring 801 LSI chip 802 I / O cell 802a Terminal pad 803 Internal region

Claims (12)

An analog switch having a P-channel transistor and an N-channel transistor formed on a semiconductor substrate;
A capacitive element having first and second electrodes;
Have
The source region of the P-channel transistor is connected to the drain region of the N-channel transistor, and the source region of the N-channel transistor is connected to the drain region of the P-channel transistor. An analog-to-digital converter to which a plurality of electrodes are connected,
The first and second electrodes are
It is formed in a region overlapping with the analog switch in a layer different from the analog switch,
An analog-to-digital converter characterized in that it is formed in a comb-shaped pattern different from the arrangement pattern of the source region and drain region of the P-channel transistor and N-channel transistor. The analog-to-digital converter of claim 1,
An analog-digital converter, wherein a shield layer is formed in a layer between the layer in which the first and second electrodes are formed and the analog switch. An analog-digital converter according to claim 2, comprising:
The analog-digital converter, wherein the shield layer has a portion formed at the same pitch and width as the first and second electrodes. The analog-to-digital converter of claim 1,
An analog-to-digital converter, wherein a shield wiring is formed in a region overlapping the source region and the drain region in the layer where the first and second electrodes are formed. An analog-to-digital converter according to claim 4,
The analog-digital converter characterized in that the shield wiring has a portion formed at the same pitch and width as the adjacent portion of the first or second electrode. An analog-to-digital converter according to claim 5,
An analog-to-digital converter, wherein a shield wiring having a portion formed at the pitch and width is further formed on the outer side of the shield wiring. The analog-to-digital converter of claim 1,
Peripheral wiring having portions formed at the same pitch and width as the first and second electrodes is formed in the periphery of the first and second electrodes,
An analog-to-digital converter, wherein a semiconductor element is formed in a region overlapping with the peripheral wiring in a peripheral portion of the analog switch. The analog-to-digital converter of claim 1,
The capacitive element further includes third and fourth electrodes connected to the first and second electrodes, respectively.
The analog-digital converter, wherein the third and fourth electrodes are formed in a layer between the layer in which the first and second electrodes are formed and the analog switch. 9. The analog to digital converter of claim 8, comprising:
An analog-digital converter, wherein the first electrode and the third electrode, and the second electrode and the fourth electrode are formed so as to overlap each other. 9. The analog to digital converter of claim 8, comprising:
The analog-digital converter, wherein the first electrode and the fourth electrode, and the second electrode and the third electrode are formed so as to overlap each other. The analog-to-digital converter of claim 1,
An analog-to-digital converter, wherein another analog switch is formed in a region overlapping the first and second electrodes in a peripheral portion of the analog switch. An analog switch having a P-channel transistor and an N-channel transistor formed on a semiconductor substrate;
A capacitive element having first and second electrodes;
Have
The source region of the P-channel transistor is connected to the drain region of the N-channel transistor, and the source region of the N-channel transistor is connected to the drain region of the P-channel transistor. Electrodes are connected,
The first and second electrodes are
It is formed in a region overlapping with the analog switch in a layer different from the analog switch,
A capacitive element having a predetermined capacitance is configured by arranging a plurality of unit capacitive element cells formed in a comb pattern different from the arrangement pattern of the source region and the drain region of the P-channel transistor and the N-channel transistor. Design method of analog-digital converter.

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