JP2009212457A - Sample-hold circuit, integrated circuit device, electro-optic device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sample-hold circuit, an integrated circuit, an electro-optic device, and electronic equipment capable of achieving a proper sample hold operation while suppressing the circuit scale. <P>SOLUTION: The sample-hold circuit includes: an operational amplifier; a sampling capacitor provided between an input node of the sample-hold circuit and a summing node that is a node of a first input terminal of the operational amplifier; and a feedback switch element provided between an output terminal and the summing node of the operation amplifier and constructed with a transfer gate. The feedback switch element includes a feedback P type transistor TFP and a feedback N type transistor TFN whose drain is connected to a summing node line LNEG. A shield pattern SLA1 is formed in a region between drain contacts CDP, CDN of a feedback P type transistor TFP and a feedback N type transistor TFN and source contacts CSP and CSN. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a sample hold circuit, an integrated circuit device, an electro-optical device, an electronic apparatus, and the like.

  Conventionally, a sample hold circuit that samples and holds an analog input signal is known. In this sample and hold circuit, a feedback switch element provided between an output terminal and an input terminal (for example, an inverting input terminal) of an operational amplifier is turned on during a sampling period, and a charge corresponding to the voltage of the input signal is used for sampling. Accumulate in a capacitor. In the hold period, the feedback switch element is turned off, and a voltage corresponding to the charge accumulated in the sampling capacitor is output to the output terminal of the operational amplifier.

  In this sample and hold circuit, the feedback switch element is constituted by a transfer gate composed of a P-type transistor and an N-type transistor. It has been found that there is a problem that correct sample and hold operation cannot be realized due to the gate-drain capacitance of these P-type transistors and N-type transistors. In order to solve such a problem, a method of devising the timing of switching control or providing another additional circuit is also conceivable, but this leads to a complicated circuit and a large scale.

  Conventionally, simple matrix liquid crystal panels and switching elements such as thin film transistors have been used as electro-optical panels used in electronic devices such as mobile phones, televisions, and projectors (projection display devices). An active matrix type liquid crystal panel or the like is known. In recent years, electro-optical panels using light emitting elements such as EL (Electro Luminescence) have also been in the limelight.

  In recent years, the number of data lines (source lines) of the electro-optical panel has increased due to the increase in the screen size of the electro-optical panel and the increase in the number of pixels. On the other hand, high precision of the voltage applied to each data line is required. Yes. Furthermore, due to the demand for low power consumption and light weight and small size of electronic devices equipped with electro-optic panels, it is required to reduce the power consumption of data drivers (source drivers) that drive data lines and to reduce the chip size. Yes.

  For example, Patent Document 1 and Patent Document 2 disclose that a rail-to-rail operation of an output circuit that drives a data line of a data driver is enabled, while a voltage is accurately applied to the data line. The structure which can supply is disclosed.

  However, in the technologies disclosed in Patent Document 1 and Patent Document 2, each output circuit is equipped with an auxiliary circuit to control the driving capability to realize rail-to-rail operation. Therefore, it is necessary to mount an auxiliary circuit as an additional circuit, and there is a problem that the circuit scale of the data driver becomes large. In addition, in order to suppress variations in voltage applied to the data line, it is necessary to increase the size of the transistor, which increases the chip size.

  Patent Document 3 discloses a layout method for reducing the chip size by arranging a data driver block and a memory block adjacent to each other along the long side direction of the integrated circuit device. However, even with this layout method, the achievement of the problem of both reducing the chip size and improving the display characteristics has been insufficient.

In any of Patent Documents 1 to 3, the data line of the electro-optical panel is driven by a voltage follower-connected operational amplifier. For this reason, the offset voltage of the operational amplifier causes problems such as display unevenness and deterioration of display characteristics.
JP 2005-175811 A JP 2005-175812 A JP 2007-243125 A

  According to some aspects of the present invention, it is possible to provide a sample and hold circuit, an integrated circuit device, an electro-optical device, and an electronic apparatus that can realize an appropriate sample and hold operation while suppressing an increase in circuit scale.

  The present invention relates to a sampling capacitor provided between an operational amplifier, an input node of a sample and hold circuit, and a summing node that is a node of a first input terminal of the operational amplifier, an output terminal of the operational amplifier, A feedback switch element provided between the summing node and configured by a transfer gate, wherein the feedback switch element has a summing node line that is a line of the summing node electrically connected to a drain thereof. A feedback P-type transistor, and a feedback N-type transistor whose summing node line is electrically connected to its drain. The feedback P-type transistor, the drain contact of the feedback N-type transistor, and the feedback P-type transistor, source contact of the feedback N-type transistor In the region between, related to the sample hold circuit shielding pattern is formed.

  According to the present invention, the summing node line is connected to the drains of the feedback P-type transistor and the feedback N-type transistor constituting the feedback switch element. A shield pattern is formed between the drain contact provided at the drain of the feedback P-type transistor and the feedback N-type transistor and the source contact provided at the source of the feedback P-type transistor and the feedback N-type transistor. Is done. This makes it possible to effectively shield the summing node line electrically connected to the drains of the feedback P-type transistor and the feedback N-type transistor via the drain contact, for example, in the planar direction. Therefore, the parasitic capacitance between the summing node line and the other signal lines can be minimized, and an appropriate sample-and-hold operation can be realized while suppressing an increase in circuit scale.

  In the present invention, the direction from the source of the feedback P-type transistor to the drain of the feedback P-type transistor is the first direction, and the direction orthogonal to the first direction is the second direction. In addition, a drain connection line connected to the drain contact of the feedback P-type transistor and the feedback N-type transistor is wired along the second direction, and the feedback P-type transistor and the feedback N-type are connected. A source connection line connected to the source contact of the transistor is wired along the second direction, and in a region between the drain connection line and the source connection line, a shield line as the seal pattern is Wiring may be performed along the second direction.

  According to this configuration, the parasitic capacitance between the drain connection line, which is the summing node line, and the other signal line is minimized by the shield pattern wired in parallel with the drain connection line along the second direction. It becomes possible.

  In the present invention, the shield pattern may be formed of the same metal layer as the drain connection line.

  In this way, the shield in the planar direction can be made more reliable.

  In the present invention, a second shield pattern formed of a metal layer above the metal layer forming the shield pattern may be formed to overlap the shield pattern and the drain connection line.

  This makes it possible to effectively shield the summing node line in the upward direction.

  In the present invention, the shield pattern may be formed so as to overlap the gates of the feedback P-type transistor and the feedback N-type transistor.

  In this way, the parasitic capacitance between the gate of the feedback P-type transistor and the feedback N-type transistor and the summing node line can be reduced.

  In the present invention, the sampling switch element provided between the input node of the sample hold circuit and the sampling capacitor, a connection node between the sampling switch element and the sampling capacitor, and the operational amplifier And a flip-around switch element provided between the output terminal and the output terminal.

  In this way, a flip-around sample-and-hold circuit can be realized, and so-called offset free can be realized.

  In the present invention, when the direction orthogonal to the first direction is the second direction, the sampling capacitor is disposed in the second direction of the sampling switch element and the flip-around switch element. The sampling switch element and the flip-around switch element may be disposed between the operational amplifier and the feedback switch element and the sampling capacitor.

  In this way, since an efficient layout arrangement can be realized, for example, the layout width in the second direction of the sample and hold circuit can be reduced. Further, since the sampling capacitor can be arranged in a region different from the sampling switch element, the operational amplifier, and the feedback switch element, it is possible to obtain appropriate capacitor characteristics of the sampling capacitor.

  In the present invention, the summing node line is wired along the second direction over the switch element region where the sampling switch element and the flip-around switch element are formed, and one end of the sampling capacitor is provided. May be connected.

  If the summing node line is wired in this way, the summing node line can be connected to one end of the sampling capacitor formed in a region separated from the region of the operational amplifier and the switch element.

  In the present invention, a line wired to the switch element region of the summing node line is higher than a metal layer forming a line formed in the operational amplifier region of the summing node line. It may be formed of a metal layer.

  In this way, the summing node line can be connected to one end of the sampling capacitor with a simple wiring even when the layout arrangement in which the switching element region is provided between the operational amplifier region and the capacitor region is adopted. It becomes possible.

  In the present invention, a shield pattern for a switch element region may be formed in a lower layer of a line wired to the switch element region in the summing node line.

  This makes it possible to minimize the parasitic capacitance between the summing node line and other signal lines in the switch element region.

  In the present invention, when the direction opposite to the second direction is the fourth direction, an analog reference power supply voltage line that is an analog reference power supply voltage line set to the second terminal of the operational amplifier is: Wiring may be performed along the first direction in the fourth direction of the summing node line.

  In this way, the shield on the fourth direction side of the summing node line can be realized by effectively utilizing the analog reference power supply voltage line.

  In the present invention, a bias signal line for supplying a bias signal to the operational amplifier may be wired along the first direction in the fourth direction of the analog reference power supply voltage line.

  In this way, it is possible to prevent the voltage fluctuation of the bias signal from being transmitted to the summing node line, thereby realizing an appropriate sampling operation.

  According to the present invention, as the sampling switch element, a first sampling switch element provided between a first input node and a first connection node of the sample hold circuit, and a second of the sample hold circuit are provided. A second sampling switch element provided between the input node and the second connection node is provided, and the sampling capacitor is provided between the first connection node and the summing node. A first sampling capacitor; a second sampling capacitor provided between the second connection node and the summing node; and the first connection node as the flip-around switch element. And a first flip-around switch element provided between the operational amplifier and the output terminal of the operational amplifier; A second flip-around switch element may be provided which is provided between the output terminal of said operational amplifier and said second connection node.

  In this way, by controlling the amount of charge accumulated in the first and second sampling capacitors, for example, a new voltage different from the input voltage can be generated.

  The present invention also relates to an integrated circuit device including any of the sample and hold circuits described above.

  The present invention also relates to an electro-optical device including the integrated circuit device described above.

  The present invention also relates to an electronic apparatus including the electro-optical device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of Sample and Hold Circuit First, the circuit configuration of the sample and hold circuit of this embodiment will be described. The sample hold circuit of this embodiment has a function of sampling an input signal (input voltage) in a sampling period, for example, and holding the sampled signal (voltage) in the hold period.

  FIG. 1A shows a basic configuration of the sample and hold circuit of this embodiment. As shown in FIG. 1A, this sample and hold circuit includes at least an operational amplifier OP1, a sampling capacitor CS, and a feedback switch element SF. It should be noted that modifications such as omitting some of these components, changing the connection relationship of these components, and adding other components are also possible. For example, the sample and hold circuit of the present embodiment can include other circuit elements necessary for the sampling operation and the hold operation in addition to the components shown in FIG. 1A. For example, the switch elements other than the feedback switch element (Transfer gate), capacitors other than sampling capacitors, and the like may be included.

  The sampling capacitor CS is a summing node NEG (negative node, non-inverting input terminal node, reference node) that is a node of the input node NI of the sample hold circuit and the inverting input terminal (first input terminal in a broad sense) of the operational amplifier OP1. Node). The capacitor CS accumulates charges according to the input voltage VI of the input node NI during the sampling period.

  The feedback switch element SF is provided between the output terminal of the operational amplifier OP1 and the summing node NEG. As shown in FIG. 1B, the feedback switch element SF is constituted by a transfer gate, and this transfer gate includes a feedback P-type transistor TFP and a feedback N-type transistor TFN. The P-type transistor TFP and the N-type transistor TFN are electrically connected to the drain of the summing node NEG. Further, the line of the node NQ of the output terminal of the operational amplifier OP1 is electrically connected to the source. Thus, in this embodiment, of the two terminals of the transistor, the terminal on the side to which the line of the summing node NEG is connected is called the drain of the transistor.

  The feedback switch element SF is turned on, for example, during the sampling period. In this way, the output of the operational amplifier OP1 is fed back to the node NEG of the inverting input terminal of OP1 during the sampling period. For example, the analog reference power supply voltage AGND is supplied (set) to the non-inverting input terminal (second input terminal in a broad sense) of the operational amplifier OP1. Therefore, the node NEG to which one end of the capacitor CS is connected is set to AGND by the imaginary short function of the operational amplifier OP1. As a result, a charge corresponding to the input voltage VI is accumulated in the capacitor CS. The feedback switch element SF is turned off, for example, during the hold period. Accordingly, the summing node NEG is set to, for example, the potential of AGND by the imaginary short function of the operational amplifier OP1 during the sampling period of the sample hold circuit, and is set to, for example, the floating state (high impedance state) during the hold period.

  AGND is set (adjusted) to a voltage between the high potential side power supply voltage and the low potential side power supply voltage (intermediate) of the operational amplifier OP1. Here, the high potential side power supply voltage is a voltage supplied to the source of the high potential side P-type transistor of the operational amplifier OP1, and the low potential side power supply voltage is the low potential side N-type transistor of the operational amplifier OP1. Is the voltage supplied to the source. For example, when the high potential side power supply voltage is VDDHS and the low potential side power supply voltage VSS is, for example, AGND = VSS + (VDDHS + VSS) / ML is set. If VSS = 0V and ML = 2, then AGND = (VDDHS + VSS) / 2. The coefficient ML does not necessarily need to be ML = 2, and can be adjusted as appropriate. AGND may be set to the low potential side power supply voltage (VSS).

  FIG. 2A shows a specific example of the sample hold circuit of this embodiment. FIG. 2A illustrates an example of a flip-around sample and hold circuit. Here, the flip-around sample-and-hold circuit samples, for example, charges corresponding to the input voltage VI in the sampling capacitor CS in the sampling period, and performs a flip-around operation of the sampling capacitor CS in the hold period, This is a circuit that outputs a voltage corresponding to the accumulated charge to its output node. This flip-around type sample-and-hold circuit can be used as, for example, a gradation generating amplifier or a driving amplifier of a data line driving circuit described later.

  In the sample hold circuit of FIG. 2A, in addition to the basic configuration of FIG. 1A, a sampling switch element SS and a flip-around switch element SA are provided.

  The sampling switch element SS is provided between the input node NI of the sample hold circuit and the sampling capacitor CS (connection node NS). The feedback switch element SF is provided between the output terminal of the operational amplifier OP1 and the summing node NEG. The flip-around switch element SA is provided between the connection node NS between the sampling switch element SS and the sampling capacitor CS and the output terminal of the operational amplifier OP1.

  Next, the operation of the sample and hold circuit in FIG. 2A will be described with reference to FIGS.

  In the sampling period, the sampling switch element SS and the feedback switch element SF are turned on, and the flip-around switch element SA is turned off. As a result, as shown in FIG. 3A, the output of the operational amplifier OP1 is fed back to the node NEG of the inverting input terminal of OP1. Further, the analog reference power supply voltage AGND is supplied to the non-inverting input terminal (second input terminal) of the operational amplifier OP1. Therefore, the node NEG to which one end of the capacitor CS is connected is set to AGND by the imaginary short function of the operational amplifier OP1. As a result, a charge corresponding to the input voltage VI is accumulated in the capacitor CS.

  On the other hand, in the hold period, the sampling switch element SS and the feedback switch element SF are turned off, and the flip-around switch element SA is turned on. As a result, as shown in FIG. 3B, the sample and hold circuit outputs an output voltage VQ corresponding to the charge accumulated in the sampling capacitor CS during the sampling period to the output node NQ. Specifically, an output voltage VQ corresponding to the electric charge accumulated in CS is obtained by performing a flip-around operation in which the other end of the capacitor CS having one end connected to the node NEG is connected to the output terminal of the operational amplifier OP1. Is output.

  By using the flip-around type sample-and-hold circuit as described above, so-called offset-free can be realized as will be described in detail later. Therefore, for example, when the sample and hold circuit of the present embodiment is applied to a data line driving circuit, variations in output voltage between data lines can be minimized. Thereby, a highly accurate voltage with little variation can be supplied to the data line, and display quality can be improved. In addition, since DAC driving for directly driving the data line by the D / A conversion circuit is not necessary, high-speed driving and simplification of control can be realized.

  In the following description, the flip-around type of FIG. 2A is mainly described as an example of the sample and hold circuit, but the sample and hold circuit of the present embodiment is not limited to this. For example, FIG. 2B illustrates another configuration example of the sample and hold circuit.

  In FIG. 2B, the flip-around switch element SA of FIG. 2A is not provided. One end of the sampling switch element SS is connected to the input node NI during the sampling period, and is connected to the AGND node during the hold period. A feedback capacitor may be provided between the summing node NEG and the output node NQ.

  In the sample hold circuit of FIG. 2B, both the sampling switch element SS and the feedback switch element SF are turned on during the sampling period. As a result, charges corresponding to the input voltage VI are accumulated in the sampling capacitor CS. On the other hand, in the hold period, one end of the sampling capacitor CS is set to AGND by the sampling switch element SS, and the feedback switch element SF is turned off.

  2A and 2B are examples of a single end type, but a differential type configuration as shown in FIG. 2C may be used. In FIG. 2C, sampling switches SSP, SSN, sampling capacitors CSP, CSN, feedback switch element SFP, corresponding to the first and second signals VIP, VIN constituting the differential signal, respectively. An SFN is provided. The operational amplifier OPD is a differential input / differential output type amplifier.

2. As shown in FIG. 1B, parasitic capacitances CP5 and CP6 are provided between the gates of the feedback P-type transistor TFP and N-type transistor TFN and the summing node NEG, respectively. Exists. A parasitic capacitance CP7 exists between the output node NQ and the summing node NEG of the sample and hold circuit.

  For example, a negative logic hold control signal that is L level during the hold period is input to the gate of the feedback P-type transistor TFP, and the gate of the feedback N-type transistor TFN is H level during the hold period. A positive logic hold control signal is input. Therefore, if there is a parasitic capacitance value difference CP5 to CP6 between CP5 and CP6, when the voltage level of the hold control signal is changed, an error (unbalance) of the accumulated charge is caused by clock feedthrough and charge injection. This causes a problem that correct sample and hold operation cannot be realized.

  A method for solving such a problem by, for example, a circuit device is also conceivable. However, according to this method, a new additional circuit or the like is required, and the circuit becomes large. In particular, when the sample and hold circuit is used for a gradation generation amplifier or a drive amplifier of a data line driving circuit as will be described later, it is necessary to provide a large number of sample and hold circuits in the integrated circuit device. Increase is a serious problem.

  Therefore, in the present embodiment, the layout problem as described below is adopted to solve the above problem.

  For example, FIG. 4 shows a layout arrangement example of the feedback switch element SF. The feedback switch element SF is composed of a P-type transistor TFP and an N-type transistor TFN. The drain DP of the P-type transistor TFP and the drain DN of the N-type transistor TFN are electrically connected to a summing node line LNEG that is a line of the summing node NEG. The source SP of the P-type transistor TFP and the source SN of the N-type transistor TFN are electrically connected to the line of the output node NQ of the sample and hold circuit. The gate GP of the P-type transistor TFP is electrically connected to the negative logic hold control signal line, and the gate GN of the N-type transistor TFN is electrically connected to the positive logic hold control signal line.

  In FIG. 4, a shield pattern SLA1 is formed. Specifically, a shield pattern SLA1 (shield line) is formed in a region between the drain contacts CDP and CDN of the P-type transistor TFP and N-type transistor TFN and the source contacts CSP and CSN of the P-type transistor TFP and N-type transistor TFN. ) Is formed (wired).

  Note that a shield pattern (shield line) of the present embodiment described below is set to, for example, a low potential side power supply voltage (VSS).

  For example, in FIG. 4, the direction from the source SP to the drain DP of the P-type transistor TFP (the direction from the source SN to the drain DN of the TFN) is the D1 direction (first direction), and the direction orthogonal to the D1 direction. Is the D2 direction (second direction). The direction opposite to the D1 direction is defined as the D3 direction (third direction), and the direction opposite to the D2 direction is defined as the D4 direction (fourth direction).

  In this case, in FIG. 4, the drain connection line LDA1 connected to the P-type transistor TFP for feedback and the drain contacts CDP and CDN of the N-type transistor TFN is wired along the direction D2. That is, the wiring is performed so that the longitudinal direction of the LDA1 is along the direction D2. A source connection line LSA1 connected to the source contacts CSP and CSN of the P-type transistor TFP and the N-type transistor TFN is wired along the direction D2. That is, the wiring is performed so that the longitudinal direction of LSA1 is along the direction D2.

  In the region between the drain connection line LDA1 and the source connection line LSA1, the shield line as the seal pattern SLA1 is wired along the direction D2. That is, the seal pattern SLA1 is wired so that the drain connection line LDA1 and the source connection line LSA1 are separated from the drain connection line LSA1 by at least a distance equal to or greater than the minimum distance on the design rule, and parallel to the LDA1 and LSA1 Is done. By wiring the shield pattern SLA1 in this way, the shield by SLA1 can be made more reliable.

  Note that the drain connection line LDA1, the source connection line LSA1, and the seal pattern SLA1 are not necessarily straight lines, and some of them may be bent.

  In FIG. 4, shield patterns SLA2 and SLA3 are wired so as to surround LNEG on both sides of the summing node line LNEG. In this way, it is possible to shield the summing node line LNEG so as to surround the periphery by the shield patterns SLA1, SLA2, and SLA3.

  In FIG. 4, the shield pattern SLA1 is formed of the same metal layer as the drain connection line LDA1. More specifically, the shield patterns SLA1, SLA2, and SLA3 are formed by the first metal layer M1, and the drain connection line LDA1 and the source connection line LSA1 are also formed by the first metal layer M1. Thus, the shield in the planar direction can be made more reliable by forming the same metal layer. Note that these lines may be formed of a metal layer that is higher than the first metal layer M1.

  In FIG. 4, the shield pattern SLA1 is formed so as to overlap the gates GP and GN of the P-type transistor TFP and the N-type transistor TFN. For example, the gates GP and GN are wired so that the longitudinal direction thereof is along the D2 direction. The shield pattern SLA1 formed of the first metal layer M1 above the polysilicon layer of the gates GP and GN is wired so as to overlap at least a part of the gates GP and GN in plan view. Is done.

  FIG. 5 shows an example of the wiring pattern of the metal layers M2, M3, and M4 that are higher than the first metal layer M1. In FIG. 5, a shield pattern SLA4 (second shield pattern) formed by a metal layer M2 that is an upper layer than the metal layer M1 that forms the shield pattern SLA1 and the like is wired. Specifically, the shield pattern SLA4 is formed so as to overlap the shield pattern SLA1 and the drain connection line LDA1. That is, the shield pattern SLA4 formed by the second metal layer M2 above SLA1 and LDA1 is wired so as to overlap the shield pattern SLA1 and the drain connection line LDA1 in plan view. The shield pattern SLA4 is formed so as to overlap with the summing node line LNEG and the shield patterns SLA2 and SLA3 of the first metal layer M1 formed on both sides of the LNEG in a plan view. .

  According to the layout method of the present embodiment described above, it is possible to effectively shield the summing node line LNEG in the plane direction (horizontal direction). That is, as shown in FIG. 4, since the shield patterns SLA1, SLA2, and SLA3 are formed around the summing node line LNEG, the parasitic capacitance between the other signal lines and the LNEG can be minimized.

  For example, the gate connection lines LGP and LGN connected to the gates GP and GN of the transistors TFP and TFN are formed of the same metal layer M1 as the summing node line LNEG. Therefore, if the shield pattern SLA1 does not exist, the parasitic capacitance between the gate connection lines LGP and LGN and the summing node line LNEG cannot be ignored. Therefore, the wiring pattern dependency occurs in the parasitic capacitance value difference CP5 to CP6 in FIG. As a result, when the voltage level of the hold control signal supplied to the gate connection lines LGP and LGN changes, an error of accumulated charge occurs due to clock feedthrough and charge injection, and a correct sample and hold operation cannot be realized. .

  In this regard, according to the layout method of the present embodiment, the shield pattern SLA1 is formed between the drain contacts CDP, CDN and the source contacts CSP, CSN, and therefore, between the summing node line LNEG and the gate connection lines LGP, LGN. Can be minimized, and the absolute value of the parasitic capacitance can be reduced. Accordingly, the parasitic capacitance value difference CP5 to CP6 in FIG. 1B can be reduced, and the wiring pattern dependency of the parasitic capacitance value difference CP5 to CP6 can be eliminated. As a result, it is possible to prevent the accumulated charge from being generated and to realize a correct sample and hold operation. Further, in FIG. 5, since the shield pattern SLA4 is formed so as to overlap the gates GP and GN of the transistors TFP and TFN, the parasitic capacitance between the gates GP and GN and the summing node line LNEG can be reduced. .

  Further, according to the layout method of the present embodiment, the distance between the gates GP and GN and the drain contacts CDP and CDN is slightly separated, and the shield pattern SLA1 is simply wired in the space generated thereby. Therefore, for example, there is an advantage that an appropriate sample-and-hold operation can be realized while minimizing the scale of the circuit, as compared with a method in which an additional circuit is provided to prevent clock feedthrough or the like by circuit contrivance.

  Further, as shown in FIG. 5, the shield pattern SLA1, SLA2, SLA3, the drain connection line LDA1, and the summing node line LNEG are further formed with a shield pattern SLA4 to effectively shield the LNEG in the upward direction. become. That is, the summing node line LNEG can be shielded not only in the plane direction but also in the upward direction, and the parasitic capacitance between the other signal lines and the LNEG can be minimized.

  The layout method of the feedback switch element SF of the present embodiment is not limited to FIGS. 4 and 5, and various modifications can be made. For example, FIGS. 6A, 6B, and 7 show other layout arrangement examples.

  Also in FIG. 6A, the shield pattern SLB1 is formed between the drain contacts CDP and CDN of the transistors TFP and TFN and the source contacts CSP and CSN.

  Also, drain connection lines LDB1 and LDB2 connected to the drain contacts CDP and CDN of the transistors TFP and TFN are wired along the direction D2, and source connection lines LSB1 and LSB2 connected to the source contacts CSP and CSN are connected in the direction D2. Wired along. The seal pattern SLB1 is wired along the direction D2 between the drain connection lines LDB1 and LDB2 and the source connection lines LSB1 and LSB2. Further, a shield pattern SLB2 is formed along the direction D2 in the direction D1 of the drain connection lines LDB1 and LDB2 (CDP, CDN). A shield pattern SLB3 is formed along the direction D2 in the direction D3 of the source connection lines LSB1 and LSB2 (CSP, CSN). In FIG. 6B, the shield pattern SLB4 is formed so as to overlap the gates GP and GN of the transistors TFP and TFN.

  Further, the shield pattern SLB1 in FIG. 6A is formed of the metal layer M1 which is the same layer as the drain connection lines LDB1 and LDB2. As shown in FIG. 6B, the second shield pattern SLB4 formed of the metal layer M2 above the metal layer forming the shield pattern SLB1 is formed so as to overlap the shield pattern SLB1 and the like. The

  As shown in FIG. 7, in this layout example, the drain connection line LDB3 and the source connection line LSB3 formed of the metal layer M3 above the metal layers M1 and M2 are wired along the direction D2.

  The drain connection line LDB3 formed of the metal layer M3 is connected to the drain connection lines LDB1 and LDB2 of FIG. 6A formed of the lower metal layer M1 through contacts (via contacts). As a result, the electrical connection between the drain DP of the P-type transistor TFP and the drain DN of the N-type transistor TFN becomes possible.

  The source connection line LSB3 formed of the metal layer M3 is connected to the source connection lines LSB1 and LSB2 shown in FIG. 6A formed of the lower metal layer M1 through contacts. As a result, the source SP of the P-type transistor TFP and the source SN of the N-type transistor TFN can be electrically connected.

  In FIG. 7, the shield pattern SLB5 formed of the metal layer M3 is wired along the direction D2 in the region between the drain connection line LDB3 and the source connection line LSB3 formed of the metal layer M3. A shield pattern SLB6 formed of the metal layer M3 is wired along the D2 direction in the D1 direction of the drain connection line LDB3, and is formed of the metal layer M3 along the D2 direction in the D3 direction of the source connection line LSB3. The shield pattern SLB7 is wired. By wiring in this way, it is possible to effectively shield the drain connection line LDB3 serving as the summing node line LNEG in the planar direction. The shield patterns SLB5, SLB6, and SLB7 also function as shields in the upward direction of the drain connection lines LDB1 and LDB2 and the gates GP and GN, so that a more effective shield can be achieved.

3. Overall Layout Arrangement of Sample and Hold Circuit Next, the overall layout arrangement of the sample and hold circuit of this embodiment will be described. In the following description, the flip-around type sample-and-hold circuit described with reference to FIG. Further, since the layout near the feedback switch element SF is shown in detail in FIGS. 4 and 5, for example, in FIGS. 10, 12, and 18, which will be described later, the layout near the feedback switch element SF is simplified. It shows.

  FIG. 8A shows a more detailed configuration example of the sample hold circuit of FIG. As shown in FIG. 8A, the sampling switch element SS includes a transfer gate including a sampling P-type transistor TSP and a sampling N-type transistor TSN. The flip-around switch element SA includes a transfer gate including a flip-around P-type transistor TAP and a flip-around N-type transistor TAN. The feedback switch element SF includes a transfer gate including a feedback P-type transistor TFP and a feedback N-type transistor TFN.

  FIG. 8B shows a detailed configuration example of the operational amplifier OP1. The operational amplifier OP1 includes a differential unit DIF (differential stage) and an output unit QQ (output stage). The operational amplifier OP1 is not limited to the configuration shown in FIG. For example, the amplifier is not limited to the class A operation amplifier as shown in FIG. 8B, but may be a class AB operation amplifier. For example, the class A operation is performed in the sampling period, and the class AB operation is performed in the hold period. An amplifier that performs the following may be used.

  The differential unit DIF of the operational amplifier OP1 includes P-type (first conductivity type in a broad sense) transistors TB1 and TB2 constituting a current mirror circuit and N-type (second conductivity in a broad sense) constituting a differential pair transistor. Side) transistors TB3 and TB4 and an N-type transistor TB5 serving as a current source. Here, the gates of the transistors TB1 and TB2 are commonly connected to the node NB2. The summing node NEG is connected to the gate of the transistor TB3 on the inverting input terminal side, and the analog reference power supply voltage AGND is supplied to the gate of the transistor TB4 on the non-inverting input terminal side. A bias signal BS1 (bias voltage) from a bias circuit (not shown) is supplied to the gate of the transistor TB5.

  The output part QQ of the operational amplifier OP1 includes a P-type transistor TB6 and an N-type transistor TB7 connected in series. The output node NB3 of the differential unit DIF is connected to the gate of the transistor TB6 serving as the driving transistor. A bias signal BS2 (bias voltage) from a bias circuit (not shown) is supplied to the gate of the transistor TB7 serving as a current source.

  As shown in FIG. 8A, a parasitic capacitance (capacitance between the gate and the drain) is provided between the gate of the sampling P-type transistor TSP, the gate of the N-type transistor TSN, and the connection node NS. CP1 and CP2 exist. Parasitic capacitances CP3 and CP4 exist between the gate of the flip-around P-type transistor TAP, the gate of the N-type transistor TAN, and the connection node NS, respectively. Parasitic capacitances CP5 and CP6 exist between the gate of the feedback P-type transistor TFP, the gate of the N-type transistor TFN, and the summing node NEG, respectively.

  For example, a negative logic sampling control signal is input to the gate of the sampling P-type transistor TSP, and a positive logic sampling control signal is input to the gate of the N-type transistor TSN. Therefore, if there is a parasitic capacitance value difference CP1−CP2 between CP1 and CP2, when the voltage level of the sampling control signal changes, an error (unbalance) of accumulated charges occurs due to clock feedthrough, etc. Correct sample and hold operation cannot be realized. The same applies when a parasitic capacitance value difference CP3-CP4 exists between CP3 and CP4, or when a parasitic capacitance value difference CP5-CP6 exists between CP5 and CP6 as described above. Therefore, it is desirable to arrange the layout of the transistors TSP, TSN, TAP, TAN, etc. so that these parasitic capacitance value differences are smaller than a predetermined value. Further, even when the capacitance value of the parasitic capacitance CP7 between the output node NQ and the summing node NEG is large, there is a possibility that a correct sample and hold operation cannot be realized. Therefore, it is desirable to perform the layout arrangement so that the parasitic capacitance value is smaller than a predetermined value.

  Therefore, in this embodiment, a layout arrangement method as described below is adopted. Specifically, in the cross-sectional view of the integrated circuit device of FIG. 9, the N-type transistors TB3, TB4, TB5, and TB7 constituting the operational amplifier OP1 of FIG. 8B are formed in the first P-type well PWL1. . Further, the P-type transistors TB1, TB2, and TB6 constituting the operational amplifier OP1 are formed in the first N-type well NWL1.

  The N-type transistors TSN and TAN constituting the sampling switch element SS and the flip-around switch element SA are formed in the second P-type well PWL2. The second P-type well PWL2 is a well formed separately from the first P-type well PWL1, for example.

  The P-type transistors TSP and TAP constituting the sampling switch element SS and the flip-around switch element SA are formed in the second N-type well NWL2. The second N-type well NWL2 is a well formed separately from the first N-type well NWL1, for example.

  Specifically, as shown in FIG. 9, a high concentration N-type well DNWL is formed in a silicon substrate. A P-type well PWL1, an N-type well NWL1, a P-type well PWL2, and an N-type well NWL2 are formed on the N-type well DNWL. For example, a P-type well PWL1, an N-type well NWL1, a P-type well PWL2, and an N-type well NWL2 are arranged along the direction D2. That is, the N-type well NWL1 is formed in the D2 direction of the P-type well PWL1, the P-type well PWL2 is formed in the D2 direction of NWL1, and the N-type well NWL2 is formed in the D2 direction of PWL2. The P-type wells PWL1 and PWL2 are set to a low-potential side power supply voltage via a P + impurity layer (not shown), and the N-type wells NWL1 and NWL2 are set to a high-potential side power supply voltage via an N + impurity layer (not shown). Is set.

  FIG. 10 shows a planar layout arrangement example of the sample and hold circuit of the present embodiment. The layout arrangement of the present embodiment is not limited to the arrangement shown in FIG. 10, and various modifications can be made.

  As shown in FIG. 10, the operational amplifier OP1 is formed in the operational amplifier region OPR, and the sampling switch element SS and the flip-around switching element SA are formed in the switch element region SWR. The switch element region SWR is formed in the direction D2 of the operational amplifier region OPR. The sampling switch element SS and the flip-around switch element SA are arranged along the direction D1 in the switch element region SWR.

  Here, the switch elements SS and SA have a symmetrical layout arrangement. Specifically, the switch elements SS and SA are arranged in line symmetry (including the case of almost line symmetry) with the center line along the direction D2 passing through the middle of the switch elements SS and SA as the axis of symmetry. Similarly, the switch elements SS and SA are arranged in line symmetry with the center line along the direction D1 passing through the middle of the switch elements SS and SA as the axis of symmetry. Then, as indicated by H1 in FIG. 10, a summing node line LNEG that is a line of the summing node NEG is wired along the direction D2 so as to avoid these switch elements SS and SA.

  As shown in FIG. 10, in the operational amplifier region OPR, P-type transistors TB6, TB1, and TB2 of the operational amplifier OP1 of FIG. 8B are arranged along the direction D1. N-type transistors TB7, TB3, and TB4 are arranged along the D1 direction in the D4 direction of P-type transistors TB6, TB1, and TB2, and a transistor TB5 is arranged in the D4 direction of TB7, TB3, and TB4.

  In FIG. 10, N-type transistors TB3, TB4, TB5, and TB7 constituting the operational amplifier OP1 are formed in the first P-type well PWL1, and the P-type transistors TB1, TB2, and TB6 constituting the operational amplifier OP1 are It is formed in the first N-type well NWL1. Note that the P-type transistor TFP and the N-type transistor TFN constituting the feedback switch element SF are also arranged in the operational amplifier region OPR. Specifically, the transistors TFP and TFN are arranged in the direction D3 of the transistors TB1 to TB7 constituting the operational amplifier OP1.

  The summing node line LNEG connected to the gate node of the transistor TB3 is wired in the operational amplifier region OPR as a lead line LDR for the metal layer (conductive layer in a broad sense) along the direction D1, as indicated by H2.

  In addition, the summing node line LNEG has a metal layer (upper layer than the metal layer (for example, the first or second metal layer M1, M2) of the lead line LDR) via a contact (via contact) or the like at a position indicated by H3. For example, it is wired as a line formed of the fourth metal layer M4).

  The summing node line LNEG is wired along the direction D2 so as to avoid the switch elements SS and SA in the switch element region SWR, as indicated by H1 in FIG.

  In H4 of FIG. 10, the line of the output node NQ of the operational amplifier OP1 and the summing node line LNEG intersect. In FIG. 8A, it is desirable that the capacitance value of the parasitic capacitance CP7 between the output node NQ and the summing node NEG is as small as possible. Therefore, in H4 of FIG. 10, a shield pattern SLD1 (shield line) is formed below the summing node line LNEG. The shield pattern SLD1 is formed of, for example, a third metal layer M3 below the fourth metal layer M4 that forms the summing node line LNEG. By providing such a shield pattern SLD1, the capacitance value of the parasitic capacitance CP7 in FIG. 8A can be minimized.

  In FIG. 10, the switch element region SWR includes a sampling P-type transistor TSP and an N-type transistor TSN that constitute the sampling switch element SS, and a flip-around P-type transistor that constitutes the flip-around switch element SA. A TAP and N-type transistor TAN are arranged. For example, the transistor TSP is arranged in the direction D2 of the transistor TSN, and the transistor TAP is arranged in the direction D2 of the transistor TAN. The transistors TSP and TAP are arranged along the direction D1, and the transistors TSN and TAN are also arranged along the direction D1. As described above, in FIG. 10, the transistors TSP, TSN, TAP, and TAN constituting the switch element have a symmetrical layout arrangement.

  In FIG. 10, the N-type transistors TSN and TAN constituting the sampling switch element SS and the flip-around switch element SA are arranged in the second P-type well PWL2. On the other hand, the P-type transistors TSP and TAP constituting the sampling switch element SS and the flip-around switch element SA are arranged in the second N-type well NWL2. That is, the transistors constituting the switch element are arranged in a region separated from the operational amplifier arrangement region by the well.

  As indicated by H5 in FIG. 10, in the switch element region SWR (P-type well PWL2 and N-type well NWL2), a shield pattern SLD2 (shield line) is formed below the summing node line LNEG. The shield pattern SLD2 is formed of, for example, a third metal layer M3 below the fourth metal layer M4 that forms the summing node line LNEG. By providing such a shield pattern SLD2, for example, the capacitance value of the parasitic capacitance formed between the gate control line or the like and the summing node line LNEG can be minimized, and deterioration of circuit characteristics can be prevented.

  In this embodiment, as indicated by H6 in FIG. 10, the sampling control lines LSP and LSN are wired in the D2 direction in the D3 direction of the summing node line LNEG (including the lead line LDR). As shown at H7 in FIG. 10, flip-around control lines LAP and LAN are wired along the D2 direction in the D1 direction of the summing node line LNEG. In other words, the sampling control lines LSP and LSN, the flip-around control line LAP and LAN are wired along the direction D2, and the area between these control lines LSP and LSN and the control lines LAP and LAN. , The summing node line LNEG is wired along the D2 direction or the like.

  Here, the sampling control lines LSP and LSN are lines for supplying a sampling control signal for controlling on / off of the sampling switch element SS. The sampling control lines LSP and LSN are formed by, for example, a fourth metal layer M4 which is the same metal layer as the summing node line LNEG.

  On the other hand, the flip-around control lines LAP and LAN are lines for supplying flip-around control signals for controlling on / off of the flip-around switch element SA. The flip-around control lines LAP and LAN are formed of, for example, a fourth metal layer M4 that is the same metal layer as the summing node line LNEG.

  The sampling P-side control line LSP among the sampling control lines LSP and LSN is a line for supplying a negative logic sampling control signal. That is, for example, a negative logic sampling control signal in which the L level becomes active is supplied.

  As indicated by H8 in FIG. 10, the sampling P-side control line LSP is connected to the sampling P-side gate control line LGSP. The gate control line LGSP is electrically connected to the gate of the sampling P-type transistor TSP. Therefore, when the control line LSP becomes L level, the gate control line LGSP becomes L level, and the P-type transistor TSP is turned on.

  On the other hand, the sampling N-side control line LSN among the sampling control lines LSP and LSN is a line for supplying a positive logic sampling control signal. That is, for example, a positive logic sampling control signal in which the H level becomes active is supplied. Therefore, when the sampling P-side control line LSP is at the L level, the sampling N-side control line LSN is at the H level.

  As indicated by H9 in FIG. 10, the sampling N-side control line LSN is connected to the sampling N-side gate control line LGSN. The gate control line LGSN is electrically connected to the gate of the sampling N-type transistor TSN. Therefore, when the control line LSN becomes H level, the gate control line LGSN becomes H level and the N-type transistor TSN is turned on.

  The flip-around P-side control line LAP of the flip-around control line LAP and LAN is a line for supplying a negative logic flip-around control signal. That is, for example, a negative logic flip-around control signal in which the L level becomes active is supplied.

  As indicated by H10 in FIG. 10, the flip-around P-side control line LAP is connected to the flip-around P-side gate control line LGAP. The gate control line LGAP is electrically connected to the gate of the flip-around P-type transistor TAP. Therefore, when the control line LAP becomes L level, the gate control line LGAP becomes L level, and the P-type transistor TAP is turned on.

  On the other hand, the flip-around N-side control line LAN among the flip-around control lines LAP and LAN is a line for supplying a positive logic flip-around control signal. That is, for example, a positive logic flip-around control signal in which the H level becomes active is supplied. Accordingly, when the flip-around P-side control line LAP is at the L level, the flip-around N-side control line LAN is at the H level.

  As shown at H11 in FIG. 10, the flip-around N-side control line LAN is connected to the flip-around N-side gate control line LGAN. The gate control line LGAN is electrically connected to the gate of the flip-around N-type transistor TAN. Therefore, when the control line LAN becomes H level, the gate control line LGAN becomes H level, and the N-type transistor TAN is turned on.

  According to the layout arrangement of this embodiment of FIG. 10, the summing node line LNEG is wired in the region between the sampling control lines LSP and LSN and the flip-around control line LAP and LAN. Therefore, the parasitic capacitance between the control lines LSP, LSN, LAP, LAN and the summing node line LNEG (LDR) can be minimized. Therefore, even if the voltage of these control lines LSP, LSN, LAP, and LAN changes with a full swing for sampling control and flip-around control, the adverse effect of this voltage change on the summing node line LNEG is minimized. To the limit. As a result, the potential of the summing node NEG that is in a floating state during the hold operation can be stabilized, and deterioration of circuit characteristics can be prevented.

  Further, according to the layout arrangement of FIG. 10, layout wiring with high symmetry between the control lines LSP and LSN and the control lines LAP and LAN becomes possible. Thereby, the imbalance of the parasitic capacitance of the control line can be reduced, and the circuit characteristics can be improved.

  In FIG. 10, the negative logic sampling control line LSP and the positive logic sampling control line LSN are wired in parallel in close proximity along the direction D2. Therefore, the parasitic capacitance added to the control line LSP and the parasitic capacitance added to the control line LSN can be made equal, and the unbalance of the parasitic capacitance can be reduced. In particular, by providing a dummy line as shown at H12 in FIG. 10, the unbalance of the parasitic capacitance can be further reduced.

  In FIG. 10, the negative logic flip-around control line LAP and the positive logic flip-around control line LAN are wired close to each other in parallel along the direction D2. Accordingly, the parasitic capacitance added to the control line LAP and the parasitic capacitance added to the control line LAN can be made equal, and the parasitic capacitance unbalance can be reduced. In particular, by providing a dummy line as shown at H13 in FIG. 10, the unbalance of the parasitic capacitance can be further reduced.

  In FIG. 10, the layout wiring of the sampling control lines LSP and LSN and the layout wiring of the flip-around control lines LAP and LAN are symmetric layout wirings. For example, the layout wiring is line symmetric with the center line along the direction D2 passing through the middle of the control lines LSP and LSN and the control line LAP and LAN as the axis of symmetry. Therefore, the parasitic capacitance added to the control lines LSP and LSN can be made equal to the parasitic capacitance added to the control lines LAP and LAN, and the unbalance of the parasitic capacitance between these control lines can be reduced. The circuit characteristics can be improved.

  Further, according to the layout arrangement of the present embodiment of FIG. 10, the transistors constituting the operational amplifier OP1 and the transistors constituting the sampling and flip-around switch elements SS and SA are formed in different wells. Therefore, compared to the case where these transistors are formed in the same well, the degree of freedom of layout is remarkably increased, and a layout arrangement with high symmetry of the transistors constituting the switch elements SS and SA becomes possible.

  For example, as a method of the comparative example of the present embodiment, a method of arranging transistors constituting the switch elements SS and SA in the operational amplifier region OPR can be considered. However, according to the method of this comparative example, the degree of freedom of layout arrangement of the transistors constituting the switch elements SS and SA is limited due to the transistor of the operational amplifier OP1 and its wiring. For this reason, a highly symmetrical layout arrangement of these transistors cannot be realized.

  In this regard, in the layout arrangement of FIG. 10, the transistors constituting the switch elements SS and SA can be freely arranged without being limited to the transistors of the operational amplifier OP1 and wiring thereof, so that a highly symmetrical layout arrangement is possible. Become. When the symmetry of the layout arrangement increases as described above, the unbalance of the parasitic capacitors CP1 and CP2 and the unbalance of the parasitic capacitors CP3 and CP4 in FIG. 8A can be reduced. Therefore, a layout that minimizes the parasitic capacitance value difference CP1-CP2 and the parasitic capacitance value difference CP3-CP4 is possible. As a result, it is possible to minimize the accumulated charge error caused by the difference between the capacitance values, and the circuit characteristics can be remarkably improved as compared with the method of the comparative example described above.

4). Capacitor Layout Arrangement Next, an example of capacitor layout arrangement will be described. In the cross-sectional view of the integrated circuit device of FIG. 11 and the plan view of FIG. 12, the sampling capacitor CS of FIG. 8A is arranged in the D2 direction of the sampling switch element SS and the flip-around switch element SA. The sampling switch element SS and the flip-around switch element SA are disposed between the operational amplifier OP1, the feedback switch element SF, and the sampling capacitor CS. By arranging in this way, the width of the sample and hold circuit in the D2 direction, for example, can be reduced.

  The sampling capacitor CS is formed in the third P-type well PWL3. The third P-type well PWL3 is a well formed separately from the first P-type well PWL1 and the second P-type well PWL2. Specifically, the second P-type well PWL2 and the second N-type well NWL2 are arranged between the first P-type well PWL1 and the first N-type well NWL1 and the third P-type well PWL3. Be placed.

  As shown in the cross-sectional structure of FIG. 11, the sampling capacitor CS (or an auxiliary capacitor and a phase compensation capacitor described later) is formed using the gate capacitance of the transistor.

  Specifically, a high-concentration N-type well DNWL is formed on a silicon substrate, and a P-type well PWL3 is formed on the N-type well DNWL. The low-potential side power supply voltage is supplied to the P-type well PWL3 via the P + impurity layer.

  An NCU that is an N + cross under impurity layer is formed on the P-type well PWL3. A polysilicon layer that is a gate of the transistor is formed above the NCU. This polysilicon layer becomes the upper electrode of the capacitor, and the impurity layer of the NCU becomes the lower electrode. If the capacitor structure using the NCU is used as described above, a large capacitance value can be obtained with a small layout area.

  As shown in FIG. 11, the summing node line LNEG is electrically connected to the N + impurity layer (NCU) of the capacitor. That is, the summing node line LNEG is electrically connected to an impurity layer (diffusion layer) that forms an electrode on one end side of the sampling capacitor CS. As shown in FIGS. 11 and 12, the connection node line LNS that is a line of the connection node NS is electrically connected to a polysilicon layer that is an electrode on the other end side of the capacitor CS.

  As described above, the reason why the line LNEG is connected to the impurity layer serving as the lower electrode instead of the polysilicon layer serving as the upper electrode is as follows.

  That is, the potential of the line LNEG is fixed to the potential of AGND by the imaginary short function of the operational amplifier OP1, but the potential of the line LNS swings greatly up and down around AGND. Therefore, if the line LNS is connected to the impurity region, a problem may occur in the capacitor characteristics.

  Further, when the line LNEG is connected to the polysilicon layer which is the upper electrode, the parasitic capacitance between the upper layer metal wiring and the polysilicon layer is increased. On the other hand, since the polysilicon layer is formed above the impurity layer, if the line LNEG is connected to the impurity layer, the parasitic capacitance with the upper metal wiring layer can be reduced.

  Further, although it is necessary to suppress the potential fluctuation of the line LNEG as much as possible, the potential of the polysilicon layer is more likely to vary than the potential of the impurity layer.

  Further, when the line LNEG is connected to the polysilicon layer, the capacitance of the diffusion region, which is the impurity layer, is added to the capacitance value that is the target value of the design, and the variation in the capacitance value increases.

  In FIGS. 11 and 12, since the line LNEG is connected to the impurity layer side, the above-described problems can be solved.

  As indicated by H1 in FIG. 12, the summing node line LNEG is a switching element region SWR (second P-type well PWL2 and second N-type well) which is a region of the sampling switch element SS and the flip-around switch element SS. NWL2) is wired along the direction D2. The summing node line LNEG is connected to one end of the sampling capacitor CS. Specifically, as described in FIG. 11, the summing node line LNEG is electrically connected to an N + impurity layer forming an electrode at one end of the sampling capacitor CS formed in the third P-type well PWL3. The

  On the other hand, the connection node line LNS is connected to the other end of the sampling capacitor CS. Specifically, as described with reference to FIG. 11, the connection node line LNS is electrically connected to the polysilicon layer constituting the electrode at the other end of the sampling capacitor CS. The drains of the transistors TSP, TSN, TAP, TAN constituting the switch elements SS, SA are electrically connected to the connection node line LNS.

  In addition, the line indicated by H1 in the summing node line LNEG that is wired to the switch element region SWR is more than the metal layer that forms the line indicated by H2 in the operational amplifier region OPR in the summing node line LNEG. The upper metal layer is formed. That is, the line indicated by H1 in the summing node line LNEG is formed by, for example, the metal layer M4, and the line indicated by H2 in the summing node line LNEG is formed by, for example, the metal layer M1.

  As indicated by H5, a shield pattern SLD2 for the switch element region is formed below the H1 line wired to the switch element region SWR in the summing node line LNEG. That is, the line H1 is formed of, for example, the metal layer M4, and the shield pattern SLD2 is formed of, for example, the metal layer M3.

  If the summing node line LNEG is wired as shown in FIG. 12, the summing node is connected to one end of the sampling capacitor CS formed in a region separated from the formation region of the transistors constituting the operational amplifier OP1 and the switch elements SS and SA. Line LNEG can be connected. Accordingly, the sampling capacitor CS can be formed in the separated P-type well PWL3, and appropriate capacitor characteristics can be obtained.

  Even if the summing node line LNEG is thus wired on the switch element region SWR (P-type well PWL2, N-type well NWL2), the switch element region is below the summing node line LNEG as indicated by H5. A shield pattern SLD2 is formed. For this reason, the parasitic capacitance between the wirings in the switch element region can be minimized, and deterioration of circuit characteristics can be prevented.

  As indicated by H2 in FIG. 12, in the operational amplifier region OPR, the summing node line LNEG is formed by the lower metal layer M1 and wired. The wiring layer of the summing node line LNEG is changed via a contact as indicated by H3, and the switching element region SWR is wired by the upper metal layer M4 as indicated by H1. In this manner, even when the layout arrangement in which the switch element region SWR is provided between the operational amplifier region OPR and the capacitor region CR as shown in FIG. 12 is adopted, the summing node line LNEG is simply connected to one end of the capacitor CS. It is possible to connect by wiring.

  Further, in the operational amplifier region OPR, by forming the shield patterns SLA1 to SLA4 as described in FIGS. 4 and 5, the parasitic capacitance between the summing node line LNEG and other signal lines is minimized. ing. On the other hand, in the switch element region SWR, a shield pattern SLD2 as shown at H5 is formed below the summing node line LNEG whose wiring layer is changed to the upper metal layer M4, so that the LNEG and other signal lines The parasitic capacitance between is kept to a minimum. Therefore, according to the layout method of this embodiment, the parasitic capacitance between the summing node line LNEG and the other signal lines can be minimized in both the operational amplifier region OPR and the switch element region SWR. . As a result, even when the summing node line LNEG is wired along the direction D2 on the switch element region SWR and connected to one end of the capacitor CS, the adverse effect due to the parasitic capacitance is minimized, and an appropriate sampling operation is performed. Can be realized.

5. Second Configuration Example of Sample and Hold Circuit Next, a second configuration example of the sample and hold circuit of this embodiment will be described. This second configuration example is a sample-and-hold circuit provided with a plurality of sampling capacitors, sampling switch elements, flip-around switch elements, and the like in order to generate gradation voltages as will be described later.

  For example, in FIGS. 13A and 13B, the flip-around sample-and-hold circuit (gradation generation amplifier) of the second configuration example includes an operational amplifier OP1 and first and second sampling capacitors CS1. , CS2 (a plurality of sampling capacitors).

  The sampling capacitor CS1 is provided between the first input node NI1 of the sample hold circuit and the inverting input terminal (summing node NEG, first connection node) of the operational amplifier. As shown in FIG. 13A, charge corresponding to the input voltage VI1 of the input node NI1 is accumulated in the capacitor CS1 in the sampling period.

  The sampling capacitor CS2 is provided between the second input node NI2 of the sample hold circuit and the inverting input terminal (summing node NEG, second connection node) of the operational amplifier OP1. The capacitor CS2 accumulates charges according to the input voltage VI2 of the input node NI2 during the sampling period.

  As shown in FIG. 13B, in the hold period, the sample hold circuit supplies the output voltage VQG (= VS) corresponding to the charges accumulated in the sampling capacitors CS1 and CS2 in the sampling period to the output node NQG. Output. Specifically, a flip-around operation is performed in which the other ends of the capacitors CS1 and CS2, which are connected to the node NEG at one end thereof, are connected to the output terminal of the operational amplifier OP1, thereby depending on the charges accumulated in CS1 and CS2. Output voltage VQG.

  If the flip-around sample-and-hold circuit as described above is used, so-called offset free can be realized.

  For example, the offset voltage generated between the inverting input terminal and the non-inverting input terminal of the operational amplifier OP1 is VOF, AGND is temporarily set to 0V for simplicity of explanation, and the input voltage during the sampling period is set to VI1 = VI2 = VI. Let CS be the parallel capacitance value of capacitors CS1 and CS2 connected in parallel. Then, the charge Q accumulated in the sampling period is expressed by the following equation.

Q = (VI−VOF) × CS (1)
On the other hand, when the voltage of the node NEG in the hold period is VX and the output voltage is VQG, the charge Q ′ accumulated in the hold period is expressed by the following equation.

Q ′ = (VQG−VX) × CS (2)
When the amplification factor of the operational amplifier OP1 is A, VQG is expressed as the following equation.

VQG = −A × (VX−VOF) (3)
Then, since Q = Q ′ by the law of charge conservation, the following equation is established.

(VI−VOF) × CS = (VQG−VX) × CS (4)
Therefore, according to the above equations (3) and (4),
VQG = VI-VOF + VX = VI-VOF + VOF-VQG / A
Is established. Therefore, the output voltage VQG of the sample and hold circuit is expressed by the following equation.

VQG = {1 / (1 + 1 / A)} × VI (5)
As apparent from the above equation (5), the output voltage VQG of the sample and hold circuit does not depend on the offset voltage VOF, and the offset can be canceled, so that offset free can be realized.

  14A and 14B show detailed examples of the sample-and-hold circuit (gradation generation amplifier) of the first configuration example. 14A and 14B includes an operational amplifier OP1, first and second sampling switch elements SS1 and SS2, and first and second sampling capacitors CS1 and CS2. , A feedback switch element SFG, and first and second flip-around switch elements SA1 and SA2. An output switch element SQG is also included. It should be noted that modifications such as omitting some of these components or adding other components are possible. In addition, the switch elements SS1, SS2, SA1, SA2, SFG, and SQG can be configured by CMOS transistors such as transfer gates, for example.

  AGND is set to the non-inverting input terminal (second input terminal) of the operational amplifier OP1. The first sampling switch element SS1 is provided between the first input node NI1 and the first connection node NS1 of the sample and hold circuit. The second sampling switch element SS2 is provided between the second input node NI2 and the second connection node NS2 of the sample and hold circuit. The first sampling capacitor CS1 is provided between the first connection node NS1 and the summing node NEG. The second sampling capacitor CS2 is provided between the second connection node NS2 and the summing node NEG.

  The feedback switch element SFG is provided between the output terminal of the operational amplifier OP1 and the inverting input terminal of OP1. The first flip-around switch element SA1 is provided between the first connection node NS1 and the output terminal of the operational amplifier OP1. The second flip-around switch element SA2 is provided between the second connection node NS2 and the output terminal of the operational amplifier OP1.

  As shown in FIG. 14A, in the sampling period, the sampling switch elements SS1 and SS2 and the feedback switch element SFG are turned on, and the flip-around switch elements SA1 and SA2 are turned off.

  On the other hand, as shown in FIG. 14B, in the hold period, the sampling switch elements SS1 and SS2 and the feedback switch element SFG are turned off, and the flip-around switch elements SA1 and SA2 are turned on.

  The output switch element SQG is provided between the output terminal of the operational amplifier OP1 and the output node NQG of the sample hold circuit. As shown in FIG. 14A, the output switch element SQG is turned off during the sampling period. As a result, the output of the sample hold circuit becomes a high impedance state, and it is possible to prevent an uncertain voltage during the sampling period from being transmitted to the subsequent stage.

  On the other hand, as shown in FIG. 14B, the output switch element SQG is turned on in the hold period. Thereby, the voltage VQG which is the gradation voltage generated in the sampling period can be output.

  Next, the circuit operation of FIGS. 14A and 14B will be described with reference to FIG. The first gradation voltage VG1 from the D / A conversion circuit included in the data line driver circuit is input to the node NG1, and the second gradation voltage VG2 having a voltage level different from that of VG1 is input to the node NG2. Is done.

  One of the switch elements SW1 and SW2 of the switch circuit 54 is exclusively turned on according to the gradation data DG. Any one of the switch elements SW3 and SW4 is exclusively turned on according to the gradation data DG.

  In the sampling period, the switch control signals input to the sampling switch elements SS1 and SS2 and the feedback switch element SFG are active (H level), so that the switch elements SS1, SS2, and SFG are turned on. On the other hand, since the switch control signals input to the flip-around switch elements SA1 and SA2 and the output switch element SQG become inactive (L level), the switch elements SA1, SA2 and SQG are turned off.

  In the hold period, the switch control signals input to the switch elements SS1, SS2, and SFG are inactive, and thus SS1, SS2, and SFG are turned off. On the other hand, since the switch control signal input to the switch elements SA1, SA2, and SQG becomes active, SA1, SA2, and SQG are turned on.

  As indicated by A1 and A2 in FIG. 15, the sampling switch elements SS1 and SS2 are turned off after the feedback switch element SFG is turned off. In this way, adverse effects of charge injection can be minimized. As indicated by A3, the flip-around switch elements SA1 and SA2 and the output switch element SQG are turned on after the sampling switch elements SS1 and SS2 are turned off.

  For example, FIG. 16A shows an example of a transfer gate TG serving as a switch element. Switch control signals CNN and CNP are input to the gates of the N-type transistor TN and the P-type transistor TP constituting the transfer gate TG. When the transfer gate TG is turned off, clock feedthrough occurs due to parasitic capacitances Cgd and Cgs between the gate and the drain or between the gate and the source. In addition, when the transfer gate TG is turned off, the channel charge flows into the drain and the source, and charge injection occurs.

  In this regard, in this embodiment, the sampling switch elements SS1 and SS2 are turned off as shown in FIG. 16C after the feedback switch element SFG is turned off as shown in FIG. 16B. , Adverse effects due to charge injection and clock feedthrough can be reduced.

  That is, as shown in FIG. 16B, when the switch element SFG is turned off when the switch elements SS1 and SS2 are on, the switch element SFG is affected by charge injection and clock feedthrough. However, as shown in FIG. 16C, at the timing when the switch elements SS1 and SS2 are turned off, the switch element SFG is turned off and the node NEG is in a high impedance state. Therefore, since it is not affected by the clock feedthrough and charge injection at SS1 and SS2, the adverse effects due to charge injection and feedthrough can be reduced.

  Note that switch control signals CNN and CNP having an amplitude of VDDHS to VSS are input to the gates of the transistors TN and TP of the transfer gate TG in FIG. Accordingly, when the drain or source potential of the transfer gate TG is set to VSS or VDDHS, an imbalance occurs between the charge amount from the N-type transistor TN and the charge amount from the P-type transistor TP, and the charge due to charge injection cancels out. It will remain without being.

  In this regard, immediately before the switching element SFG is turned off as shown in FIG. 16B, the non-inverting input terminal of the operational amplifier OP1 is set to AGND that is an intermediate voltage between VDDHS and VSS, and the operational amplifier OP1 is imaginary. The potential of the node NEG is set to AGND = (VDDHS + VSS) / 2 by the null short function. Therefore, immediately before the switch element SFG is turned off, the source and drain of the SFG are set to AGND, there is no dependency of the input gradation voltage, and the charge amount from the N-type transistor of the transfer gate TG and the P-type transistor Therefore, the adverse effect of charge injection caused by the switching element SFG being turned off can be minimized.

  FIG. 17A shows a modification of the second configuration example of the sample and hold circuit. In FIG. 17A, an auxiliary capacitor CAX is added to the configuration of FIGS. 14A and 14B.

  Here, one end of auxiliary capacitor CAX is connected to summing node NEG. Specifically, the auxiliary capacitor CAX is provided between the inverting input terminal (first input terminal) of the operational amplifier OP1 and the analog reference power supply voltage AGND. For example, one end of the auxiliary capacitor CAX is connected to the node NEG, and the like. The end is connected to AGND.

  Providing such an auxiliary capacitor CAX can suppress voltage fluctuations at the inverting input terminal of the operational amplifier OP1 and can further stabilize the output voltage VQG.

  Specifically, the voltage of the node NEG fluctuates at the moment when the sampling period in FIG. 14A shifts to the hold period in FIG. 14B. In this case, if the auxiliary capacitor CAX is not provided, the voltage at the node NEG varies instantaneously by the potential difference between the nodes NS1 and NS2 and the node NQG at the end of the sampling period. If the voltage of the node NEG at this time exceeds the substrate voltage of the switch element SFG, the charges accumulated in the capacitors CS1 and CS2 are lost. In order to prevent this, an auxiliary capacitor CAX is provided in FIG. In this way, the capacitor CS1 or CS2 and the capacitor CAX connected in series are provided between the nodes NQG and AGND, and the voltage fluctuation of the node NEG is suppressed to the range of VDDHS to VSS. , The situation where the accumulated charge of CS2 is lost can be prevented.

  In the modification of FIG. 17A, the operational amplifier OP1 includes a phase compensation capacitor CCP. Specifically, as shown in FIG. 17B, the phase compensation capacitor CCP is provided between the output node NB3 of the differential section DIF of the operational amplifier OP1 and the output node NB4 of the output section QQ. For example, one end of the phase compensation capacitor CCP is connected to the node NB3, and the other end is connected to the node NB4. By providing such a phase compensation capacitor CCP, oscillation of the operational amplifier OP1 can be prevented.

6). Detailed Layout Arrangement of Sample and Hold Circuit FIG. 18 shows a more detailed layout arrangement example of the sample and hold circuit. FIG. 18 shows a layout arrangement of a modified example of the second configuration example described with reference to FIGS. 17A and 17B.

  As indicated by I1 in FIG. 18, the auxiliary capacitor CAX described in FIGS. 17A and 17B is arranged in the capacitor region CR. A phase compensation capacitor CCP is also disposed as indicated by I2.

  Specifically, as indicated by I1, the auxiliary capacitor CAX is disposed in the D2 direction of the first and second sampling capacitors CS1 and CS2. In other words, sampling capacitors CS1 and CS2 are arranged between the auxiliary capacitor CAX and the operational amplifier OP1.

  As indicated by I3, the summing node line LNEG is wired along the direction D2 from the operational amplifier OP1 side to the auxiliary capacitor CAX side in the region between the capacitors CS1 and CS2.

  In FIG. 18, not only the switch element region SWR but also the capacitor region CR, a shield pattern SLD3 (shield line) is formed below the summing node line LNEG. The shield pattern SLD3 is formed of, for example, a third metal layer M3 below the fourth metal layer M4 that forms the summing node line LNEG. By providing such a VSS shield pattern SLD3, it is possible to reduce the parasitic capacitance between circuit elements and wirings formed thereunder. Specifically, in the capacitor region CR, other signal lines (not shown) are wired along the direction D1. Examples of such other signal lines include a signal line for a repeater circuit. Specifically, for example, when a plurality of sample and hold circuits are arranged along the direction D1, a repeater circuit that buffers a control signal from a logic circuit (not shown) is provided for each of the plurality of sample and hold circuits. Then, the signal line for the repeater circuit is wired on the capacitors CS1, CS2, CAX and the like. That is, if such a signal line for the repeater circuit is wired in the operational amplifier region OPR, it becomes difficult to prevent the operational amplifier from malfunctioning due to parasitic capacitance. On the other hand, if a signal line for the repeater circuit is wired on the capacitor, such a malfunction can be prevented by forming an appropriate shield pattern. When the shield pattern SLD3 as shown in FIG. 18 is formed, it is possible to reduce the adverse effect of such voltage level fluctuations on the sample-and-hold circuit, such as the signal line for the repeater circuit.

  As indicated by I2, the phase compensation capacitor CCP is disposed between the first and second sampling capacitors CS1 and CS2 and the operational amplifier OP1. In other words, the phase compensation capacitor CCP is disposed at a location in the D2 direction of the operational amplifier OP1 and at a location in the D4 direction of the sampling capacitors CS1 and CS2.

  For example, since the auxiliary capacitor CAX is intended to suppress voltage fluctuations, it is not necessary to form its capacitance value with high accuracy compared to the sampling capacitors CS1 and CS2.

  Further, the phase compensation capacitor CCP is also a capacitor for preventing oscillation of the operational amplifier OP1, and therefore, it is not necessary to form the capacitance value with high accuracy as compared with the sampling capacitors CS1 and CS2.

  In consideration of the above, in FIG. 18, the layout is such that the sampling capacitors CS1 and CS2 are disposed between the auxiliary capacitor CAX and the phase compensation capacitor CCP. Specifically, the sampling capacitors CS1 and CS2 are arranged along the direction D1, the auxiliary capacitor CAX is arranged in the direction D2 of the capacitors CS1 and CS2, and the phase compensation capacitor CCP is arranged in the direction D4 of CS1 and CS2. Yes.

  For example, if a plurality of sample and hold circuits having the layout arrangement of FIG. 18 are arranged along the direction D1, for example, the second of the sample and hold circuits arranged on the left side in the D3 direction of the sampling capacitor CS1 of FIG. The sampling capacitor CS2 is arranged. As shown in FIG. 18, a sampling capacitor CS2 is arranged in the direction D1 of the sampling capacitor CS1. An auxiliary capacitor CAX is arranged in the direction D2 of the sampling capacitor CS1, and a phase compensation capacitor CCP is arranged in the direction D4. That is, other capacitors are arranged adjacent to the four sides of the capacitor CS1. Accordingly, since the gap between the edge of the capacitor CS1 and the edges of the adjacent capacitors CS2, CAX, CCP can be formed, for example, at substantially the same etching rate, the capacitor CS1 can be formed with high accuracy. The same applies to the sampling capacitor CS2.

  As described above, in FIG. 18, the auxiliary capacitor CAX and the phase compensation capacitor CCP are formed by effectively utilizing the empty area in the D2 direction and the empty area in the D4 direction of the sampling capacitors CS1 and CS2. Therefore, the layout efficiency can be improved, and the accuracy of the capacitance values of CS1 and CS2 can be improved by arranging the capacitors on the four sides of the capacitors CS1 and CS2.

  In FIG. 18, the summing node line LNEG is wired along the direction D2 over the region between the sampling capacitors CS1 and CS2. Therefore, the summing node NEG of the operational amplifier OP1 can be electrically connected to the auxiliary capacitor CAX arranged in the direction D2 of CS1 and CS2. As a result, the processing accuracy of the capacitors CS1 and CS2 can be improved while minimizing the imbalance of the parasitic capacitance with respect to the line LNEG.

  Further, as indicated by I4 in FIG. 18, a switch element region SWR is formed between the capacitor region CR and the operational amplifier region OPR.

  In the switch element region SWR, a P-type transistor TSP1 and an N-type transistor TSN1 constituting the sampling switch element SS1, and a P-type transistor TAP1 and an N-type transistor TAN1 constituting the flip-around switch element SA1 are arranged. In this case, the drains of the transistors TSP1 and TAP1 are common, and the drains of the transistors TSN1 and TAN1 are common. These drains are connected to the other end of the sampling capacitor CS1 via the connection node line LNS1. The sources of the flip-around transistors TAP1 and TAN1 are connected to the output node NQ of the operational amplifier OP1 arranged in the operational amplifier region OPR via the output node line LNQ.

  In the switch element region SWR, a P-type transistor TSP2 and an N-type transistor TSN2 constituting the sampling switch element SS2, and a P-type transistor TAP2 and an N-type transistor TAN2 constituting the flip-around switch element SA2 are arranged. In this case, the drains of the transistors TSP2 and TAP2 are common, and the drains of the transistors TSN2 and TAN2 are common. These drains are connected to the other end of the sampling capacitor CS2 via the connection node line LNS2. The sources of the flip-around transistors TAP2 and TAN2 are connected to the output node NQ of the operational amplifier OP1 arranged in the operational amplifier region OPR via the output node line LNQ.

  As shown by I4 in FIG. 18, in the present embodiment, the N-type transistors TSN1, TAN1, TSN2, and TAN2 constituting the sampling switch elements SS1 and SS2 and the flip-around switch elements SA1 and SA2 are used as the second P-type well. It arrange | positions along D1 direction in PWL2. The P-type transistors TSP1, TAP1, TSP2, and TAP2 constituting the sampling switch elements SS1 and SS2 and the flip-around switch elements SA1 and SA2 are arranged along the direction D1 in the second N-type well NWL2. In this way, a highly symmetric layout arrangement of these transistors is possible, the parasitic capacitance value differences CP1-CP2, CP3-CP4 can be reduced, and circuit characteristics can be improved.

  In FIG. 18, the sampling control lines LSP and LSN are wired in the D3 direction of the summing node line LNEG, and the flip-around control lines LAP and LAN are wired in the D1 direction of the summing node line LNEG. The negative logic sampling control line LSP is connected to the sampling P-side gate control line LGSP in the switch element region SWR. The positive logic sampling control line LSN is connected to the sampling N-side gate control line LGSN. The negative logic flip-around control line LAP is connected to the flip-around P-side gate control line LGAP in the switch element region SWR. The positive logic flip-around control line LAN is connected to the flip-around N-side gate control line LGAN.

  As described in FIG. 11, the summing node line LNEG is electrically connected to the N + impurity layer (NCU) of the capacitor. For example, an impurity layer that forms an electrode on one end of the sampling capacitor CS1 is a first impurity layer, and an impurity layer that forms an electrode on one end of the sampling capacitor CS2 is a second impurity layer. Then, the summing node line LNEG is electrically connected to the first impurity layer of the capacitor CS1 as indicated by I5 in FIG. 18, and is electrically connected to the second impurity layer of the capacitor CS2 as indicated by I6. Connected.

  Further, as indicated by I7 and I8 in FIG. 18, the line LNS1 of the node NS1 is electrically connected to the polysilicon layer which is an electrode on the other end side of the capacitor CS1, and the line LNS2 of the node NS2 is connected to the capacitor CS2. It is electrically connected to a polysilicon layer which is an end electrode.

  Also, in I9 of FIG. 18, the first lead line LDR1 of the line LNEG is wired on the capacitor CS1 along the direction D1. The lead line LDR1 is a line for connecting the line LNEG to one end (impurity layer) of the capacitor CS1, and is formed of a metal layer (conductive layer in a broad sense) different from the line LNEG. Specifically, the lead line LDR1 is formed of, for example, the second metal layer M2, and the line LNEG is formed of, for example, the fourth metal layer M4.

  Similarly, in I10 of FIG. 18, the second lead line LDR2 of the line LNEG is wired on the capacitor CS2 along the direction D1. The lead line LDR2 is a line for connecting the line LNEG to one end (impurity layer) of the capacitor CS2, and is formed of a metal layer (conductive layer) different from the line LNEG. Specifically, the lead line LDR2 is formed of, for example, the second metal layer M2.

  If such a lead line LDR1 is wired, the node NEG can be electrically connected to the electrode on one end side of the capacitor CS1 on both the left and right sides (impurity layers on both sides) of the capacitor CS1. If the lead line LDR2 is wired, the node NEG can be electrically connected to the electrode on one end side of the capacitor CS2 on both the left side and the right side of the capacitor CS2. Thereby, the capacitance values of CS1 and CS2 can be stabilized.

  Further, in I11 of FIG. 18, the first line LNS1 connected to the other end of the capacitor CS1 is wired on the capacitor CS1 along the direction D2. In I12, the second line LNS2 connected to the other end of the capacitor CS2 is wired on the capacitor CS2 along the direction D2. These lines LNS1 and LNS2 are upper metal layers of the lead lines LDR1 and LDR2, and are formed of, for example, a fourth metal layer that is the same layer as the line LNEG.

  As indicated by I3, I11, and I12, the line LNEG is wired between the line LNS1 and the line LNS2 along the direction D2.

  If the lines LNEG, LNS1, and LNS2 are wired in this way, for example, a layout that minimizes the parasitic capacitance between these lines becomes possible. Specifically, by forming (wiring) a shield pattern (shield wire) between the lines LNEG and LNS1, or by forming (wiring) a shield pattern (shield wire) between the lines LNEG and LNS2, The parasitic capacitance between lines can be minimized.

  Further, in I13 of FIG. 18, the AGND line LAGND is wired along the D1 direction in the D4 direction of the summing node line LNEG. This line LAGND is a line for supplying the analog reference power supply voltage AGND set to the non-inverting input terminal (second terminal) of the operational amplifier OP1.

  Also, in I14 and I15 of FIG. 18, the bias signal lines LBS1 and LBS2 are wired along the D1 direction in the D4 direction of the AGND line. The lines LBS1 and LBS2 are lines for supplying the bias signals BS1 and BS2 of FIG. 17B to the operational amplifier OP1.

  If the line LAGND is wired as indicated by I13 in FIG. 18, this line LAGND can be effectively used to realize the shield on the D4 direction side of the summing node line LNEG. That is, the line LAGND serves as a shield, and the parasitic capacitance between the other signal lines existing on the D4 direction side of the summing node line LNEG and LNEG can be reduced.

  Also, as shown by I14 and I15 in FIG. 17, if the lines LBS1 and LBS2 are wired in the direction D4 of the line LAGND, the voltage fluctuations in the bias signal lines LBS1 and LBS2 are transmitted to the summing node line LNEG. This can be prevented by LAGND functioning as a shield pattern.

  That is, when a large number of operational amplifiers are arranged along the direction D1 in order to drive a large number of data lines, these operational amplifiers operate simultaneously, whereby the voltages of the bias signals BS1 and BS2 in FIG. Greatly fluctuates transiently. When this voltage fluctuation is transmitted to the summing node line LNEG via the parasitic capacitance, a situation in which an appropriate sampling operation cannot be realized occurs.

  In this regard, as shown by I13, I14, and I15 in FIG. 18, if the AGND line LAGND and the bias signal lines LBS1 and LBS2 are wired, the voltage fluctuation of the bias signal is prevented from being transmitted to the summing node line LNEG. And the above situation can be effectively prevented.

  In FIG. 18, shield patterns SEL1, SEL2, SEL3, and SEL4 are wired along the direction D1 on both sides of the lines LAGND, LBS1, and LBS2. By wiring such shield patterns SEL1, SEL2, SEL3, and SEL4, it is possible to reduce fluctuations in the voltage of AGND and the bias signal.

7). Circuit Configuration of Integrated Circuit Device FIG. 19 shows a circuit configuration example of the integrated circuit device 10 (driver) including the sample hold circuit of the present embodiment. The sample and hold circuit of this embodiment is provided in the data driver 50 of the integrated circuit device 10, for example.

  The integrated circuit device 10 of the present embodiment is not limited to the configuration shown in FIG. 19, and some of the components (for example, a scan driver, a gradation voltage generation circuit, a logic circuit, etc.) are omitted, or other components are Various modifications such as addition are possible.

  The electro-optical panel 400 (electro-optical device) includes a plurality of data lines (for example, source lines), a plurality of scanning lines (for example, gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of electro-optical elements (liquid crystal elements, EL elements, etc. in a narrow sense) in each pixel region. This electro-optical panel (display panel in a narrow sense) can be constituted by an active matrix type panel using switch elements such as TFT and TFD. The electro-optical panel may be a panel other than the active matrix system, or may be a panel using a light emitting element such as an organic EL (Electro Luminescence) or an inorganic EL other than the liquid crystal panel.

  The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22.

  The logic circuit 40 (driver logic circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A).

  The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation adjustment data (γ correction data) for adjusting gradation characteristics (γ characteristics) is output to the gradation voltage generation circuit 110, or the power supply voltage is supplied to the power supply circuit 90. Outputs power adjustment data for adjustment. In addition, a write / read process to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28 is controlled.

  The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory 20 to the electro-optical panel 400 side. The host (MPU) interface circuit 46 implements a host interface that accesses the memory 20 by generating an internal pulse for each access from the host. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to the memory 20 using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  The data driver 50 is a circuit that generates a data signal (voltage, current) to be supplied to a data line of the electro-optical panel 400 (electro-optical device). Specifically, the data driver 50 receives image data (grayscale data, display data) from the memory 20, and receives a plurality of (for example, 256 levels) grayscale voltages (reference voltages) from the grayscale voltage generation circuit 110. Then, a voltage (data voltage) corresponding to the image data (gradation data) is selected from the plurality of gradation voltages, and is output to the data line of the electro-optical panel 400.

  The scanning driver 70 is a circuit that generates a scanning signal for driving the scanning lines of the electro-optical panel 400. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by level-converting the shifted signal is applied to each scanning line of the electro-optical panel 400 as a scanning signal (scanning voltage). Output. The scan driver 70 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 90 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. Then, the voltage obtained by the boosting is supplied to the data driver 50, the scan driver 70, the gradation voltage generation circuit 110, and the like.

  The gradation voltage generation circuit 110 is a circuit that generates gradation voltages and supplies them to the data driver 50. Specifically, the gradation voltage generation circuit 110 can include a ladder resistor circuit that divides a resistance between a high potential side voltage and a low potential side voltage and outputs a gradation voltage to a resistance dividing node. In addition, a gradation register unit in which gradation adjustment data is written, a gradation voltage setting circuit that variably sets (controls) the gradation voltage output to the resistance division node based on the written gradation adjustment data, and the like. Can be included.

8). Data Driver Next, a detailed configuration example of the data driver will be described with reference to FIG. FIG. 20 is a configuration example of each sub-driver block of a plurality of sub-driver blocks included in the data driver. Specifically, the data driver (sub driver block) includes a D / A conversion circuit 52 and data line driving circuits 60-1 to 60-L. In FIG. 20, one D / A conversion circuit 52 is shared by a plurality of data line driving circuits 60-1 to 60-L (first to Lth data line driving circuits). A data line driving circuit or the like may be provided for each data line of the electro-optical panel, or the data line driving circuit may drive a plurality of data lines in a time division manner. A part or all of the data driver (integrated circuit device) may be integrally formed on the electro-optical panel.

  The D / A conversion circuit 52 (voltage generation circuit) receives gradation data DG (image data, display data) from the memory 20 of FIG. 19, for example. Then, the first and second gradation voltages VG1 and VG2 corresponding to the gradation data DG are output.

  Specifically, the D / A conversion circuit 52 receives the gradation data and applies the first and second gradation voltages VG1 and VG2 corresponding to the gradation data to each sampling in the first to Lth sampling periods. Output in time division during the period.

  The data line driving circuits 60-1 to 60-L include gradation generation amplifiers 62-1 to 62-L (GA1 to GAL). Each of these gradation generation amplifiers 62-1 to 62-L has first and second gradation voltages VG1 output from the D / A conversion circuit 52 in each sampling period of the first to Lth sampling periods. , VG2 is sampled to generate a gradation voltage between VG1 and VG2.

  FIG. 21 shows a second configuration example of the data driver (sub driver block). In FIG. 21, the data line drive circuits 60-1 to 60-L include drive amplifiers 64-1 to 64-L (first to L-th drive amplifiers) provided in the subsequent stage of the gradation generation amplifiers 62-1 to 62-L. Drive amplifier).

  The drive amplifiers 64-1 to 64-L (DA1 to DAL) included in the data line drive circuits 60-1 to 60-L generate gradations in the drive amplifier sampling period after the first to Lth sampling periods. The output voltage of the amplifiers 62-1 to 62-L is sampled. In the drive amplifier hold period after the drive amplifier sampling period, the sampled output voltage is output.

  For example, FIG. 22 shows a signal waveform example when the D / A conversion circuit 52 is shared by the six data line driving circuits GA1 to GA6. The data line driving circuits GA1 to GA6 perform a sampling operation in the sampling periods TS1 to TS6 (first to Lth sampling periods), and perform a holding operation in the subsequent hold periods TH1 to TH6 (first to Lth hold periods). Do.

  The drive amplifiers DA1 to DA6 perform a sampling operation in the drive amplifier sampling period TDS after the sampling periods TS1 to TS6, and perform a hold operation in the subsequent drive amplifier hold period TDH.

  20 and 21, it is not necessary to provide a D / A conversion circuit for each data line driving circuit, and one D / A conversion is performed for a plurality of data line driving circuits 60-1 to 60-L. A circuit 52 may be provided. Therefore, the area occupied by the D / A conversion circuit 52 in the integrated circuit device can be reduced, and the integrated circuit device can be downsized.

  As described above, even if the D / A conversion circuit 52 outputs the first and second gradation voltages VG1 and VG2 in a time division manner, the sampling function of the gradation generation amplifiers 62-1 to 62-L causes the first and second gradation voltages VG1 and VG2 to be output. Appropriate sampling of the voltage in each of the 1st to Lth sampling periods becomes possible.

  Further, when the D / A conversion circuit 52 is used for time division in this way, the total time of the sampling periods TS1 to TS6 becomes longer as shown in FIG. For this reason, for example, the hold period TH6 of the gradation generation amplifier GA6 is shortened, and there is no margin in the drive time of the data line.

  In this regard, if the drive amplifiers DA1 to DA6 are provided after the gradation generation amplifiers GA1 to GA6 as shown in FIG. 21, the drive amplifiers DA1 to DA6 are sampled during the sampling periods TS1 to TS6 as shown at E15 in FIG. DA6 enters the hold operation mode and can drive the data line. Therefore, the drive time of the data line can be extended, and a highly accurate voltage can be supplied to the data line.

  Further, in the conventional data driver, in order to increase the voltage supplied to the data line with high accuracy, for example, in the second half of the driving period, DAC driving for directly driving the data line by the D / A conversion circuit is performed. For this reason, it is necessary to provide a D / A conversion circuit having the same configuration for each data line, which causes an increase in the scale of the integrated circuit device due to the layout area of the D / A conversion circuit.

  In this respect, if the tone generation amplifier and the drive amplifier have a sample hold function and are configured by, for example, a flip-around sample hold circuit, so-called offset free can be realized. Accordingly, it is possible to supply a highly accurate voltage to the data line while minimizing the variation in the output voltage to the data line, and thus the above-described DAC drive is not necessary. Therefore, it is not necessary to provide a D / A conversion circuit having the same configuration for each data line, and a single D / A conversion circuit can be shared by a plurality of data line driving circuits as shown in FIGS. Become. Therefore, it is possible to achieve both high accuracy of the voltage of the data line and reduction of the area of the data driver.

  20 and 21 also has an advantage that the gradation voltage lines can be shared in time division for R (red), G (green), and B (blue).

  For example, it is assumed that the data transfer bus (gradation data bus) connecting the memory 20 and the data driver 50 in FIG. 19 is, for example, a 16-bit bus. Further, it is assumed that the number of bits of each of the R, G, and B subpixels is 8 bits, and the number of bits of the pixel configured by the R, G, and B subpixels is 8 × 3 = 24 bits.

  In this case, in E1 and E2 of FIG. 22, 8-bit sub-pixel image data R0 (gradation data) of the first pixel and 8-bit sub-pixel image data of the second pixel adjacent to the first pixel. R1 (gradation data) is transferred from each memory block to each data driver block via, for example, a 16-bit data transfer bus (gradation data bus).

  In E3 of FIG. 22, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit subpixel image data R0. Then, as indicated by E4, the gradation generating amplifier GA1 performs a sampling operation of VG1 and VG2 in the sampling period TS1, and generates a gradation voltage between VG1 and VG2.

  In E5, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit subpixel image data R1. Then, as indicated by E6, the gradation generation amplifier GA2 performs a sampling operation of VG1 and VG2 in the sampling period TS2, and generates a gradation voltage between VG1 and VG2.

  In E7 and E8, 8-bit subpixel image data G0 and 8-bit subpixel image data G1 of the second pixel are transferred from each memory block via a 16-bit data transfer bus (gradation data bus). Transferred to each data driver block.

  In E9, the D / A conversion circuit 52 outputs the first and second gradation voltages VG1 and VG2 corresponding to the 8-bit subpixel image data G0. Then, as indicated by E10, the gradation generation amplifier GA3 performs a sampling operation of VG1 and VG2 in the sampling period TS3, and generates a gradation voltage between VG1 and VG2.

  In E11, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit subpixel image data G1. Then, as indicated by E12, the gradation generation amplifier GA4 performs a sampling operation of VG1 and VG2 in the sampling period TS4 to generate a gradation voltage between VG1 and VG2. In E13 and E14, the sub-pixel image data B0 and B1 are transferred, and the same processing as described above is performed.

  In this way, it is not necessary to provide separate gradation voltage lines for R, G, and B, and one gradation voltage line is used for the gradation voltages for R, G, and B. Can be used in a time-sharing manner. For example, the gradation voltage line can be used for R in E1 and E2 in FIG. 22, the gradation voltage line can be used for G in E7 and E8, and the gradation voltage line can be used for B in E13 and E14.

  For example, when 64 gradation voltage lines are required for each of R, G, and B, the method of providing separate gradation voltage lines for R, G, and B is 64 × 3. = 192 grayscale voltage lines are required.

  In this respect, in the present embodiment, since one gradation voltage line is used for R, G, and B in a time-sharing manner, 64 gradation voltage lines can be used, and the gradation voltage is reduced. The wiring area of the line can be greatly reduced, and the area of the integrated circuit device can be reduced.

  In the present embodiment, a common potential setting method (equalization) of the data lines is adopted in order to realize low power consumption. Specifically, as indicated by E16 in FIG. 22, in the drive amplifier sampling period TDS, the output lines of the drive amplifiers DA1 to DA6 are set to a common potential such as the common voltage VCOM. For example, the common voltage VCOM which is a common potential is set. The common potential is not limited to VCOM, and may be, for example, a GND potential.

  By doing so, the charge accumulated in the electro-optical panel is reused to charge and discharge the charge on the data line of the electro-optical panel, so that the power consumption can be further reduced.

9. Electronic Device FIGS. 23A and 23B show a configuration example of an electronic device or the electro-optical device 500 including the integrated circuit device 10 of this embodiment. Note that various modifications may be made such as omitting some of the components shown in FIGS. 23A and 23B or adding other components (such as a camera, an operation unit, or a power supply). . The electronic device of the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a television, a projector, or a portable information terminal.

  In FIGS. 23A and 23B, the host device 410 is, for example, an MPU or a baseband engine. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, the image processing controller 420 in FIG. 23B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 23A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the electro-optical panel. On the other hand, in the case of FIG. 23B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the electro-optical panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (inverted input terminals, non-inverted input terminals, etc.) described at least once together with different terms having a broader meaning or the same meaning (first input terminal, second input terminal, etc.) are: The different terms can be used anywhere in the specification or drawings. Further, the configurations and operations of the integrated circuit device, the electro-optical device, the electronic apparatus, and the like are not limited to those described in this embodiment, and various modifications can be made.

1A and 1B are basic configurations of the sample-and-hold circuit of this embodiment. 2A to 2C are specific examples of the sample and hold circuit. 3A and 3B are diagrams for explaining the operation of the sample and hold circuit. The layout arrangement example of the switch element for feedback. The layout arrangement example of the switch element for feedback. 6A and 6B show other layout arrangement examples of the feedback switch element. The other layout arrangement example of the switch element for feedback. 8A and 8B show detailed configuration examples of the sample hold circuit and the operational amplifier. Sectional drawing for demonstrating the layout arrangement | positioning of a sample hold circuit. 4 is a layout arrangement example of a sample and hold circuit according to the present embodiment. Sectional drawing for demonstrating the layout arrangement | positioning of a capacitor. An example of layout of capacitors. FIG. 13A and FIG. 13B are explanatory diagrams of a sample-and-hold circuit of the second configuration example. 14A and 14B are detailed examples of the sample-and-hold circuit of the second configuration example. Explanatory drawing of the circuit operation | movement of a sample hold circuit. FIG. 16A to FIG. 16C are explanatory diagrams of the switch control method of the present embodiment. FIG. 17A and FIG. 17B are explanatory diagrams of a modification of the second configuration example of the sample and hold circuit. 3 is a detailed layout arrangement example of a sample and hold circuit of the present embodiment. 2 is a circuit configuration example of the integrated circuit device of the present embodiment. Configuration example of data driver. 2 shows a second configuration example of a data driver. The signal waveform example for demonstrating operation | movement of a data driver. FIG. 23A and FIG. 23B are configuration examples of electronic devices.

Explanation of symbols

SF switch element for feedback, SS switch element for sampling,
CS sampling capacitor, SA flip-around switch element,
OP1 operational amplifier, NEG summing node, LNEG summing node line,
TFP feedback P-type transistor, TFN feedback N-type transistor,
DP, DN drain, SP, SN source, GP, GN gate,
CDP, CDN drain contact, CSP, CSN source contact,
LDA1, LDB1, LDB2, LDB3 drain connection lines,
LSA1, LSB1, LSB2, LSB3 source connection line,
LGP, LGN gate connection line,
SLA1 to SLA4, SLB1 to SLB7 shield pattern,
OPR operational amplifier area, CR capacitor area, SWR switch element area,
CS1, CS2 sampling capacitor, CAX auxiliary capacitor,
CCP phase compensation capacitor, LNS1, LNS2 connection node line,
10 integrated circuit device, 20 memory, 22 memory cell array,
24 row address decoder, 26 column address decoder,
28 write / read circuit, 40 logic circuit, 42 control circuit,
44 display timing control circuit, 46 host interface circuit,
48 RGB interface circuit, 50 data driver,
52 D / A conversion circuit, 54 switch circuit,
60 60-1 to 60-L data line drive circuit, 62, 62-1 to 62-L gradation generation amplifier,
64 64-1 to 64-L drive amplifier, 70 scan driver, 90 power supply circuit,
110 gradation voltage generation circuit, 400 electro-optical panel, 410 host device,
420 image processing controller, 500 electro-optical device

Claims (16)

An operational amplifier;
A sampling capacitor provided between an input node of the sample hold circuit and a summing node which is a node of the first input terminal of the operational amplifier;
A feedback switching element provided between an output terminal of the operational amplifier and the summing node, and configured by a transfer gate;
The feedback switch element includes a feedback P-type transistor in which a summing node line which is a line of the summing node is electrically connected to a drain thereof, and a feedback transistor in which the summing node line is electrically connected to a drain thereof. Including N-type transistors,
A shield pattern is formed in a region between the drain contact of the feedback P-type transistor and the feedback N-type transistor and the source contact of the feedback P-type transistor and the feedback N-type transistor. Sample hold circuit. In claim 1,
When the direction from the source of the feedback P-type transistor to the drain of the feedback P-type transistor is the first direction, and the direction orthogonal to the first direction is the second direction,
A drain connection line connected to a drain contact of the feedback P-type transistor and the feedback N-type transistor is wired along the second direction,
A source connection line connected to a source contact of the feedback P-type transistor and the feedback N-type transistor is wired along the second direction,
A sample-and-hold circuit, wherein a shield line as the seal pattern is wired along the second direction in a region between the drain connection line and the source connection line. In claim 2,
The sample-and-hold circuit, wherein the shield pattern is formed of the same metal layer as the drain connection line. In claim 3,
A sample and hold circuit, wherein a second shield pattern formed of a metal layer above the metal layer forming the shield pattern is formed so as to overlap the shield pattern and the drain connection line. . In any one of Claims 1 thru | or 4,
The sample and hold circuit, wherein the shield pattern is formed so as to overlap the gates of the feedback P-type transistor and the feedback N-type transistor. In any one of Claims 1 thru | or 5,
A sampling switch element provided between the input node of the sample hold circuit and the sampling capacitor;
A sample and hold circuit comprising: a flip-around switch element provided between a connection node between the sampling switch element and the sampling capacitor and the output terminal of the operational amplifier. In claim 6,
When the direction orthogonal to the first direction is the second direction, the sampling capacitor is disposed in the second direction of the sampling switch element and the flip-around switch element,
The sampling and holding circuit, wherein the sampling switch element and the flip-around switch element are arranged between the operational amplifier and the feedback switch element and the sampling capacitor. In claim 7,
The summing node line is wired along the second direction over the switch element region where the sampling switch element and the flip-around switch element are formed, and is connected to one end of the sampling capacitor. A sample-and-hold circuit. In claim 8,
Of the summing node line, a line wired to the switch element region is formed of a metal layer that is an upper layer than a metal layer that forms a line formed in the operational amplifier region of the summing node line. A sample-and-hold circuit. In claim 9,
The sample-and-hold circuit, wherein a shield pattern for a switch element region is formed in a lower layer of a line wired to the switch element region in the summing node line. In any of claims 7 to 10,
When the direction opposite to the second direction is the fourth direction, an analog reference power supply voltage line, which is an analog reference power supply voltage line set at the second terminal of the operational amplifier, is connected to the summing node line. A sample-and-hold circuit, wherein the sample-and-hold circuit is wired along the first direction in the fourth direction. In claim 11,
A sample and hold circuit, wherein a bias signal line for supplying a bias signal to the operational amplifier is wired along the first direction in the fourth direction of the analog reference power supply voltage line. In any of claims 6 to 12,
As the sampling switch element, a first sampling switch element provided between a first input node and a first connection node of the sample and hold circuit, a second input node and a second of the sample and hold circuit. A second sampling switch element provided between the first and second connection nodes,
As the sampling capacitor, a first sampling capacitor provided between the first connection node and the summing node, and a second provided between the second connection node and the summing node. And a sampling capacitor of
The flip-around switch element includes a first flip-around switch element provided between the first connection node and the output terminal of the operational amplifier, the second connection node, and the operational amplifier. And a second flip-around switch element provided between the output terminal and the output terminal.   14. An integrated circuit device comprising the sample and hold circuit according to claim 1.   An electro-optical device comprising the integrated circuit device according to claim 14.   An electronic apparatus comprising the electro-optical device according to claim 15.

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