JP2009116303A - Data driver, integrated circuit device, and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data driver, an integrated circuit device, and an electronic instrument that can supply a voltage to a data line by a small circuit configuration even when the number of grayscales increases. <P>SOLUTION: The data driver includes a D/A conversion circuit 52 that receives grayscale data and outputs first and second grayscale voltages VG1 and VG2 corresponding to the grayscale data by time division in each of first to Nth sampling periods, and first to Nth data line driver circuits 60-1 to 60-N that share the D/A conversion circuit 52. The first to Nth data line driver circuits 60-1 to 60-N include grayscale generation amplifiers 62-1 to 62-N that each sample the first and second grayscale voltages VG1 and VG2, and generate a grayscale voltage between the first and second grayscale voltages VG1 and VG2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data driver, an integrated circuit device, an electronic device, and the like.

  Conventionally, as a liquid crystal panel (electro-optical device, display panel) used in an electronic device such as a cellular phone, a liquid crystal panel of a simple matrix type and an active matrix type liquid crystal using a switching element such as a thin film transistor (Thin Film Transistor). The panel is known.

  In recent years, the number of data lines (source lines) of the liquid crystal panel has increased due to the increase in the screen size of the liquid crystal panel and the increase in the number of pixels, while high accuracy of the voltage applied to each data line is required. Furthermore, due to the demand for lighter and smaller battery-powered electronic devices equipped with a liquid crystal panel, it is also required to reduce the power consumption and the chip size of the data driver (source driver) that drives the data lines of the liquid crystal panel. Yes.

  For example, Patent Document 1 and Patent Document 2 disclose a configuration capable of supplying a voltage to a data line with high accuracy while enabling a Rail-to-Rail operation of an output circuit that drives a data line of a data driver. ing.

  However, in the techniques disclosed in Patent Document 1 and Patent Document 2, each output circuit is equipped with an auxiliary circuit to control the driving capability and realize a Rail-to-Rail operation. Therefore, it is necessary to mount an auxiliary circuit as an additional circuit, and there is a problem that the circuit scale of the data driver becomes large. In addition, the size of the transistor has to be increased in order to suppress variations in voltage applied to the data line.

  Further, in order to supply a high-accuracy voltage to the data line, it is necessary to supply the voltage from the D / A conversion circuit that outputs a gradation voltage corresponding to the gradation data to the data line as it is. For this reason, when the number of gradations increases, it is necessary to increase the number of gradation voltage lines, which increases the chip size.

In general operational amplifiers, it is necessary to consider variations in output voltage. For this reason, it is necessary to increase the size of the transistors constituting the operational amplifier and suppress variations in output voltage.
JP 2005-175811 A JP 2005-175812 A

  According to some embodiments of the present invention, it is possible to provide a data driver, an integrated circuit device, and an electronic device that can supply a voltage to a data line with a small circuit configuration even when the number of gradations increases. According to another aspect of the present invention, it is possible to provide a data driver, an integrated circuit device, and an electronic device that can supply a highly accurate voltage with little variation to a data line.

  The present invention is a data driver for driving a data line of an electro-optical device, which receives grayscale data and applies first and second grayscale voltages corresponding to the grayscale data to first to Nth. A D / A conversion circuit that outputs in a time-sharing manner during each sampling period (N is an integer of 2 or more), and first to Nth data line driving circuits that share the D / A conversion circuit, Each data line driving circuit of the first to Nth data line driving circuits has the first and second output from the D / A conversion circuit in each sampling period of the first to Nth sampling periods. The present invention relates to a data driver including a gradation generation amplifier that samples a gradation voltage and generates a gradation voltage between the first gradation voltage and the second gradation voltage.

  In the present invention, the D / A conversion circuit outputs the first and second gradation voltages corresponding to the gradation data in a time division manner during each sampling period of the first to Nth sampling periods. The gradation generation amplifier of each data line driving circuit of the first to Nth data line driving circuits uses the first and second gradation voltages output in each sampling period of the first to Nth sampling periods. Sampling is performed to generate a gradation voltage between the first and second gradation voltages. In this way, since only one D / A conversion circuit needs to be provided for the first to Nth data line driving circuits, the area occupied by the D / A conversion circuit can be reduced. In the present invention, even if the D / A conversion circuit outputs the first and second gradation voltages in a time division manner, the voltage in each of the first to Nth sampling periods is obtained by the sampling function of the gradation generation amplifier. It is possible to perform proper sampling. Therefore, it is possible to provide a data driver that can supply a voltage to a data line with a small circuit configuration even when the number of gradations increases.

  In the present invention, the gradation generation amplifier may be formed of a flip-around sample / hold circuit.

  By using such a flip-around type sample-and-hold circuit, the tone generation amplifier can be provided with a voltage sample-and-hold function and so-called offset-free can be realized, so that a highly accurate voltage with little variation can be applied to the data line. Can supply.

  In the present invention, the gradation generation amplifier is provided between an operational amplifier, a first input terminal of the operational amplifier, and the first input node of the gradation generation amplifier, and the gradation generation amplifier includes the first generation node in a sampling period. Between the first sampling capacitor in which charges corresponding to the input voltage of one input node are stored, and the first input terminal of the operational amplifier and the second input node of the gradation generating amplifier And a second sampling capacitor in which charges corresponding to the input voltage of the second input node are accumulated during the sampling period, and accumulated in the first and second sampling capacitors during the sampling period. An output voltage corresponding to the generated charge may be output in the hold period.

  According to this configuration, the input voltages to the first and second input nodes are sampled by the first and second sampling capacitors during the sampling period, and the flip-around operation of the first and second sampling capacitors is performed. As a result, an output voltage corresponding to the charge accumulated in the first and second sampling capacitors can be output in the hold period.

  In the present invention, the gradation generation amplifier includes an operational amplifier in which a given reference voltage is set to the second input terminal thereof, the first input node of the gradation generation amplifier, and the first of the operational amplifier. A first sampling switch element and a first sampling capacitor provided between the first input terminal and the first input terminal of the operational amplifier; A second sampling switch element and a second sampling capacitor provided between the feedback amplifier, a feedback switch element provided between the output terminal of the operational amplifier and the first input terminal, A first flip-flop provided between a first connection node between a first sampling switch element and the first sampling capacitor and an output terminal of the operational amplifier. A second flip-flop provided between the second switch node, a second connection node between the second sampling switch element and the second sampling capacitor, and an output terminal of the operational amplifier An around switch element may be included.

  In this way, sampling of the input voltage to the first and second sampling capacitors is realized using the first and second sampling switch elements and the feedback switch element, and the first and second flip-flops are realized. Using the around switch element, the flip-around operation of the first and second sampling capacitors can be realized.

  In the present invention, in the sampling period, the first and second sampling switch elements and the feedback switch element are turned on, and the first and second flip-around switch elements are turned off. In the hold period, the first and second sampling switch elements and the feedback switch element may be turned off, and the first and second flip-around switch elements may be turned on.

  In this way, the first and second sampling capacitors and the feedback switch device are turned on during the sampling period, so that the first and second sampling capacitors are utilized by utilizing the imaginary short function of the operational amplifier. It is possible to store charges corresponding to the input voltage. Also, by turning on the first and second flip-around switch elements in the hold period, the output voltage corresponding to the electric charge accumulated in the first and second sampling capacitors is output to the output node of the gradation generation amplifier. Can be output.

  In the present invention, the gradation generation amplifier includes an output switch element provided between the output terminal of the operational amplifier and an output node of the gradation generation amplifier. The switch element may be turned off, and the output switch element may be turned on in the hold period.

  As described above, since the output switch element is turned off in the sampling period, it is possible to prevent a situation in which an uncertain voltage in the sampling period is transmitted to the subsequent stage.

  In the present invention, the first and second sampling switch elements may be turned off after the feedback switch element is turned off.

  By so doing, it is possible to minimize the adverse effects of charge injection from the first and second sampling switch elements and the like.

  In the present invention, the high-potential-side power supply voltage of the switch control signals of the first and second sampling switch elements, the feedback switch element, and the first and second flip-around switch elements is set to VDD, and the low-potential When the side power supply voltage is VSS, the reference voltage set to the second input terminal of the operational amplifier may be set to an intermediate voltage between VDD and VSS.

  Setting the reference voltage in this way can further reduce the adverse effects caused by charge injection.

  In the present invention, each of the data line drive circuits of the first to Nth data line drive circuits may include a drive amplifier provided in a subsequent stage of the gradation generation amplifier.

  Providing such a drive amplifier makes it possible to lengthen the drive time of the data line and improve the display quality.

  In the present invention, the drive amplifier may be constituted by a flip-around sample / hold circuit.

  By using such a flip-around type sample-and-hold circuit, it is possible to provide the drive amplifier with a voltage sample-and-hold function and realize so-called offset-free, so that a highly accurate voltage with little variation is applied to the data line. Can supply.

  In the present invention, the drive amplifier is provided between a second operational amplifier, a first input terminal of the second operational amplifier, and an input node of the drive amplifier, and in the drive amplifier sampling period, A sampling capacitor in which charge corresponding to the input voltage of the input node is stored, and an output voltage corresponding to the charge stored in the sampling capacitor in the drive amplifier sampling period is output in the drive amplifier hold period May be.

  In this way, the input voltage to the input node is sampled in the sampling capacitor during the drive amplifier sampling period, and the sampling capacitor performs a flip-around operation so that the output corresponding to the charge accumulated in the sampling capacitor is output. The voltage can be output during the hold period for the drive amplifier.

  According to the present invention, the drive amplifier includes a second operational amplifier in which a given reference voltage is set to the second input terminal, an input node of the drive amplifier, and a first operational amplifier. A sampling switch element and a sampling capacitor provided between the input terminal and a second feedback switch element provided between the output terminal of the second operational amplifier and the first input terminal; A flip-around switch element provided between a connection node between the sampling switch element and the sampling capacitor and an output terminal of the second operational amplifier may be included.

  In this way, sampling of the input voltage to the sampling capacitor is realized using the sampling switch element and the second feedback switch element, and the flip-around operation of the sampling capacitor is performed using the flip-around switch element. Can be realized.

  In the present invention, the operational amplifier included in the gradation generation amplifier is configured by an amplifier that performs a class A amplification operation, and the second operational amplifier included in the drive amplifier is configured by an amplifier that performs a class AB amplification operation. It may be configured.

  In this way, both low power consumption and high accuracy of the supply voltage to the data line can be achieved. Note that the operational amplifier of the drive amplifier may be an amplifier that performs class A amplification operation in the sampling period and performs class AB amplification operation in the hold period.

  In the present invention, the driving amplifier included in each data line driving circuit of the first to Nth data line driving circuits may be configured such that the driving amplifier sampling period after the first to Nth sampling periods is the level of the driving amplifier. The output voltage of the tone generation amplifier may be sampled, and the sampled output voltage may be output in the drive amplifier hold period after the drive amplifier sampling period.

  In this way, even when the total time of the first to Nth sampling periods becomes long, the drive amplifier is in the hold operation mode and drives the data lines during the first to Nth sampling periods. it can. Therefore, the drive time of the data line can be extended, and a highly accurate voltage can be supplied to the data line.

  In the present invention, the output line of the drive amplifier may be set to a common potential in the drive amplifier sampling period.

  In this way, the power consumption can be reduced by effectively using the drive amplifier sampling period, setting the output line of the drive amplifier to a common potential, and reusing the charge.

  In the present invention, the D / A conversion circuit outputs a maximum gradation voltage as the first gradation voltage and outputs the first gradation voltage when all bits of the gradation data are at the first logic level. The maximum gradation voltage is output as the second gradation voltage, and when all bits of the gradation data are at the second logic level, the minimum gradation voltage is output as the first gradation voltage. At the same time, the minimum gradation voltage may be output as the second gradation voltage.

  In this way, the maximum gradation voltage and the minimum gradation voltage can be adjusted independently of the gradation step, and convenience can be improved.

  The present invention also relates to an integrated circuit device including any of the data drivers described above.

  The present invention also relates to an electronic device including the integrated circuit device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Integrated Circuit Device FIG. 1 shows a circuit configuration example of an integrated circuit device 10 (display driver) including a data driver of this embodiment. Note that the integrated circuit device 10 of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The display panel 400 (electro-optical device in a broad sense) includes a plurality of data lines (for example, source lines), a plurality of scanning lines (for example, gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel can be constituted by an active matrix type panel using switch elements such as TFT and TFD. The display panel may be a panel other than the active matrix system, or a panel other than the liquid crystal panel (organic EL panel or the like).

  The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22.

  The logic circuit 40 (driver logic circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A).

  The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation adjustment data (γ correction data) for adjusting gradation characteristics (γ characteristics) is output to the gradation voltage generation circuit 110, or the power supply voltage is supplied to the power supply circuit 90. Outputs power adjustment data for adjustment. In addition, a write / read process to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28 is controlled.

  The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory 20 to the display panel side. The host (MPU) interface circuit 46 implements a host interface that accesses the memory 20 by generating an internal pulse for each access from the host. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to the memory 20 using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  The data driver 50 is a circuit that generates a data signal for driving the data lines of the display panel. Specifically, the data driver 50 receives image data (grayscale data, display data) from the memory 20, and receives a plurality of (for example, 256 levels) grayscale voltages (reference voltages) from the grayscale voltage generation circuit 110. Then, a voltage (data voltage) corresponding to the image data (gradation data) is selected from the plurality of gradation voltages and is output to the data line of the display panel.

  The scan driver 70 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output as a scanning signal (scanning voltage) to each scanning line of the display panel. . The scan driver 70 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 90 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. Then, the voltage obtained by the boosting is supplied to the data driver 50, the scan driver 70, the gradation voltage generation circuit 110, and the like.

  The gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage and supplies it to the data driver 50. Specifically, the gradation voltage generation circuit 110 can include a ladder resistor circuit that divides a resistance between a high potential side voltage and a low potential side voltage and outputs a gradation voltage to a resistance dividing node. In addition, a gradation register unit in which gradation adjustment data is written, a gradation voltage setting circuit that variably sets (controls) the gradation voltage output to the resistance division node based on the written gradation adjustment data, and the like. Can be included.

2. Data Driver FIG. 2 shows a configuration example of the data driver (source driver) of this embodiment. This data driver drives a data line of a display panel 400 (electro-optical device) such as a liquid crystal panel, and includes a D / A conversion circuit 52 and data line drive circuits 60-1 to 60-N. In FIG. 2, one D / A conversion circuit 52 is shared by a plurality of data line driving circuits 60-1 to 60-N (first to Nth data line driving circuits). A data line driving circuit or the like may be provided for each data line of the display panel, or the data line driving circuit may drive a plurality of data lines in a time division manner. A part or all of the data driver (integrated circuit device) may be integrally formed on the display panel.

  The D / A conversion circuit 52 (voltage generation circuit) receives gradation data DG (image data, display data) from the memory 20 of FIG. 1, for example. Then, the first and second gradation voltages VG1 and VG2 corresponding to the gradation data DG are output.

  Specifically, the D / A conversion circuit 52 receives the gradation data and applies the first and second gradation voltages VG1 and VG2 corresponding to the gradation data to each sampling in the first to Nth sampling periods. Output in time division during the period.

  The data line driving circuits 60-1 to 60-N include gradation generation amplifiers 62-1 to 62-N (GA1 to GAN). Each of these gradation generation amplifiers 62-1 to 62-N has first and second gradation voltages VG1 output from the D / A conversion circuit 52 in each sampling period of the first to Nth sampling periods. , VG2 is sampled to generate a gradation voltage between VG1 and VG2.

  FIG. 3 shows a second configuration example of the data driver. In FIG. 3, the data line drive circuits 60-1 to 60-N further include drive amplifiers 64-1 to 64-N provided at the subsequent stage of the gradation generation amplifiers 62-1 to 62-N.

  A modification in which the drive amplifiers 64-1 to 64-N are not provided is also possible. Details of the D / A converter 52, the data line drive circuits 60-1 to 60-N, the gradation generation amplifiers 62-1 to 62-N, and the drive amplifiers 64-1 to 64-N will be described later.

  The drive amplifiers 64-1 to 64-N (DA1 to DAN) included in the data line drive circuits 60-1 to 60-N generate gradations in the drive amplifier sampling period after the first to Nth sampling periods. The output voltage of the amplifiers 62-1 to 62-N is sampled. In the drive amplifier hold period after the drive amplifier sampling period, the sampled output voltage is output.

  For example, FIG. 4 shows an example of a signal waveform when the D / A conversion circuit 52 is shared by six data line driving circuits GA1 to GA6. The data line driving circuits GA1 to GA6 perform a sampling operation in the sampling periods TS1 to TS6 (first to Nth sampling periods), and perform a holding operation in the subsequent hold periods TH1 to TH6 (first to Nth hold periods). Do.

  The drive amplifiers DA1 to DA6 perform a sampling operation in the drive amplifier sampling period TDS after the sampling periods TS1 to TS6, and perform a hold operation in the subsequent drive amplifier hold period TDH.

  2 and 3, it is not necessary to provide a D / A conversion circuit for each data line driving circuit, and one D / A conversion is performed for a plurality of data line driving circuits 60-1 to 60-N. A circuit 52 may be provided. Therefore, the area occupied by the D / A conversion circuit 52 in the integrated circuit device can be reduced, and the integrated circuit device can be downsized.

  Thus, even if the D / A conversion circuit 52 outputs the first and second gradation voltages VG1 and VG2 in a time division manner, the sampling function of the gradation generation amplifiers 62-1 to 62-N causes the first and second gradation voltages VG1 and VG2 to be output. Appropriate sampling of the voltage in each of the 1st to Nth sampling periods becomes possible.

  Further, when the D / A conversion circuit 52 is used for time division in this way, the total time of the sampling periods TS1 to TS6 becomes longer as shown in FIG. For this reason, for example, the hold period TH6 of the gradation generation amplifier GA6 is shortened, and there is no margin in the drive time of the data line.

  In this regard, if the drive amplifiers DA1 to DA6 are provided after the gradation generation amplifiers GA1 to GA6 as shown in FIG. 3, the drive amplifiers DA1 to DA6 are sampled during the sampling periods TS1 to TS6 as shown at E15 in FIG. DA6 enters the hold operation mode and can drive the data line. Therefore, the drive time of the data line can be extended, and a highly accurate voltage can be supplied to the data line.

  Further, in the conventional data driver, in order to increase the voltage supplied to the data line with high accuracy, for example, in the second half of the driving period, DAC driving for directly driving the data line by the D / A conversion circuit is performed. For this reason, it is necessary to provide a D / A conversion circuit having the same configuration for each data line, which causes an increase in the scale of the integrated circuit device due to the layout area of the D / A conversion circuit.

  In this regard, as will be described later, if the tone generation amplifier and the drive amplifier are provided with a sample hold function and configured by, for example, a flip-around sample hold circuit, so-called offset free can be realized. Accordingly, it is possible to supply a highly accurate voltage to the data line while minimizing the variation in the output voltage to the data line, and thus the above-described DAC drive is not necessary. Therefore, it is not necessary to provide a D / A conversion circuit having the same configuration for each data line, and a single D / A conversion circuit can be shared by a plurality of data line driving circuits as shown in FIGS. Become. Therefore, it is possible to achieve both high accuracy of the voltage of the data line and reduction of the area of the data driver.

  2 and FIG. 3 also has an advantage that the gradation voltage lines can be shared in time division for R (red), G (green), and B (blue).

  Specifically, in the present embodiment, the gradation data bus that connects the memory 20 and the data driver 50 in FIG. 1 is, for example, a 16-bit bus. On the other hand, the number of bits of each of the R, G, and B sub-pixels is 8 bits, and the number of bits of the pixel that is composed of the R, G, and B sub-pixels is 8 × 3 = 24 bits.

  Therefore, in E1 and E2 of FIG. 4, 8-bit gradation data of the subpixel R0 of the first pixel and 8-bit gradation data of the subpixel R1 of the second pixel adjacent to the first pixel are The data is transferred from the memory 20 to the data driver 50 via a 16-bit gradation data bus.

  In E3 of FIG. 4, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit gradation data of the subpixel R0. Then, as indicated by E4, the gradation generating amplifier GA1 performs a sampling operation of VG1 and VG2 in the sampling period TS1, and generates a gradation voltage between VG1 and VG2.

  In E5, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit gradation data of the subpixel R1. Then, as indicated by E6, the gradation generation amplifier GA2 performs a sampling operation of VG1 and VG2 in the sampling period TS2, and generates a gradation voltage between VG1 and VG2.

  In E7 and E8, 8-bit gradation data of the subpixel G0 of the first pixel and 8-bit gradation data of the subpixel G1 of the second pixel are transmitted via the 16-bit gradation data bus. The data is transferred from the memory 20 to the data driver 50.

  In E9, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit gradation data of the subpixel G0. Then, as indicated by E10, the gradation generation amplifier GA3 performs a sampling operation of VG1 and VG2 in the sampling period TS3, and generates a gradation voltage between VG1 and VG2.

  In E11, the D / A conversion circuit 52 outputs first and second gradation voltages VG1 and VG2 corresponding to the 8-bit gradation data of the sub-pixel G1. Then, as indicated by E12, the gradation generation amplifier GA4 performs a sampling operation of VG1 and VG2 in the sampling period TS4 to generate a gradation voltage between VG1 and VG2. In E13 and E14, the gradation data of the subpixels B0 and B1 are transferred, and the same processing as described above is performed.

  If the grayscale data of R0, R1, G0, G1, B0, and B1 is transferred in this way, it is not necessary to provide separate grayscale voltage lines for R, G, and B. The gradation voltage lines can be used in a time division manner for transferring gradation data for R, G, and B. For example, the gradation voltage line can be used for R in E1 and E2 in FIG. 4, the gradation voltage line can be used for G in E7 and E8, and the gradation voltage line can be used for B in E13 and E14.

  For example, when 64 gradation voltage lines are required for each of R, G, and B, the method of providing separate gradation voltage lines for R, G, and B is 64 × 3. = 192 grayscale voltage lines are required.

  In this respect, in the present embodiment, since one gradation voltage line is used for R, G, and B in a time-sharing manner, 64 gradation voltage lines can be used, and the gradation voltage is reduced. The wiring area of the line can be greatly reduced, and the area of the integrated circuit device can be reduced.

3. Data Line Common Potential Setting In this embodiment, a data line common potential setting method (equalization) is employed in order to achieve low power consumption. Specifically, as indicated by E16 in FIG. 4, the output lines of the drive amplifiers DA1 to DA6 are set to a common potential in the drive amplifier sampling period TDS.

  For example, in FIG. 5, a VCOM generation circuit 180 (common voltage generation circuit) generates and outputs a common voltage VCOM (counter electrode voltage) supplied to a common electrode that is a counter electrode of a pixel of the display panel. The generated common voltage VCOM is supplied to the common electrode of the display panel via the VCOM pad (bump).

  Specifically, the VCOM generation circuit 180 outputs either the high potential side common voltage VCOMH or the low potential side common voltage VCOML as the common voltage VCOM based on a polarity inversion signal (not shown). For example, in the case of line inversion driving, since the polarity of the voltage applied to the liquid crystal element is inverted every scanning period, the VCOM generation circuit 180 switches between VCOMH and VCOML and outputs every scanning period. To do.

  In FIG. 5, the output lines of the drive amplifiers DA1 to DA6 are set to the common voltage VCOM, which is a common potential, as indicated by E16 in FIG. 4 in the drive amplifier sampling period TDS. Specifically, in the drive amplifier sampling period, the switch element SVD of FIG. 5 is turned on, and the data lines that are the output lines of the drive amplifiers DA1 to DA6 are set to the common voltage VCOM. The common potential is not limited to VCOM, and may be, for example, a GND potential.

  According to FIG. 5, the charge accumulated in the display panel is reused to charge and discharge the charge on the data lines of the display panel, so that the power consumption can be further reduced.

  As will be described later, the output switch elements SQD of the drive amplifiers DA1 to DA6 are turned off in the drive amplifier sampling period TDS, and the outputs of DA1 to DA6 are in a high impedance state. Therefore, the data line can be efficiently set to the common voltage VCOM by using the period TDS during which the outputs of the drive amplifiers DA1 to DA6 are in a high impedance state. Further, it is possible to prevent the adverse effect of setting the common voltage VCOM from reaching the drive amplifiers DA1 to DA6.

4). Switch Circuits Various modifications of the data driver of this embodiment will be described below. In the following description, in order to simplify the description, the data line driving circuits 60-1 to 60-N sharing the single D / A conversion circuit 52, the gradation generating amplifiers 62-1 to 62-N, and the driving amplifier 64 are used. -1 to 64-N are described as the data line driving circuit 60, the gradation generation amplifier 62, and the driving amplifier 64, respectively, as representatives.

  FIG. 6 shows a first modification of the data driver of this embodiment. In the first modification of FIG. 6, a switch circuit 54 is newly added.

  In FIG. 6, the D / A conversion circuit 52 receives a plurality of gradation voltages (for example, V0 to V128, V0 to V64) via the gradation voltage line from the gradation voltage generation circuit 110 of FIG. Then, the first and second gradation voltages VG1 and VG2 corresponding to the gradation data DG are selected and output from the plurality of gradation voltages. In this case, the first and second gradation voltages VG1 and VG2 output from the D / A conversion circuit 52 are adjacent gradation voltages. Specifically, adjacent gradation voltages (for example, V0, V1, and V1) in a plurality of gradation voltages (V0 to V128, V0 to V64) input to the D / A conversion circuit 52 via the gradation voltage line. V2, V2 and V3).

  For example, in FIG. 7, the gradation data DG is data of 8 bits (256 gradations) D7 to D0. A plurality of gradation voltages V0 to V128 are input to the D / A conversion circuit 52. Here, V0 to V128 has a monotonically decreasing relationship of V0> V1> V2... V127> V128. However, a monotonically increasing relationship of V0 <V1 <V2... V127 <V128 may be established.

  The D / A conversion circuit 52 outputs VG1 = V1 and VG2 = V0 when the gradation data is DG (D7 to D0) = (00000000), (00000001), and (00000010), (00000011). In this case, VG1 = V1 and VG2 = V2 are output. When DG = (00000100) and (00000101), VG1 = V3 and VG2 = V2 are output, and when (00000110) and (00000111), VG1 = V3 and VG2 = V4 are output.

  As described above, the D / A conversion circuit 52 is the gradation voltage corresponding to the gradation data DG among the gradation voltages V0 to V128 input from the gradation voltage generation circuit 110, and is adjacent to the first and second adjacent ones. 2 gradation voltages VG1 and VG2 are output. 6 and 7 are examples in which the D / A conversion circuit 52 generates two kinds of gradation voltages, the first and second gradation voltages VG1 and VG2, the kind of gradation voltages to be output ( The number) is not limited to this.

  The data line driving circuit 60 (data line driving circuits 60-1 to 60-N) is a circuit for driving the data lines of the display panel 400, and the gradation generation amplifier 62 (gradation generation amplifiers 62-1 to 62-N). including. The gradation generation amplifier 62 (gradation generation sample hold circuit) can generate and output a gradation voltage between the first gradation voltage VG1 and the second gradation voltage VG2.

  In FIG. 7, when the gradation data is DG = (00000001), the gradation generation amplifier 62 generates a gradation voltage VS = V0− (V0−V1) / 2 between VG1 = V1 and VG2 = V0. (Sampling) and output. When the gradation data is DG = (00000000), VS = VG2 = V0 is output. When the gradation data is DG = (00000011), a gradation voltage VS = V1- (V1-V2) / 2 between VG1 = V1 and VG2 = V2 is generated and output. When the gradation data is DG = (00000010), VS = VG1 = V1 is output.

  The switch circuit 54 is provided between the D / A conversion circuit 52 and the data line driving circuit 60. The switch circuit 54 may be a component of the D / A conversion circuit 52 or the data line driving circuit 60.

  The switch circuit 54 includes a plurality of switch elements. For example, FIG. 6 includes first to fourth switch elements SW1 to SW4. The number of switch elements is not limited to this, and may be, for example, 8 or 16, as will be described later. Each of the switch elements SW1 to SW4 can be composed of a CMOS transistor. Specifically, it can be constituted by a transfer gate composed of a P-type transistor and an N-type transistor. These transistors are turned on / off by a switch control signal from a switch control signal generation circuit (not shown).

  The switch element SW1 includes a first voltage output node NG1 that is an output node of the first gradation voltage VG1 of the D / A conversion circuit 52, and a first input of the gradation generation amplifier 62 (data line driving circuit 60). Provided with the node NI1. The switch element SW2 is provided between the second voltage output node NG2 that is the output node of the second gradation voltage VG2 of the D / A conversion circuit 52 and the input node NI1 of the gradation generation amplifier 62. These switch elements SW1 and SW2 are exclusively turned on / off. For example, as shown in FIG. 7, when the gradation data is DG = (00000000), SW1 is turned off while SW2 is turned on. When DG = (00000001), SW1 is turned on while SW2 is turned on. Turns off.

  The switch element SW3 is provided between the voltage output node NG1 of the D / A conversion circuit 52 and the input node NI2 of the gradation generation amplifier 62. The switch element SW4 is provided between the voltage output node NG2 of the D / A conversion circuit 52 and the input node NI2 of the gradation generation amplifier 62. These switch elements SW3 and SW4 are exclusively turned on / off. For example, when DG = (00000001), SW3 is turned off while SW4 is turned on. When DG = (00000010), SW3 is turned on while SW4 is turned off.

  As shown in FIG. 7, when the gradation data is DG = (00000000), the D / A conversion circuit 52 outputs VG1 = V1 and VG2 = V0. Further, the switch elements SW1, SW2, SW3, and SW4 of the switch circuit 54 are turned off, on, off, and on, respectively. Therefore, VI1 = VG2 = V0 and VI2 = VG2 = V0 are input to the input nodes NI1 and NI2 of the gradation generation amplifier 62, respectively. As a result, the gradation generation amplifier 62 outputs a gradation voltage (sampling voltage) VS = V0.

  On the other hand, when the gradation data is DG = (00000001), the switch elements SW1, SW2, SW3, and SW4 are turned on, off, off, and on, respectively. Therefore, the gradation generation amplifier 62 receives VI1 = VG1 = V1 and VI2 = VG2 = V0 at its input nodes NI1 and NI2, and outputs the gradation voltage VS = V0− (V0−V1) / 2. That is, a gradation voltage corresponding to gradation data DG = (00000001) is output.

  When the gradation data is DG = (00000010), the D / A conversion circuit 52 outputs VG1 = V1 and VG2 = V2. The switch elements SW1, SW2, SW3, and SW4 are turned on, off, on, and off, respectively. Therefore, the gradation generation amplifier 62 receives VI1 = VG1 = V1 and VI2 = VG1 = V1 at its input nodes NI1 and NI2, and outputs the gradation voltage VS = V1.

  On the other hand, when the gradation data is DG = (00000011), the switch elements SW1, SW2, SW3, and SW4 are turned off, on, on, and off, respectively. Therefore, the gradation generation amplifier 62 receives VI1 = VG2 = V2 and VI2 = VG1 = V1 at its input nodes NI1 and NI2, and outputs the gradation voltage VS = V1− (V1−V2) / 2. That is, the gradation voltage corresponding to the gradation data DG = (00000011) is output.

  As is apparent from FIG. 7, the switch elements SW1 to SW4 are turned on / off based on the lower bits of the gradation data DG. That is, the switch elements SW1 to SW4 are turned on / off based on the switch control signal generated based on the lower bits of the gradation data DG. For example, when the lower bits D1 and D0 of the gradation data DG are (00), the switch elements SW1, SW2, SW3, and SW4 are turned off, on, off, and on, respectively, as shown in FIG. , (01), on, off, off, on respectively. In the case of (10), it is on, off, on and off, and in the case of (11), it is off, on, on and off.

  According to the data driver of the present embodiment described above, since the gradation voltage can be generated by the gradation generation amplifier 62, the number (type) of gradation voltages generated by the gradation voltage generation circuit 110 in FIG. 1 is reduced. it can. As a result, the number of gradation voltage lines can be reduced, and the circuit scale of the D / A conversion circuit 52 can be reduced.

For example, when the gradation data DG is 8 bits and the number of gradations is 2 ⁸ = 256 gradations, the gradation voltage generation circuit 110 needs to generate 256 gradation voltages in the conventional method. The D / A conversion circuit 52 requires a selector group for selecting a gray scale voltage corresponding to the gray scale data DG from these 256 gray scale voltages. Therefore, the gradation voltage generation circuit 110 and the D / A conversion circuit 52 are increased in scale. In addition, since the number of gradation voltage lines is 256, the area occupied by the wiring region also increases.

  In this regard, according to the data driver of the present embodiment of FIG. 6, since the gradation voltage is generated by the gradation generation amplifier 62, the gradation voltage generation circuit 110 may generate, for example, 128 gradation voltages. The D / A conversion circuit 52 may be provided with a selector group for selecting a voltage from these 128 gradation voltages. Therefore, the circuit scale can be greatly reduced as compared with the conventional method. Further, the number of gradation voltage lines can be reduced to 128, and the area of the wiring region can be greatly reduced. Actually, since the gradation generation amplifier 62 generates a voltage obtained by dividing the first and second gradation voltages VG1 and VG2, 128 + 1 = 129 gradation voltage lines are required in the above case.

  Further, according to the data driver of FIG. 6, the tone generation amplifier 62 can be provided with a sample hold function. Therefore, a voltage with little variation can be supplied to the data line without performing DAC driving in which the data line is directly driven by the D / A conversion circuit 52. That is, a highly accurate voltage can be supplied to the data line with a relatively small and simple circuit configuration. Further, by providing the tone generation amplifier 62 with a sample and hold function, a configuration in which one D / A conversion circuit 52 is shared by a plurality of data line driving circuits 60 becomes possible, and the circuit can be further reduced in scale. .

  Further, according to the data driver of FIG. 6, the switch circuit 54 is provided between the D / A conversion circuit 52 and the data line driving circuit 60. Accordingly, based on the first and second gradation voltages VG1 and VG2 from the D / A conversion circuit 52, for example, as shown in FIG. 7, (VI1, VI2) = (V0, V0), (V1, V0). , (V1, V1), (V2, V1)... Can be input to the gradation generation amplifier 62. Thereby, the gradation generation amplifier 62 is monotonously decreased (or monotonically increased), for example, VS = V0, V0− (V0−V1) / 2, V1, V1− (V1−V2) / 2, V2. Therefore, it is possible to output an appropriate gradation voltage with a simple circuit configuration.

5). Flip Around Sample / Hold Circuit The gradation generation amplifier 62 can be configured by a so-called flip around sample / hold circuit. Here, the flip-around sample-and-hold circuit, for example, samples the charge according to the input voltage in the sampling capacitor in the sampling period, performs the flip-around operation of the sampling capacitor in the hold period, and stores the accumulated charge Is a circuit that outputs a voltage corresponding to 1 to its output node.

  The flip-around sample-and-hold circuit will be described in more detail with reference to FIGS. 8A and 8B.

  For example, in FIGS. 8A and 8B, the gradation generation amplifier 62 configured by a flip-around sample-and-hold circuit includes an operational amplifier OP1 and first and second sampling capacitors CS1 and CS2 (a plurality of sampling amplifiers CS1 and CS2). Sampling capacitors).

  The sampling capacitor CS1 is provided between the inverting input terminal (first input terminal in a broad sense) of the operational amplifier OP1 and the input node NI1 of the gradation generation amplifier 62. As shown in FIG. 8A, charge corresponding to the input voltage VI1 of the input node NI1 is accumulated in the capacitor CS1 in the sampling period.

  The sampling capacitor CS2 is provided between the inverting input terminal of the operational amplifier OP1 and the input node NI2 of the gradation generation amplifier 62. The capacitor CS2 accumulates charges according to the input voltage VI2 of the input node NI2 during the sampling period.

  As shown in FIG. 8A, during the sampling period, the output of the operational amplifier OP1 is fed back to the node NEG of the inverting input terminal of OP1. The non-inverting input terminal (second input terminal in a broad sense) of the operational amplifier OP1 is set to AGND that is an analog reference voltage. Therefore, the node NEG to which one ends of the capacitors CS1 and CS2 are connected is set to AGND by the imaginary short function of the operational amplifier OP1. As a result, charges corresponding to the input voltages VI1 and VI2 are accumulated in the capacitors CS1 and CS2.

  As shown in FIG. 8B, in the hold period, the gradation generation amplifier 62 outputs the output voltage VQG (= VS) corresponding to the charges accumulated in the sampling capacitors CS1 and CS2 in the sampling period as its output node. Output to NQG. Specifically, a flip-around operation is performed in which the other ends of the capacitors CS1 and CS2, which are connected to the node NEG at one end thereof, are connected to the output terminal of the operational amplifier OP1, thereby depending on the charges accumulated in CS1 and CS2. Output voltage VQG.

  If the gradation generating amplifier 62 is configured by the flip-around sample-and-hold circuit as described above, so-called offset free can be realized.

  For example, the offset voltage generated between the inverting input terminal and the non-inverting input terminal of the operational amplifier OP1 is VOF, AGND = 0, the input voltage during the sampling period is VI1 = VI2 = VI, and the capacitors CS1 connected in parallel, Let CS2 be the parallel capacitance value of CS2. Then, the charge Q accumulated in the sampling period is expressed by the following equation.

Q = (VI−VOF) × CS (1)
On the other hand, when the voltage of the node NEG in the hold period is VX and the output voltage is VQG, the charge Q ′ accumulated in the hold period is expressed by the following equation.

Q ′ = (VQG−VX) × CS (2)
When the amplification factor of the operational amplifier OP1 is A, VQG is expressed as the following equation.

VQG = −A × (VX−VOF) (3)
Then, since Q = Q ′ by the law of charge conservation, the following equation is established.

(VI−VOF) × CS = (VQG−VX) × CS (4)
Therefore, according to the above equations (3) and (4),
VQG = VI-VOF + VX = VI-VOF + VOF-VQG / A
Is established. Therefore, the output voltage VQG of the gradation generation amplifier 62 is expressed by the following equation.

VQG = {1 / (1 + 1 / A)} × VI (5)
As apparent from the above equation (5), the output voltage VQG of the gradation generation amplifier 62 does not depend on the offset voltage VOF, and the offset can be canceled, so that offset free can be realized.

  For example, when a plurality of data lines are driven by the plurality of data line driving circuits 60, if the offset voltage VOF appears in the output voltage VQG, the output voltage VQG varies between the data lines, and the display quality deteriorates.

  In this regard, if the flip-around type sample and hold circuit is used, the offset can be canceled, so that the variation in the output voltage VQG between the data lines can be minimized. Therefore, a highly accurate voltage with little variation can be supplied to the data lines, and display quality can be improved. Further, since the DAC drive for directly driving the data line by the D / A conversion circuit 52 is not necessary, high-speed driving and simplification of control can be realized.

  9A and 9B show detailed configuration examples of the gradation generation amplifier 62 using a flip-around sample-and-hold circuit.

  9A and 9B includes an operational amplifier OP1, first and second sampling switch elements SS1 and SS2, and first and second sampling capacitors CS1, It includes CS2, a feedback switch element SFG, and first and second flip-around switch elements SA1 and SA2. An output switch element SQG is also included. It should be noted that modifications such as omitting some of these components or adding other components are possible. In addition, the switch elements SS1, SS2, SA1, SA2, SFG, and SQG can be configured by CMOS transistors such as transfer gates, for example.

  An analog reference voltage AGND (a given reference voltage in a broad sense) is set to the non-inverting input terminal (second input terminal) of the operational amplifier OP1.

  The sampling switch element SS1 and the sampling capacitor CS1 are provided between the input node NI1 of the gradation generation amplifier 62 and the inverting input terminal (first input terminal) of the operational amplifier OP1. The sampling switch element SS2 and the sampling capacitor CS2 are provided between the input node NI2 of the gradation generation amplifier 62 and the inverting input terminal of the operational amplifier OP1.

  The feedback switch element SFG is provided between the output terminal of the operational amplifier OP1 and the inverting input terminal of OP1.

  The flip-around switch element SA1 is provided between the first connection node NS1 between the switch element SS1 and the capacitor CS1 and the output terminal of the operational amplifier OP1. The flip-around switch element SA2 is provided between the second connection node NS2 between the switch element SS2 and the capacitor CS2 and the output terminal of the operational amplifier OP1.

  As shown in FIG. 9A, in the sampling period, the sampling switch elements SS1 and SS2 and the feedback switch element SFG are turned on, and the flip-around switch elements SA1 and SA2 are turned off. Thereby, the sampling operation of the flip-around sample-hold circuit described with reference to FIG.

  On the other hand, as shown in FIG. 9B, in the hold period, the sampling switch elements SS1 and SS2 and the feedback switch element SFG are turned off, and the flip-around switch elements SA1 and SA2 are turned on. Thus, the hold operation of the flip-around sample / hold circuit described with reference to FIG. 8B can be realized.

  The output switch element SQG is provided between the output terminal of the operational amplifier OP1 and the output node NQG of the gradation generation amplifier 62. As shown in FIG. 9A, the output switch element SQG is turned off during the sampling period. This makes it possible to prevent the output of the gradation generation amplifier 62 from entering a high impedance state and transmitting an uncertain voltage during the sampling period to the subsequent stage.

  On the other hand, as shown in FIG. 9B, the output switch element SQG is turned on in the hold period. Thereby, the voltage VQG which is the gradation voltage generated in the sampling period can be output.

  Next, the circuit operation of FIGS. 9A and 9B will be described with reference to FIG. The first gradation voltage VG1 from the D / A conversion circuit 52 is input to the node NG1, and the second gradation voltage having a voltage level different from that of VG1 is input to the node NG2 as described in FIG. VG2 is input.

  As described with reference to FIG. 7, one of the switch elements SW1 and SW2 of the switch circuit 54 is exclusively turned on according to the gradation data DG. Any one of the switch elements SW3 and SW4 is exclusively turned on according to the gradation data DG.

  In the sampling period, the switch control signals input to the sampling switch elements SS1 and SS2 and the feedback switch element SFG are active (H level), so that the switch elements SS1, SS2, and SFG are turned on. On the other hand, since the switch control signals input to the flip-around switch elements SA1 and SA2 and the output switch element SQG become inactive (L level), the switch elements SA1, SA2 and SQG are turned off.

  In the hold period, the switch control signals input to the switch elements SS1, SS2, and SFG are inactive, and thus SS1, SS2, and SFG are turned off. On the other hand, since the switch control signal input to the switch elements SA1, SA2, and SQG becomes active, SA1, SA2, and SQG are turned on.

  As shown by A1 and A2 in FIG. 10, the sampling switch elements SS1 and SS2 are turned off after the feedback switch element SFG is turned off. In this way, the adverse effect of charge injection can be minimized as will be described later. As indicated by A3, the flip-around switch elements SA1 and SA2 and the output switch element SQG are turned on after the sampling switch elements SS1 and SS2 are turned off.

  11A and 11B show a grayscale generation amplifier of the second configuration example, and FIG. 12 is an explanatory diagram of the circuit operation.

  As shown in B1 and B2 of FIG. 12, in the second configuration example of FIGS. 11A and 11B, the first and second gradation voltages from the D / A conversion circuit 52 are in the sampling period. Are input to the gradation generation amplifier 62 in a time division manner. Then, as shown in B3 of FIG. 12, when the sampling switch element SS1 is turned off, the first gradation voltage input and sampled at B1 is held. Also, as shown in B4, when the sampling switch element SS2 is turned off, the second gradation voltage input and sampled at B2 is held.

  In the second configuration example of FIGS. 11A to 12, the sampling period is shortened compared to FIGS. 9A to 10, so that there is no time margin for the sampling operation and the output voltage VQG There is a risk that the accuracy of the lowering.

  On the other hand, in the configurations of FIGS. 9A to 10, since the sampling period can be made sufficiently long, an accurate sample-and-hold operation can be realized, and a highly accurate output voltage VQG can be output.

  In the second configuration example, since it is necessary to turn off the switch elements SS1 and SS2 in time series, the switch element SS1 is turned off before the switch element SFG is turned off as shown in B3 and B5 of FIG. turn into. Therefore, at the timing when the switch element SS1 is turned off, the switch element SFG is in the on state and the node NEG is not in the high impedance state, and therefore, the switch element SS1 is adversely affected by charge injection and clock feedthrough in the switch element SS1. .

  On the other hand, in the configurations of FIGS. 9A to 10, switch control at the timings indicated by A1, A2, and A3 in FIG. 10 is possible, so that adverse effects such as charge injection can be minimized. And fluctuations in the output voltage VQG can be minimized.

  For example, FIG. 13A shows an example of a transfer gate TG serving as a switch element. Switch control signals CNN and CNP are input to the gates of the N-type transistor TN and the P-type transistor TP constituting the transfer gate TG. When the transfer gate TG is turned off, clock feedthrough occurs due to parasitic capacitances Cgd and Cgs between the gate and the drain or between the gate and the source. In addition, when the transfer gate TG is turned off, the channel charge flows into the drain and the source, and charge injection occurs.

  In this regard, in this embodiment, the sampling switch elements SS1 and SS2 are turned off as shown in FIG. 13C after the feedback switch element SFG is turned off as shown in FIG. 13B. The adverse effects of charge injection and clock feedthrough can be reduced as compared with the second configuration example of FIGS.

  That is, as shown in FIG. 13B, if the switch element SFG is turned off when the switch elements SS1 and SS2 are on, the switch element SFG is affected by charge injection and clock feedthrough. However, as shown in FIG. 13C, at the timing when the switch elements SS1 and SS2 are turned off, the switch element SFG is turned off and the node NEG is in a high impedance state. Therefore, since it is not affected by the clock feedthrough and charge injection at SS1 and SS2, the adverse effects due to charge injection and feedthrough can be reduced as compared with the second configuration example.

  Note that switch control signals CNN and CNP having an amplitude of VDD to VSS are input to the gates of the transistors TN and TP of the transfer gate TG in FIG. Accordingly, when the drain or source potential of the transfer gate TG is set to VSS or VDD, an imbalance occurs between the charge amount from the N-type transistor TN and the charge amount from the P-type transistor TP, and the charge due to charge injection cancels out. It will remain without being.

  In this regard, immediately before the switching element SFG is turned off as shown in FIG. 13B, VDD (second power supply in a broad sense) and VSS (first power in a broad sense) are connected to the non-inverting input terminal of the operational amplifier OP1. AGND, which is an intermediate voltage of the power supply), is set, and the potential of the node NEG is set to AGND = (VDD + VSS) / 2 by the imaginary short function of the operational amplifier OP1. Therefore, immediately before the switch element SFG is turned off, the source and drain of the SFG are set to AGND, there is no dependency of the input gradation voltage, and the charge amount from the N-type transistor of the transfer gate TG and the P-type transistor Therefore, the adverse effect of charge injection caused by the switching element SFG being turned off can be minimized.

  FIG. 14 shows a configuration example of the operational amplifier OP1. The operational amplifier OP1 performs a class A amplification operation. In FIG. 14, transistors TD1, TD2, TD3, TD4, and TD5 constitute a differential section (differential stage) of the operational amplifier OP1, and transistors TD6 and TD7 constitute an output section (output stage) of OP1. In FIG. 14, a phase compensation capacitor CCP is provided between the output node ND1 of the differential section and the output node ND2 of the operational amplifier OP1.

6). Drive Amplifier FIG. 15 shows a second modification of the data driver. In FIG. 15, the data line driving circuit 60 further includes driving amplifiers 64 (driving amplifiers 64-1 to 64-N) as compared with FIG.

  The drive amplifier 64 (drive sample and hold circuit, output amplifier) is provided in the subsequent stage of the gradation generation amplifier 62 and drives the data lines of the display panel 400. The drive amplifier 64 can also be configured by the flip-around sample-and-hold circuit described with reference to FIGS. 8A and 8B. In this way, the offset cancellation function of the flip-around type sample-and-hold circuit can minimize the variation in the output voltage of the drive amplifier 64, thereby improving the display quality.

  16 and 17 show a specific configuration example of the drive amplifier 64. FIG. The configuration of the drive amplifier 64 is not limited to this, and various modifications may be made such as omitting some of the components or adding other components.

  The drive amplifier 64 includes a second operational amplifier OP2 and a sampling capacitor CS. The sampling capacitor CS is provided between the inverting input terminal (first input terminal) of the operational amplifier OP2 and the input node NQG of the drive amplifier 64.

  As shown in FIG. 16, charges corresponding to the input voltage VQG of the input node NQG are accumulated in the sampling capacitor CS during the drive amplifier sampling period. That is, in the driving amplifier sampling period, the gradation generation amplifier 62 performs a hold operation, and outputs a voltage VQG corresponding to the charge accumulated in the sampling period. The drive amplifier 64 samples the output voltage VQG in the drive amplifier sampling period.

  The drive amplifier 64 outputs the output voltage VQD corresponding to the charge accumulated in the capacitor CS in the drive amplifier sampling period of FIG. 16 in the drive amplifier hold period as shown in FIG. At this time, the gradation generation amplifier 62 performs a sampling operation, and the output switch element SQG is off.

  More specifically, the drive amplifier 64 includes an operational amplifier OP2, a sampling switch element SS and a sampling capacitor CS, a second feedback switch element SFD, and a flip-around switch element SA. An output switch element SQD is also included.

  Here, the AGND reference voltage (given reference voltage) is set to the non-inverting input terminal (second input terminal) of the operational amplifier OP2.

  The sampling switch element SS and the sampling capacitor CS are provided between the input node NQG of the drive amplifier 64 and the inverting input terminal (first input terminal) of the operational amplifier OP2. The feedback switch element SFD is provided between the output terminal and the inverting input terminal of the operational amplifier OP2.

  The flip-around switch element SA is provided between a connection node NS between the switch element SS and the capacitor CS and the output terminal of the operational amplifier OP2. The output switch element SQD is provided between the output terminal of the operational amplifier OP2 and the output node NQD of the drive amplifier 64.

  As shown in FIG. 16, in the drive amplifier sampling period, the sampling switch element SS and the feedback switch element SFD are turned on, and the flip-around switch element SA is turned off. Thereby, the sampling operation of the flip-around sample / hold circuit can be realized.

  On the other hand, as shown in FIG. 17, in the hold period for the drive amplifier, the sampling switch element SS and the feedback switch element SFD are turned off, and the flip-around switch element SA is turned on. Thereby, the hold operation of the flip-around sample / hold circuit can be realized.

  As shown in FIG. 16, the output switch element SQD is turned off during the drive amplifier sampling period. As a result, the output of the drive amplifier 64 becomes a high impedance state, and it is possible to prevent an uncertain voltage during the sampling period from being transmitted to the subsequent stage. Further, as shown in FIG. 17, the switch element SQD is turned on in the drive amplifier hold period. Thereby, the voltage sampled in the sampling period can be output to the subsequent stage.

  If the drive amplifier 64 as described above is provided, the voltage VQG output by the gradation generation amplifier 62 during the hold period can be sampled during the drive amplifier sampling period as shown in FIG. As shown in FIG. 17, during the sampling period of the gradation generation amplifier 62, the drive amplifier 64 can output the voltage VQD corresponding to the voltage VQG to the data line instead of the gradation generation amplifier 62.

  For example, if the sampling period of the gradation generation amplifier 62 is lengthened, the output of the gradation generation amplifier 62 is in a high impedance state during the long sampling period, so that the data line cannot be driven and the drive time has a margin. Disappear.

  On the other hand, when the drive amplifier 64 as shown in FIGS. 16 and 17 is provided, the drive amplifier 64 is in the hold operation mode during the sampling period of the gradation generation amplifier 62, and the data line can be driven. As a result, the driving time can be extended and the display quality can be improved.

  In particular, when the D / A conversion circuit 52 is shared by a plurality of data line driving circuits 60 and the D / A conversion circuit 52 supplies grayscale voltages to the plurality of data line driving circuits 60 in a time division manner. The total time of the plurality of sampling periods of the plurality of data line driving circuits 60 becomes very long.

  In this regard, if the drive amplifier 64 as shown in FIGS. 16 and 17 is provided, the drive amplifier 64 is in the hold operation mode and drives the data lines during the plurality of sampling periods of the plurality of data line drive circuits 60. it can. Accordingly, a highly accurate voltage can be supplied to the data line, and the display quality can be improved.

  When the drive amplifier 64 is provided in addition to the gradation generation amplifier 62, the operational amplifier OP1 included in the gradation generation amplifier 62 is configured by an amplifier that performs, for example, a class A amplification operation, and the operation included in the drive amplifier 64 is included. The amplifier OP2 may be configured by an amplifier that performs, for example, a class AB amplification operation. Specifically, the operational amplifier OP2 is configured by an amplifier that performs class A amplification operation in the sampling period and performs class AB amplification operation in the hold period.

  For example, the operational amplifier OP1 of FIG. 14 constituting the gradation generation amplifier 62 is an amplifier for class A amplification operation. By using such a class A amplification amplifier, the circuit can be simplified and the power consumption can be easily reduced. When the drive amplifier 64 is provided in the subsequent stage, the drive load of the gradation generation amplifier 62 is only the sampling capacitor CS of the drive amplifier 64 and the like, and since it is a low load, it can be driven without any problem.

  On the other hand, the drive amplifier 64 needs to drive a data line having a large parasitic capacitance during the hold period, and the drive load becomes high. Therefore, the operational amplifier OP2 of the drive amplifier 64 is configured by an amplifier capable of class AB amplification operation.

  FIG. 18 shows a configuration example of the operational amplifier OP2 capable of performing a class AB amplification operation. The operational amplifier OP2 includes a differential section (differential stage) composed of transistors TE1, TE2, TE3, TE4, and TE5, and an output section (output stage) composed of transistors TE6 and TE7.

  Unlike the operational amplifier OP1 of FIG. 14, the operational amplifier OP2 of FIG. 18 is provided with a switch element SE1 to which the bias voltage BS is supplied at one end and the other end is connected to the gate node NE3 of the transistor TE7 of the output unit. ing. The capacitor CCP2 is provided between the output node NE1 of the differential section and the gate node NE3 of the transistor TE7.

  The switch element SE1 is turned on in the drive amplifier sampling period. As a result, the operational amplifier OP2 of FIG. 18 functions as an amplifier for class A amplification operation because the bias voltage BS is input to the gate of the transistor TE7 in the output section. On the other hand, the switch element SE1 is turned off in the drive amplifier hold period. As a result, the gate node NE3 of the transistor TE7 enters a floating state, and the voltage at the node NE2 varies according to the voltage variation at the node NE1 due to the capacitor CCP2. As a result, the operational amplifier OP2 of FIG. 18 functions as an amplifier for class AB amplification operation.

7). Number of Switch Elements FIG. 19 shows a third modification of the data driver. In FIG. 16, the switch circuit 54 is provided with four switch elements SW1 to SW4, but the present embodiment is not limited to this. For example, the switch circuit 54 of FIG. 19 is provided with eight switch elements SW1 to SW8. Note that the number of switch elements may be more than eight (for example, 16, 32, etc.).

  In FIG. 16, the tone generation amplifier 62 is provided with two sampling switch elements SS1 and SS2, two sampling capacitors CS1 and CS2, and two flip-around switch elements SA1 and SA2. These numbers are not limited to two. For example, in FIG. 19, four sampling switch elements SS1 to SS4, four sampling capacitors CS1 to CS4, and four flip-around switch elements SA1 to SA4 are provided. Note that these numbers may be larger than four (for example, eight, sixteen, etc.).

  Also in FIG. 19, switch elements SW1 and SW2, SW3 and SW4, SW5 and SW6, and SW7 and SW8 are turned on / off exclusively. Then, by setting these switch elements SW1 to SW8 to ON or OFF, the gradation voltage between the first and second gradation voltages VG1 and VG2 is generated in the gradation generation amplifier 62 in the same manner as in FIG. Can be made. Specifically, in FIG. 7, one gradation voltage between VG1 and VG2 is generated, but in FIG. 19, three gradation voltages between VG1 and VG2 can be generated.

For example, when the gradation data is 8 bits and the number of gradations is 2 ⁸ = 256 gradations, the gradation voltage generation circuit 110 only needs to generate 128 gradation voltages in the configuration of FIG. The D / A conversion circuit 52 may be provided with a selector group for selecting a voltage from 128 gradation voltages.

  On the other hand, according to the configuration of FIG. 19, the gradation voltage generation circuit 110 only needs to generate 64 gradation voltages, and the D / A conversion circuit 52 has a voltage from among the 64 gradation voltages. It is sufficient to provide a selector group for selecting. Therefore, the circuit scale of the gradation voltage generation circuit 110 and the D / A conversion circuit 52 and the number of gradation voltage lines can be further reduced, and the area of the integrated circuit device including the data driver can be further reduced.

8). Configuration Example of D / A Conversion Circuit FIG. 20 shows a configuration example of the D / A conversion circuit 52. The D / A conversion circuit 52 includes a first D / A converter DACA and a second D / A converter DACB.

  Here, the first D / A converter DACA (odd DAC) has a gradation from among a plurality of gradation voltages V1, V3, V5, V7... Vm-1 (a plurality of input voltages in a broad sense). By selecting a gradation voltage (voltage in a broad sense) corresponding to data (input data in a broad sense), a first gradation voltage VG1 (a first voltage in a broad sense) is output.

  On the other hand, the second D / A converter DACB (even number DAC) has gradation data (input data) out of a plurality of gradation voltages V0, V2, V4, V6, V8... Vm (a plurality of input voltages). ) Is selected, a second gradation voltage VG2 (second voltage in a broad sense) is output. Note that the voltage difference between the first and second gradation voltages VG1 and VG2 is a voltage corresponding to, for example, at least 1LSB of gradation data (input data).

  The DACA includes a plurality of selector blocks BL1A, BL2A, and BL3A in which the output of the selector included in the preceding selector block is input to the selector included in the succeeding selector block. On the other hand, the DACB includes a plurality of selector blocks BL1B, BL2B, and BL3B in which the output of the selector included in the preceding selector block is input to the selector included in the succeeding selector block. The number of selector blocks is not limited to three as shown in FIG. 20, but may be two or four or more.

  FIG. 21 shows a detailed configuration example of the first and second D / A converters DACA and DACB. Each of these DACA and DACB selects one gradation voltage from a plurality of gradation voltages by a so-called tournament method, and outputs them as first and second gradation voltages VG1 and VG2.

  As shown in FIG. 21, the first-stage selector block BL1A of DACA includes a plurality of two-input selectors S10A to S13A (2-to1 selector). On the other hand, the selector block BL1B at the first stage of DACB includes a plurality of 3-input selectors S10B to S13B (3 to 1 selector). The switch elements included in these selectors can be constituted by, for example, transfer gates composed of P-type transistors and N-type transistors.

  The two-input selector S10A (i-th two-input selector, i = 0) of the plurality of two-input selectors of the DACA is based on grayscale data (input data) and V1 (fourth i + 1 input voltage) and V3 ( Any one of the (4i + 3) th gradation voltages (input voltages) is selected and output to the 4-input selector S20A of the selector block BL2A at the subsequent stage.

  Further, the 2-input selector S11A (i-th 2-input selector, i = 1) selects one of V5 and V7 gradation voltages (4i + 1, 4i + 3 input voltages) based on the gradation data, Output to the 4-input selector S20A in the subsequent stage. The same applies to the two-input selectors S12A and S13A.

  Then, the 4-input selector S20A selects one of the output voltages of the 2-input selectors S10A, S11A, S12A, and S13A and outputs it as the first gradation voltage VG1.

  The three-input selector S10B (i-th three-input selector, i = 0) of the DACB's three-input selectors is based on the gradation data (input data), and the gradation voltages (0th, V2, V2, and V4) 4i, 4i + 2, and 4i + 4) are selected and output to the 4-input selector S20B of the selector block BL2B at the subsequent stage.

  Also, the 3-input selector S11B (i-th 3-input selector, i = 1) is any of the V4, V6, and V8 gradation voltages (the 4i, 4i + 2, and 4i + 4 input voltages) based on the gradation data. Is output to the subsequent 4-input selector S20B. The same applies to the three-input selectors S12B and S13B.

  Then, the 4-input selector S20B selects any one of the output voltages of the 3-input selectors S10B, S11B, S12B, and S13B and outputs it as the second gradation voltage VG2.

  As shown in FIG. 21, in the DACB, the gradation voltage V4 is input to the three-input selectors S10B and S11B in common. The gradation voltage V8 is commonly input to the three-input selectors S11B and S12B, and the gradation voltage V12 is commonly input to the three-input selectors S12B and S13B.

  The DACA 2-input selectors S10A to S13A are controlled based on a DACA-dedicated selector control signal EN1A.

  Specifically, based on the voltage level of the selector control signal EN1A, one of the two switch elements included in the two-input selectors S10A to S13A is turned on and the other switch element is turned off.

  The DACB three-input selectors S10B to S13B are controlled based on the DACB dedicated selector control signals EN1B [2] to EN1B [0].

  Specifically, based on the voltage levels of the selector control signals EN1B [2] to EN1B [0], any one of the three switch elements included in the three-input selectors S10B to S13B is turned on. Other switch elements are turned off.

  On the other hand, the 4-input selector S20A included in the second-stage (second and subsequent) selector block BL2A of DACA and the 4-input selector S20B included in the second-stage (second and subsequent) selector block BL2B of DACB are common. Control is performed based on selector control signals EN2 [3] to EN2 [0].

  Specifically, based on the voltage levels of the selector control signals EN2 [3] to EN2 [0], any one of the four switch elements of the four-input selector S20A is turned on, and the other The switch element is turned off. As a result, the first gradation voltage VG1 is output from DACA.

  Further, based on the voltage levels of the selector control signals EN2 [3] to EN2 [0], any one of the four switch elements of the four-input selector S20B is turned on and the other switch elements are turned off. become. As a result, the second gradation voltage VG2 is output from the DACB.

  According to the configuration shown in FIG. 21, the number of DACA and DACB selector switch elements can be reduced, and the number of selector control signals can be reduced.

  For example, FIG. 22 shows a second configuration example of DACA and DACB. In FIG. 22, the DACA has a configuration in which one gradation voltage can be selected from 16 gradation voltages V0 to V15. The DACB is also configured such that one gradation voltage can be selected from the 16 gradation voltages V0 to V15.

  The 4-input selector included in the first-stage selector block BL1A of DACA is controlled based on the selector control signals EN1A [3] to EN1A [0], and the 4-input selector included in the second-stage selector block BL2A is a selector. Control is performed based on the control signals EN2A [3] to EN2A [0].

  Similarly, the 4-input selector included in the first-stage selector block BL1B of the DACB is controlled based on the selector control signals EN1B [3] to EN1B [0], and the 4-input selector included in the second-stage selector block BL2B is: Control is performed based on the selector control signals EN2B [3] to EN2B [0].

  According to the first configuration example of FIG. 21, the number of switch elements can be reduced from 40 to 28 as compared to the second configuration example of FIG. Further, the number of selector control signals can be reduced from 16 to 8. Therefore, the circuit area of the D / A conversion circuit 52 can be reduced as compared with FIG. In addition, since the number of selector control signals is reduced, the wiring area of the signal line can be reduced, and the area of the integrated circuit device can be reduced.

9. Adjustment of Minimum Gradation Voltage and Maximum Gradation Voltage FIG. 23 shows a modification of the D / A conversion circuit 52. In FIG. 23, it is possible to adjust the minimum gradation voltage VGML (for example, the minimum gradation voltage based on 0V) and the maximum gradation voltage VGMH (for example, the maximum gradation voltage based on 0V).

  Specifically, the first D / A converter DACA in FIG. 23 receives the gradation voltages V1, V3, V5... V63, selects a voltage corresponding to the gradation data, and selects the gradation voltage VG1 ′. Output as. The second D / A converter DACB receives the gradation voltages V0, V2, V4... V64, selects a voltage corresponding to the gradation data, and outputs it as the gradation voltage VG2 '. As these DACA and DACB, for example, the configuration described in FIG. 21 (a configuration expanded from 16 gradations to 64 gradations) can be adopted. Note that the configuration described in FIG. 22 may be employed.

  The 3-input selector SGA selects any one of the gradation voltage VG1 'from the DACA, the maximum gradation voltage VGMH, and the minimum gradation voltage VGML, and outputs it as the first gradation voltage VG1. The 3-input selector SGB selects any one of the gradation voltage VG2 'from the DACB, the maximum gradation voltage VGMH, and the minimum gradation voltage VGML, and outputs it as the second gradation voltage VG2.

  As shown in FIG. 24, when all the bits D7 to D0 of the gradation data DG are “0” (first logical level in a broad sense) (when DG = (00000000)), D / The A conversion circuit 52 outputs the maximum gradation voltage VGMH as the first gradation voltage VG1, and also outputs the maximum gradation voltage VGMH as the second gradation voltage VG2. That is, the three-input selectors SGA and SGB in FIG. 23 both select and output the maximum gradation voltage VGMH.

  On the other hand, when all the bits D7 to D0 of the gradation data DG are “1” (second logic level in a broad sense) (when DG = (11111111)), the D / A conversion circuit 52 The minimum gradation voltage VGML is output as the first gradation voltage VG1, and the minimum gradation voltage VGML is also output as the second gradation voltage VG2. That is, the three-input selectors SGA and SGB in FIG. 23 both select and output the minimum gradation voltage VGML.

  On the other hand, when the gradation data is other than DG = (00000000) or (11111111), the selectors SGA and SGB use VG1 ′ and VG2 ′ from DACA and DACB as the first and second gradation voltages VG1. , VG2 is output. That is, VG1 'and VG2' output by DACA and DACB are output as VG1 and VG2 by the method described in FIG.

  FIG. 25 shows a configuration example of the gradation voltage generation circuit 110 for realizing the methods of FIGS. In FIG. 25, the amplifier OPBH generates and outputs the maximum gradation voltage VGMH, and the amplifier OPBL generates and outputs the minimum gradation voltage VGML. The maximum gradation voltage VGMH and the minimum gradation voltage VGML are resistance-divided by the ladder resistor circuit RDL, so that gradation voltages V0, V1, V2,... V63, V64 are generated at each tap position of the RDL. And output to the D / A conversion circuit 52.

  24 and 25, V0 is a high potential side voltage and V64 is a low potential side voltage. However, V0 may be a low potential side voltage and V64 may be a high potential side voltage.

  It is desirable that the amplifiers OPBH and OPBL can variably set the voltage values of the maximum gradation voltage VGMH and the minimum gradation voltage VGML. Specifically, the voltage value is variably set by register setting based on the command. An operational amplifier or the like that converts the impedance of the voltage divided by the ladder resistor circuit RDL may be further provided.

  In the present embodiment, as described with reference to FIG. 7 and the like, the gradation generation amplifier 62 generates gradation voltages such as between V0 and V1, between V1 and V2, and between V2 and V3. In this case, the step size of the gradation voltage is equal as shown in FIG.

  However, it may be desirable not to engrave gradations at equal intervals between VGMH and V0 in FIG. 25 or between V64 and VGML. For example, when adjusting contrast independently of gamma correction, it is desirable that only VGML and VGMH can be controlled independently.

  Therefore, in FIGS. 24 and 25, the D / A conversion circuit 52 outputs VG1 = VG2 = VGMH when the gradation data is, for example, DG = (00000000), and the gradation data is, for example, DG = (11111111). In this case, VG1 = VG2 = VGML is output. In this way, the voltage difference between VGMH and V0 and the voltage difference between V64 and VGML can be arbitrarily set without gradations being evenly spaced. Accordingly, contrast and the like can be adjusted by setting VGMH and VGML independently of the adjustment of the gamma gradation curve by setting V0 to V64, and convenience can be improved.

10. Electronic Device FIGS. 26A and 26B show a configuration example of an electronic device (electro-optical device) including the integrated circuit device 10 of the present embodiment. Various modifications may be made such as omitting some of the components shown in FIGS. 26A and 26B and adding other components (such as a camera, an operation unit, or a power supply). . The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  In FIGS. 26A and 26B, the host device 410 is, for example, an MPU, a baseband engine, or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. Also, the image processing controller 420 in FIG. 26B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 26A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 26B, the integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, at least once, together with different terms having a broader meaning or the same meaning (electro-optical device, first input terminal, second input terminal, reference voltage, first power supply, second power supply, etc.) The described terms (display panel, inverting input terminal, non-inverting input terminal, AGND, VSS, VDD, and the like) can be replaced with the different terms anywhere in the specification or the drawings. In addition, the configurations and operations of the data driver, D / A conversion circuit, switch circuit, data line driving circuit, gradation generation amplifier, driving amplifier, integrated circuit device, electronic device, and the like are also limited to those described in this embodiment. However, various modifications can be made.

1 is a configuration example of an integrated circuit device according to an embodiment. 2 is a configuration example of a data driver according to the present embodiment. 2 shows a second configuration example of a data driver. The signal waveform example for demonstrating operation | movement of this embodiment. Explanatory drawing of the common electric potential setting method of a data line. The 1st modification of a data driver. FIG. 5 is an operation explanatory diagram of a D / A conversion circuit, a switch circuit, and a gradation generation amplifier. 8A and 8B are explanatory diagrams of a flip-around sample-and-hold circuit. FIGS. 9A and 9B are configuration examples of a gradation generation amplifier using a flip-around sample-and-hold circuit. Explanatory drawing of the circuit operation | movement of a gradation generation amplifier. 11A and 11B show a second configuration example of the gradation generation amplifier. Explanatory drawing of the circuit operation | movement of the gradation generation amplifier of a 2nd structural example. FIG. 13A to FIG. 13C are explanatory diagrams of the switch control method of the present embodiment. 6 is a configuration example of an operational amplifier of a gradation generation amplifier. The 2nd modification of a data driver. A detailed configuration example of a drive amplifier. A detailed configuration example of a drive amplifier. The structural example of the operational amplifier of a drive amplifier. The 3rd modification of a data driver. 2 shows a configuration example of a D / A conversion circuit. 1 shows a first configuration example of first and second D / A converters. The 2nd structural example of a 1st, 2nd D / A converter. A modification of the D / A conversion circuit. The operation | movement explanatory drawing of the D / A converter circuit of a modification. 2 is a configuration example of a gradation voltage generation circuit. FIG. 26A and FIG. 26B are configuration examples of electronic devices.

Explanation of symbols

VG1, VG2 first and second gradation voltages, SW1 to SW8 switch elements,
OP1, OP2 operational amplifier, SS, SS1-SS4 sampling switch element,
CS, CS1 to CS4 sampling capacitors,
SFG, SFD feedback switch element,
SA, SA1 to SA4 flip-around switch element,
SQG, SQD output switch element,
10 integrated circuit device, 20 memory, 22 memory cell array,
24 row address decoder, 26 column address decoder,
28 write / read circuit, 40 logic circuit, 42 control circuit,
44 display timing control circuit, 46 host interface circuit,
48 RGB interface circuit, 50 data driver,
52 D / A conversion circuit, 54 switch circuit,
60 60-1 to 60-N data line drive circuit, 62, 62-1 to 62-N gradation generation amplifier,
64 64-1 to 64-N drive amplifier, 70 scan driver,
90 power supply circuit, 110 gradation voltage generation circuit, 400 display panel,
410 Host device, 420 Image processing controller

Claims (18)

A data driver for driving a data line of an electro-optical device,
Receiving the gradation data, the first and second gradation voltages corresponding to the gradation data are output in a time-sharing manner during each sampling period of the first to Nth sampling periods (N is an integer of 2 or more). A D / A conversion circuit;
Including first to Nth data line driving circuits sharing the D / A conversion circuit;
Each data line driving circuit of the first to Nth data line driving circuits is:
The first and second gradation voltages output from the D / A conversion circuit in each sampling period of the first to Nth sampling periods are sampled, and the first gradation voltage and the second gradation voltage are sampled. A data driver comprising a gradation generation amplifier that generates a gradation voltage between gradation voltages. In claim 1,
The gradation driver includes a flip-around type sample and hold circuit. In claim 2,
The gradation generation amplifier is
An operational amplifier;
The first amplifier is provided between the first input terminal of the operational amplifier and the first input node of the grayscale generation amplifier, and charges corresponding to the input voltage of the first input node are accumulated in the sampling period. A sampling capacitor;
Provided between the first input terminal of the operational amplifier and the second input node of the grayscale generation amplifier, charges corresponding to the input voltage of the second input node are accumulated during the sampling period. A second sampling capacitor
A data driver, wherein an output voltage corresponding to the charge accumulated in the first and second sampling capacitors in the sampling period is output in the hold period. In claim 2,
The gradation generation amplifier is
An operational amplifier having a given reference voltage set at its second input terminal;
A first sampling switch element and a first sampling capacitor provided between the first input node of the gradation generation amplifier and a first input terminal of the operational amplifier;
A second sampling switch element and a second sampling capacitor provided between the second input node of the gradation generation amplifier and the first input terminal of the operational amplifier;
A feedback switch element provided between an output terminal of the operational amplifier and the first input terminal;
A first flip-around switch element provided between a first connection node between the first sampling switch element and the first sampling capacitor and an output terminal of the operational amplifier;
A second flip-around switch element provided between a second connection node between the second sampling switch element and the second sampling capacitor and an output terminal of the operational amplifier; A data driver characterized by that. In claim 4,
In the sampling period, the first and second sampling switch elements and the feedback switch element are turned on, and the first and second flip-around switch elements are turned off.
In the hold period, the first and second sampling switch elements and the feedback switch element are turned off, and the first and second flip-around switch elements are turned on. driver. In claim 5,
The gradation generation amplifier is
An output switch element provided between the output terminal of the operational amplifier and an output node of the gradation generation amplifier;
In the sampling period, the output switch element is turned off,
A data driver, wherein the output switch element is turned on during a hold period. In claim 5 or 6,
The data driver, wherein the first and second sampling switch elements are turned off after the feedback switch element is turned off. In any of claims 4 to 7,
The high-potential-side power supply voltage of the first and second sampling switch elements, the feedback switch element, and the first and second flip-around switch elements is set to VDD and the low-potential-side power supply voltage is VSS. In this case, the reference voltage set to the second input terminal of the operational amplifier is set to a voltage between VDD and VSS. In any one of Claims 1 thru | or 8.
Each data line driving circuit of the first to Nth data line driving circuits is:
A data driver comprising a drive amplifier provided at a subsequent stage of the gradation generation amplifier. In claim 9,
The data driver according to claim 1, wherein the drive amplifier comprises a flip-around type sample and hold circuit. In claim 10,
The drive amplifier is
A second operational amplifier;
A sampling capacitor provided between the first input terminal of the second operational amplifier and the input node of the drive amplifier, and storing a charge corresponding to the input voltage of the input node in the drive amplifier sampling period; Including
A data driver, wherein an output voltage corresponding to the electric charge accumulated in the sampling capacitor in the drive amplifier sampling period is output in the drive amplifier hold period. In claim 10,
The drive amplifier is
A second operational amplifier having a given reference voltage set at its second input terminal;
A sampling switch element and a sampling capacitor provided between an input node of the drive amplifier and a first input terminal of the second operational amplifier;
A second feedback switch element provided between an output terminal of the second operational amplifier and the first input terminal;
A data driver comprising: a flip-around switch element provided between a connection node between the sampling switch element and the sampling capacitor and an output terminal of the second operational amplifier. In claim 11 or 12,
The operational amplifier included in the gradation generation amplifier is configured by an amplifier that performs a class A amplification operation,
The data driver, wherein the second operational amplifier included in the drive amplifier includes an amplifier that performs a class AB amplification operation. In any of claims 9 to 13,
The drive amplifier included in each data line drive circuit of the first to Nth data line drive circuits is:
The output voltage of the gradation generation amplifier is sampled in the driving amplifier sampling period after the first to Nth sampling periods, and the output voltage is sampled in the driving amplifier hold period after the driving amplifier sampling period. A data driver characterized by outputting an output voltage. In claim 14,
The data driver, wherein an output line of the drive amplifier is set to a common potential in the drive amplifier sampling period. In any one of Claims 1 thru | or 15,
The D / A conversion circuit includes:
When all bits of the gradation data are at the first logic level, the maximum gradation voltage is output as the first gradation voltage and the maximum gradation voltage is also used as the second gradation voltage. When all the bits of the gradation data are at the second logic level, the minimum gradation voltage is output as the first gradation voltage, and the minimum gradation is also used as the second gradation voltage. A data driver characterized by outputting a regulated voltage.   An integrated circuit device comprising the data driver according to claim 1.   An electronic apparatus comprising the integrated circuit device according to claim 17.

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