JP2007306462A - Signal selection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal selection circuit capable of reducing crosstalk without giving an adverse effect on an external circuit connected to the signal selection circuit. <P>SOLUTION: The signal selection circuit 10 is provided with sample-and-hold circuits 12, 16 capable of holding a level of non-selection signal lines SL1, SL3 arranged adjacent to a signal line SL2 to be selected to a voltage of an electric signal of the non-selection signal lines SL1, SL3, and the sample-and-hold circuits 12, 16 hold the level of the non-selection signal lines SL1, SL3 to the voltage of the electric signal during the period of time that the selected signal line SL2 outputs the electric signal to an output terminal Vout. Since the level of the non-selection signal lines SL1, SL3 is maintained by the voltage of the electric signal of an external circuit or the like, an electric effect is not exerted on the external circuit or the like, and the impedance of the signal lines SL1, SL3 located adjacent to both sides of the signal line SL2 is reduced to suppress forming of a coupling capacitance between the signal lines thereby decreasing the crosstalk. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal selection circuit that selects one signal line from signal lines connected to a plurality of input terminals and outputs an electric signal of the selected signal line to an output terminal.

As a signal selection circuit that selects one signal line from signal lines connected to a plurality of input terminals and outputs an electric signal of the selected signal line to an output terminal, for example, disclosed in Patent Document 1 below. There is a “signal input selection switching circuit”. In this circuit, in order to reduce crosstalk between input terminals and signal lines arranged adjacent to each other under high-density mounting, a configuration in which other than the selected signal line can be connected to a bias power supply is adopted. This lowers the impedance of the other signal lines adjacent to the selected signal line rather than the impedance of the selected signal line, thereby generating crosstalk that can affect the high-impedance signal line via the coupling capacitance between the lines. It is possible to prevent.
JP-A-8-56146

  However, according to the “signal input selection switching circuit” disclosed in Patent Document 1, it is possible to reduce the impedance of these signal lines by connecting other than the selected signal lines to the bias power supply. If a voltage from such a bias source is applied to a signal line, a current flows into the signal source via the signal line. For this reason, if the predetermined voltage level is not set between the bias source and the signal source, the voltage of the bias source is always received during the period when the signal line is not selected. There is a problem in that the failure of the signal source can be caused by stress due to such a voltage.

  In addition, in the case of adopting a configuration in which a protection circuit or the like is provided on the signal source side so as to receive a voltage from such a bias source, a signal source that may be connected to the signal input selection switching circuit Such a protection circuit is required for all of the above. In this case, not only the circuit configuration of the signal source is complicated, but also a new problem that the cost increases due to an increase in the number of parts is caused.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a signal selection circuit that can reduce crosstalk without affecting a connected external circuit. It is in.

  In order to achieve the above object, in the signal selection circuit according to claim 1, the signal line (SL1) connected to a plurality of input terminals (Vin1, Vin2, Vin3 [or Vin2, Vin3, Vin4]). , SL2, SL3 [or SL2, SL3, SL4]), one signal line (for example, SL2 [or SL3]) is selected, and an electric signal of the selected signal line (SL2 [or SL3]) is output to an output terminal ( Vout), a potential of a non-selected signal line (SL1, SL3 [or SL2, SL4]) arranged adjacent to one signal line (SL2 [or SL3]) to be selected Voltage holding means (12, 16 [or 32, 36]) capable of holding the voltage of the electric signal of the non-selected signal line (SL1, SL3 [or SL2, SL4]), and the first signal line During the period when the electrical signal is output from (SL2 [or SL3]) to the output terminal (Vout) The voltage holding means (12, 16 [or 32, 36]) holds the potential of the non-selected signal line (SL1, SL3 [or SL2, SL4]) at the voltage of the electric signal. And The numbers in () or [] may correspond to the symbols described in the “Best Mode for Carrying Out the Invention” column (the same applies hereinafter).

In order to achieve the above object, in the signal selection circuit according to claim 2, the signal lines (SL1, SL2, SL3) connected to the plurality of input terminals (Vin1, Vin2, Vin3) A signal selection circuit that selects a signal line (for example, SL2) and outputs an electric signal of the selected signal line (SL2) to an output terminal (Vout), the plurality of input terminals (Vin1, Vin2, Vin3) And a plurality of sample-and-hold circuits (12, 14, and 16) to which the respective inputs are connected, and a plurality of sample-and-hold circuits (12, 14, and 16) provided so as to be short-circuited and opened. Are connected to the respective outputs of the first switch (SA11, SA12, SA13) and the plurality of sample-and-hold circuits (12, 14, 16), and the outputs are combined into the output terminal (Vout). Multiple second connected to Switch (SA21, SA22, SA23) and sampling / holding control of the plurality of sample hold circuits (12, 14, 16), on / off control of the plurality of first switches (SA11, SA12, SA13) and the plurality of A control circuit (18) capable of ON / OFF control of the second switches (SA21, SA22, SA23),
The control circuit (18)
(1) The plurality of first switches (SA11, SA12, SA13) and the plurality of second switches (SA21, SA22, SA23) are all turned off, and the plurality of sample hold circuits (12, 14, 16) are all sampled. From the controlled state (pre-sampling state; Fig. 4),
(2) The sample hold circuit (12, 16) connected to the non-selected signal lines (SL1, SL3) arranged adjacent to the one signal line (SL2) to be selected is in the hold state, and this sample hold circuit ( 12, 16) after controlling the first switches (SA11, SA13) connected to the ON state (sampling state; FIG. 5),
(3) The sample hold circuit (14) of the first signal line (SL2) is controlled to be in the hold state, and the second switch (SA22) of the sample hold circuit (14) is controlled to be in the ON state (hold state; FIG. 6). ) Is a technical feature.

In order to achieve the above object, in the signal selection circuit according to claim 3, the signal lines (SL1, SL2) connected to the plurality of input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...). , SL3, SL4, SL5,...)), One signal line (for example, SL3) is selected, and an electric signal of the selected signal line (SL3) is output to the output terminal (Vout), A plurality of first switches (SB11, SB12, SB13, SB14, SB15,...) Connected to the respective input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...), And the plurality of first terminals. A first common line (CL1) commonly connected to the outputs of one switch (SB11, SB12, SB13, SB14, SB15,...) And a first connected to the first common line (CL1). Sample hold circuit (32) and a plurality of input terminals (Vin1, Vin2, Vin3, Vin4, Vin5) ,..., A plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) Connected to the respective inputs, and the plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) A second common line (CL2) commonly connected to the outputs of the first and second sample-and-hold circuits in which an input is connected to the second common line (CL2) and an output is connected to the output terminal (Vout). (34) and a plurality of third switches (SB31, SB32, SB33, SB34, SB35,...) Connected to the plurality of input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...), Respectively. The third common line (CL3) connected in common to the respective outputs of the plurality of third switches (SB31, SB32, SB33, SB34, SB35,...) And the third common line (CL3) have inputs. Between the input and output of the third sample and hold circuit (36) to be connected and the first sample and hold circuit (32) A fourth switch (SB41) provided so as to be short-circuited and opened, a fifth switch (SB51) provided so as to be short-circuited and opened between the input and output of the third sample hold circuit (36), and the plurality of first switches Switches (SB11, SB12, SB13, SB14, SB15,...), The plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) And the plurality of third switches (SB31, SB32, SB33, SB34,. SB35,...), And the sampling / holding of each of the first sample hold circuit (32), the second sample hold circuit (34), and the third sample hold circuit (36) can be controlled. A control circuit (38), the control circuit (38),
(1) “Unselected signal line arranged on one side adjacent to one signal line (SL3) to be selected among the plurality of first switches (SB11, SB12, SB13, SB14, SB15,...) The first switch (SB12) connected to (SL2) is turned on, the first switch (SB13) connected to this one signal line (SL3) is turned off, the other side adjacent to this one signal line The first switch (SB14) connected to the non-selected signal line (SL4) arranged in the off state ”,“ among the plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) The second switch (SB22) connected to the non-selected signal line (SL2) arranged on one side adjacent to the one signal line (SL3) to be selected is turned off, and the signal line (SL3) is connected to the first signal line (SL3). The second switch (SB23) to be connected is turned on, and a non-selected signal arranged on the other side adjacent to the one signal line (SL3) The second switch (SB24) connected to (SL4) is turned off "," one signal line (SL3) to be selected from among the plurality of third switches (SB31, SB32, SB33, SB34, SB35, ...) The third switch (SB32) connected to the non-selected signal line (SL2) disposed on one side adjacent to the third switch (SB32) connected to the one signal line (SL3) is turned off. The third switch (SB34) connected to the non-selected signal line (SL4) arranged on the other side adjacent to the one signal line (SL3) "," the fourth switch (SB41) and the fifth switch (SB51) are turned off "," all the first sample hold circuit (32), the second sample hold circuit (34) and the third sample hold circuit (36) are in a sampling state " From the controlled state (sampling preparation state; 9),
(2) After controlling the first sample hold circuit (32) and the third sample hold circuit (36) to the hold state and the fourth switch (SB41) and the fifth switch (SB51) to the on state (sampling state) ; FIG. 10),
(3) The second sample and hold circuit (34) is controlled to be in a hold state, and the second switch (SB23) connected to the first signal line (SL3) is controlled to be in an off state (hold state; FIG. 11). Characteristic.

  According to the first aspect of the present invention, the potential of the non-selected signal line (SL1, SL3 [or SL2, SL4]) arranged adjacent to the one signal line (SL2 [or SL3]) to be selected is set to the non-selected state. Voltage holding means (12, 16 [or 32, 36]) capable of holding the voltage of the electric signal of the signal line (SL1, SL3 [or SL2, SL4]). During the period in which an electric signal is output from one signal line (SL2 [or SL3]) to the output terminal (Vout), the voltage holding means (12, 16 [or 32, 36]) is not connected to the non-selected signal line ( The potential of SL1, SL3 [or SL2, SL4]) is held at the voltage of the electric signal. As a result, during the period in which the electric signal of one signal line (SL2 [or SL3]) to be selected is output from the output terminal (Vout), the signal line (SL2 [or SL3]) is arranged adjacent to this one signal line. Since the potential of the non-selected signal line (SL1, SL3 [or SL2, SL4]) is held at the voltage of the electric signal, the non-selected signal line (SL1, SL3 [or SL2, SL4]) Low impedance can be achieved. That is, for the external circuit connected to the signal selection circuit (10 [or 30]), the external circuit is kept held at the voltage of its own electrical signal, so that the external circuit is not electrically affected. It is possible to reduce the impedance of the non-selected signal line (SL1, SL3 [or SL2, SL4]). Therefore, crosstalk can be reduced without affecting the connected external circuit.

  In the invention of claim 2, a plurality of sample and hold circuits (12, 14, 16), a plurality of first switches (SA11, SA12, SA13), a plurality of second switches (SA21, SA22, SA23) and a control circuit (18 ). Then, the control circuit (18), as the pre-sampling state (FIG. 4), (1) all the plurality of first switches (SA11, SA12, SA13) and the plurality of second switches (SA21, SA22, SA23) are turned off. From the state in which all of the sample and hold circuits (12, 14, 16) are controlled to the sampling state, the sampling state (FIG. 5) is changed to be adjacent to (2) one signal line (SL2) to be selected. The sample hold circuits (12, 16) connected to the non-selected signal lines (SL1, SL3) are in the hold state, and the first switches (SA11, SA13) connected to the sample hold circuits (12, 16) are in the on state. Therefore, the non-selected signal lines (SL1, SL3) arranged adjacent to the one signal line (SL2) to be selected are changed by the sample hold circuit (12, 16) connected thereto. The electric signal potential It is held in lifting state. Therefore, after this, as the hold state (FIG. 6), (3) the sample hold circuit (14) of the signal line (SL2) 1 is held, and the second switch (SA22) of this sample hold circuit (14) is turned on. By controlling the on state, the electric signal of the selected one signal line (SL2) is output to the output terminal (Vout) via the second switch (SA22) in the on state.

  Thereby, when the electric signal of the selected one signal line (SL2) is output from the output terminal (Vout), the non-selected signal line arranged adjacent to the one signal line (SL2). Since the potential of (SL1, SL3) is maintained at the voltage of the electric signal, the unselected signal lines (SL1, SL3) can be set to low impedance. That is, for the external circuit connected to the signal selection circuit (10), since it is maintained at the voltage of its own electrical signal, the non-selected signal is not affected electrically. The impedance of the line can be reduced. Therefore, crosstalk can be reduced without affecting the connected external circuit.

  In the invention of claim 3, a plurality of first switches (SB11, SB12, SB13, SB14, SB15,...), A plurality of second switches (SB21, SB22, SB23, SB24, SB25,...), A plurality of third switches. (SB31, SB32, SB33, SB34, SB35,...), Fourth switch (SB41), fifth switch (SB51), first common line (CL1), second common line (CL2), third common line (CL3) ), A first sample hold circuit (32), a second sample hold circuit (34), a third sample hold circuit (36), and a control circuit (38). Then, the control circuit (38), as a sampling preparation state (FIG. 9), selects (1) “one signal line to be selected from a plurality of first switches (SB11, SB12, SB13, SB14, SB15,...) The first switch (SB12) connected to the non-selected signal line (SL2) arranged on one side adjacent to SL3) is turned on, and the first switch (SB3) connected to this one signal line (SL3) ( SB13) is in the off state, the first switch (SB14) connected to the non-selected signal line (SL4) disposed on the other side adjacent to the one signal line is in the off state "," a plurality of second switches (SB21, SB22, SB23, SB24, SB25,...), A second switch connected to a non-selected signal line (SL2) arranged on one side adjacent to one signal line (SL3) to be selected (SB22) is turned off, and the second switch (SB23) connected to the first signal line (SL3) is turned on. The second switch (SB24) connected to the non-selected signal line (SL4) arranged on the other side adjacent to the signal line (SL3) "," a plurality of third switches (SB31, SB32, SB33, SB34, SB35,...), The third switch (SB32) connected to the non-selected signal line (SL2) arranged on one side adjacent to one signal line (SL3) to be selected is turned off, The third switch (SB33) connected to the one signal line (SL3) is turned off and connected to the non-selected signal line (SL4) arranged on the other side adjacent to the one signal line (SL3). The third switch (SB34) turned on "," the fourth switch (SB41) and the fifth switch (SB51) are turned off "," first sample hold circuit (32), second sample hold circuit (34) " And the third sample and hold circuit (36) are all controlled to the sampling state. (2) First sample hold circuit (32) and third sample hold circuit (36) are held, and fourth switch (SB41) and fifth switch (SB51) are turned on. The non-selected signal lines (SL2, SL4) arranged adjacent to the one signal line (SL3) to be selected are controlled by the sample and hold circuit (32, 36) connected thereto at this time. Is maintained in a state in which the potential of the electric signal is maintained. Therefore, after this, as a hold state (FIG. 11), (3) the second sample hold circuit (34) is in the hold state, and the second switch (SB23) connected to the one signal line (SL3) is turned off. By controlling, the electric signal of the selected one signal line (SL3) is output to the output terminal (Vout).

  Thereby, when the electrical signal of the selected one signal line (SL3) is output from the output terminal (Vout), the unselected signal line arranged adjacent to the one signal line (SL3). Since the potential of (SL2, SL4) is maintained at the voltage of the electric signal, the unselected signal lines (SL2, SL4) can be set to low impedance. That is, for the external circuit connected to the signal selection circuit (30), since it is maintained at the voltage of its own electrical signal, the non-selected signal is not affected electrically. The impedance of the line can be reduced. Regardless of the number of signal lines (SL1, SL2, SL3,...), The sample and hold circuit includes a first sample and hold circuit (32), a second sample and hold circuit (34), and a third sample and hold circuit (36). Therefore, the number of components can be reduced and the circuit scale can be reduced as compared with the case where a sample hold circuit is provided for each input terminal (Vin1, Vin2, Vin3,...). Therefore, the crosstalk can be reduced without affecting the connected external circuit, and further, the device can be reduced in weight and size and the device cost can be reduced.

Hereinafter, embodiments of a signal selection circuit of the present invention will be described with reference to the drawings.
[First Embodiment]
First, the signal selection circuit 10 according to the first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the signal selection circuit 10 according to the first embodiment includes a plurality of input terminals Vin1, Vin2, Vin3,... (Hereinafter referred to as “input terminal Vin1” in accordance with selection information #N input from the selection terminal SEL. Etc.)) is selected from a plurality of signal lines SL1, SL2, SL3,... (Hereinafter “signal line SL1 etc.”), and the selected signal line SL2 is transmitted. It has a function of outputting an electrical signal to an output terminal Vout, mainly a plurality of input terminals Vin1, etc., a plurality of sample hold circuits 12, 14, 16,... (Hereinafter “sample hold circuit 12 etc.”), a plurality of Switch SA11, SA12, SA13,... (Hereinafter “switch SA11 etc.”), a plurality of switches SA21, SA22, SA23,... (Hereinafter “switch SA21 etc.”), control circuit 18, output terminal Vout, selection terminal SEL It is al configuration. For example, an A / D converter is connected to the output terminal Vout, and an external circuit that outputs information (selection information) for selecting the one signal line is connected to the selection terminal SEL.

  The sample hold circuit 12 or the like has a function to sample and hold an electric signal (mainly an analog signal) input to the input IN, and each input IN is connected to a corresponding input terminal Vin1 or the like. Yes. For example, the input IN of the sample and hold circuit 12 is input to the input terminal Vin1, the input IN of the sample and hold circuit 14 is input to the input terminal Vin2, and the input IN of the sample and hold circuit 16 is input to the input terminal Vin3. Corresponding to Vin1 etc., each sample hold circuit 12 etc. are connected. Sample hold circuits for the number of input terminals Vin1 and the like (the number of channels) are prepared.

  In the present embodiment, such a sample hold circuit 12 and the like are configured by, for example, a circuit shown in FIG. Here, the configuration of the sample hold circuit 12 and the like will be described with reference to FIG. As shown in FIG. 2A, the sample hold circuit 12 or the like has an operational amplifier OPa in which a non-inverting input is connected to the ground potential and an output is connected to the output OUT of the circuit, and one end side is an inverting input of the operational amplifier OPa. The connected capacitor Ca, the switch SWa1 connected between the other end of the capacitor Ca and the input IN of the circuit, and the switch SWa2 connected between the inverting input of the operational amplifier OPa and the output of the operational amplifier OPa And a switch SWa3 connected between the other end of the capacitor Ca and the output of the operational amplifier OPa.

  These switches SWa1, SWa2, SWa3 are composed of, for example, MOS transistors and are composed of semiconductor switching elements that can be switched on and off according to the voltage level of a control signal applied from the outside. In the embodiment, the switches SWa1 and SWa2 are N-channel transistors, and the switch SWa3 is a P-channel transistor. Accordingly, when a predetermined control voltage is applied from the outside, the switches SWa1 and SWa2 are controlled to be in the on state, the switch SWa3 is in the off state, the switches SWa1 and SWa2 are in the off state, and the switch SWa3 is in the on state. That is, the states of the switches SWa1 and SWa2 and the switch SWa3 are exclusively controlled.

  As described above, the switches SWa1, SWa2, and SWa3 can each be configured by a single MOS transistor. However, in this configuration, the switch SWa1, SWa2, and SWa3 may not be turned on in relation to the input voltage by the input IN. For example, when the switches SWa1 and SWa2 are composed of N-channel transistors (threshold voltage Vth = 1V), when the voltage of the input IN is 0V, the gate-source voltage Vgs is 5V-0V = 5V> Vth ( = 1V), the transistor is turned on. On the other hand, when the voltage of the input IN is 5V, the gate-source voltage Vgs is 5V-5V = 0V <Vth (= 1V), so that the transistor is turned off and not turned on. Since the polarity of the P-channel transistor is reversed, it may be impossible to turn on when the voltage of the input IN is 0V. That is, if the switches SWa1, SWa2, and SWa3 are each configured by a single MOS transistor, the voltage range of the input IN becomes narrow.

  Therefore, as a modification of the present embodiment, for example, as shown in FIG. 3, an N-channel transistor and a P-channel transistor are connected in parallel to the switches SWa1, SWa2, and SWa3, and either one of the gates is connected. A configuration using a so-called CMOS switch, which is configured with an inverter interposed therebetween. Accordingly, when the voltage of the input IN is lower than the threshold voltage Vth of the transistor, the N-channel transistor is turned on (the P-channel transistor is turned off), and the voltage of the input IN is When the threshold voltage Vth is higher than the threshold voltage Vth of the transistor, the P-channel transistor is turned on (the N-channel transistor is turned off), and the voltage of the input IN is an intermediate voltage between them. Can turn on both N-channel and P-channel transistors. Therefore, it is possible to ensure a wide allowable range of the voltage of the input IN as compared with the case where a single MOS transistor is used as the switches SWa1, SWa2, and SWa3.

  By configuring the sample hold circuit 12 and the like in this way, when the switches SWa1 and SWa2 are controlled to be in the on state and the switch SWa3 is in the off state, the capacitor Ca of the input IN and the ground potential is connected. Therefore, the input electric signal is charged in the capacitor Ca, that is, sampled (sampling state). On the other hand, when the switches SWa1 and SWa2 are controlled to be in the off state and the switch SWa3 is in the on state, respectively, instead of blocking between the input IN and the capacitor Ca, between the capacitor Ca and the output OUT. Therefore, the electric signal charged in the capacitor Ca is held, that is, held (held state). Thereby, the sample hold circuit 12 and the like are realized.

  FIG. 2B shows the most basic sample-and-hold circuit, which is connected between an operational amplifier OPb whose voltage follower is connected and whose output is connected to the output OUT, and the non-inverting input of the operational amplifier OPb. Switch SWb and a capacitor Cb connected between the non-inverting input of the operational amplifier OPb and the ground potential.

  This switch SWb is also a semiconductor switching element that can be controlled on and off from the outside, like the sample-and-hold circuit switch SWa1 shown in FIG. 2A. For example, an N-channel MOS transistor or a CMOS switch shown in FIG. It is configured. In the case of this sample and hold circuit, the sampling state is controlled when the switch SWb is in the off state, and the hold state is controlled when the switch SWb is in the on state. For this reason, there is a merit that external control is simplified compared with that shown in FIG. 2A in that the sampling state and the hold state can be switched by the on / off control of one switch SWb. There is a demerit in that the signal is easily affected by the offset voltage of the operational amplifier OPb.

  That is, in the case of the sample and hold circuit shown in FIG. 2A, since the offset voltage of the operational amplifier OPa is absorbed by the charging of the capacitor Ca, a voltage error corresponding to the offset voltage is not output as it is. On the other hand, in the case of the sample and hold circuit shown in FIG. 2B, the offset voltage of the operational amplifier OPb is added in series to the capacitor Cb, so that a voltage error corresponding to the offset voltage is output as it is. For this reason, the sample and hold circuit shown in FIG. 2B has a problem that the voltage accuracy of the held electric signal can be lowered although external control is simplified.

  Therefore, in the present embodiment, from the viewpoint of emphasizing the voltage accuracy of the electric signal output from the sample hold circuit 12 or the like, the sample hold circuit shown in FIG. When emphasizing simplification of hold state control, the sample hold circuit shown in FIG. 2B is employed.

  As shown in FIG. 1, the sample hold circuit 12 and the like configured as described above are connected to a switch SA21 or the like at the output OUT, and the output OUT is connected to the output terminal Vout via the switch SA21 or the like. It is comprised so that it can output to. In the present embodiment, the signal line SL0 is connected to the output terminal Vout. Further, a control line is connected to the sample hold circuit 12 or the like so that a control voltage output from the control circuit 18 (corresponding to “external” described above) can be applied to the switch SWa1 or the like (the chain line shown in FIG. ).

  As shown in FIG. 1, the sample hold circuit 12 or the like is connected to a switch SA11 or the like that can short-circuit and open the input and output thereof. These switches SA11 and the like are semiconductor switching elements constituted by, for example, N-channel type MOS transistors, similarly to the switches SWa1 and the like of the sample hold circuit 12 and the like described above, and control voltages applied from the control circuit 18 described later. Is configured to be capable of on / off control (broken line shown in FIG. 1).

  Similarly to the switch SA11 and the like, the switch SA21 and the like connected to the respective outputs OUT of the sample and hold circuit 12 and the like are semiconductor switching elements such as an N-channel MOS transistor and are turned on and off by a control voltage applied from the control circuit 18. It is configured to be controllable (broken line shown in FIG. 1). The outputs of these SA21 and the like are collected and connected to the output terminal Vout, and the output OUT of the sample hold circuit connected to the switch controlled to be turned on by the control circuit 18 can be output to the output terminal Vout. It is configured as follows.

  The control circuit 18 has a function capable of on / off controlling the above-described switches SA11 and SA21 according to selection information #N input from the selection terminal SEL. For example, the control circuit 18 is configured by a predetermined logic circuit or a microcomputer. Yes. In the case of the present embodiment, for example, if a plurality of input terminals Vin1 and the like have a 7-channel configuration (Vin1 to Vin7), each input is based on selection information #N (# 0 to # 7) input as 3-bit data. The control circuit 18 is configured so that the signal lines SL1 (# 1) to SL7 (# 7) connected to the terminals Vin1 to Vin7 can be selected (# 0 indicates no selection of signal lines).

  Further, as described above, the control circuit 18 applies a control voltage capable of ON / OFF control of the switch SWa1, etc., the switch SA11, etc., and the switch SA21, etc. constituting the sample hold circuit 12, etc. Etc., a control line is connected between the switch SA11 and the like (a chain line and a broken line shown in FIG. 1).

  In the signal selection circuit 10 configured as described above, the input terminals Vin1 and the like are generally arranged in the order of Vin1, Vin2, Vin3,..., For example, the input terminal Vin1 is on one side of the input terminal Vin2. Input terminals Vin3 are arranged adjacent to each other on the other side of the input terminal Vin2. Also, the sample hold circuit 12 connected to the input terminal Vin1, etc., and the switches SA11, SA21, etc. disposed in the periphery thereof are all on a semiconductor substrate or a printed wiring board under high-density mounting. They are placed close to each other.

  Therefore, for example, between the wiring pattern from the input terminal Vin2 to the sample hold circuit 14 and the wiring pattern from the input terminal Vin1 to the sample hold circuit 12 disposed adjacent thereto, or from the input terminal Vin2 to the sample hold circuit 14. Between the wiring pattern and the wiring pattern from the input terminal Vin3 disposed adjacent to the wiring pattern to the sample and hold circuit 16, they can be electrically capacitively coupled to each other via a coupling capacitance such as a floating capacitance or a capacitance between lines. Therefore, so-called crosstalk is likely to occur.

  Also in the signal lines SL1 and the like until they are connected to the signal selection circuit 10, for example, when the plurality of signal lines SL1 and the like are configured by multipolar flat cables, multicore PVC cables, or the like. Since the signal lines SL2 and SL1, the signal lines SL2 and SL3, and the like are disposed adjacent to each other, crosstalk may also occur between these via the coupling capacitance.

  Therefore, the signal selection circuit 10 according to the present embodiment adopts the above-described configuration and controls the sample hold circuit 12 and the like, the switches SA11 and the like, and the SA21 and the like as described with reference to FIGS. By using the control circuit 18, it is possible to suppress the occurrence of such crosstalk. 4 to 6, the control lines from the control circuit 18 and the control circuit 18 to the sampling / holding state of the sample hold circuit 12 and the on / off state of the switch SA11 and the like are shown in FIG. Not shown.

  As shown in FIG. 4 to FIG. 6, the signal selection circuit 10 has (1) the pre-sampling state (FIG. 4) and (2) the sampling state (as shown in FIG. 4) as the control states of the sample hold circuit 12 and the switches SA11 and SA21. 5) and (3) hold state (FIG. 6). For this reason, each state is demonstrated in order below.

  As shown in FIG. 4, first, in the state before the electrical signal sampling is performed by the signal selection circuit 10, that is, in the pre-sampling state (standby state), the control circuit 18 sets all the sample hold circuits 12 and the like in the sampling state. (“Samp” shown in FIG. 4), all the switches SA11 and the like and the switch SA21 and the like are controlled to be in an OFF state, and the selection information #N is input from the selection terminal SEL. The selection information #N is input from an external circuit connected to the selection terminal SEL. In this state, for example, # 0 meaning “no selection” is input.

  When selection information #N is input from the selection terminal SEL, the state shifts to a state where an electrical signal is sampled by the signal selection circuit 10, that is, a sampling state. For example, as shown in FIG. 5, when the input terminal Vin2 is selected from the input terminal Vin1 or the like, the control circuit 18 keeps the sample hold circuit 14 connected to the selected input terminal Vin2 in the sampling state. ("Samp" shown in FIG. 5), the sample-and-hold circuit 12 that is arranged adjacent to the input terminal Vin2 and connected to the unselected (unselected) input terminal Vin1 and similarly arranged adjacent to the input terminal Vin2. The sample hold circuit 16 connected to the unselected (unselected) input terminal Vin3 is controlled to be switched from the sampling state to the hold state ("Hold" shown in FIG. 5). Further, the switches SA11 and SA13 that can short-circuit the input and output of the sample and hold circuits 12 and 14 are switched from the off state to the on state.

  As a result, the potential of the signal line SL1 connected to the input terminal Vin1 is maintained at the voltage of the electric signal when the sample hold circuit 12 shifts to the hold state, that is, the bias voltage is applied by the sample hold voltage. The impedance of the line SL1 can be lowered. Similarly, the potential of the signal line SL3 connected to the input terminal Vin3 is also reduced by the impedance of the signal line SL3 because the sample hold circuit 14 shifts to the hold state and a bias voltage is applied by the sample hold voltage. Is possible.

  After such control, as shown in FIG. 6, the control circuit 18 switches the sample hold circuit 12 connected to the selected input terminal Vin2 from the sampling state to the hold state (“Hold” shown in FIG. 6). In addition, the switch SA22 is switched from the off state to the on state. As a result, the sample-and-hold voltage by the sample-and-hold circuit 14, that is, the voltage of the electric signal of the signal line SL2 connected to the input terminal Vin2, is output to the output terminal Vout through the switch SA22, and is thus connected to the output terminal Vout. The A / D converter can obtain an electric signal of the target signal line SL2.

  As described above, in the signal selection circuit 10 according to this embodiment, the potentials of the non-selected signal lines SL1 and SL3 arranged adjacent to the one signal line SL2 to be selected are set to the potentials of the non-selected signal lines SL1 and SL3. Sample hold circuits 12 and 16 are provided that can hold the voltage of the electric signal. During the period in which the electrical signal is output from the selected signal line SL2 to the output terminal Vout, the sample hold circuits 12 and 16 hold the potentials of the non-selected signal lines SL1 and SL3 at the voltage of the electrical signal. For this reason, since an external circuit or the like that sends out such an electrical signal to the signal lines SL1 and SL3 is maintained at the voltage of its own electrical signal, the external circuit is not electrically affected. .

  Further, the signal line SL2 connected to the selected input terminal Vin2 is selected between the selected signal line SL2 and the signal line SL1 due to a decrease in impedance of the signal lines SL1 and SL3 located adjacent to both sides thereof. In addition to suppressing the formation of the coupling capacitance between the signal line SL2 and the signal line SL3, the presence of the signal lines SL1 and SL3 with reduced impedance provides an electrical and electromagnetic shielding effect. Therefore, it is possible to reduce crosstalk without affecting the external circuit that sends electric signals to the signal lines SL1 and SL3 connected to the input terminals Vin1 and Vin3.

  In the embodiment described above, the case where SL2 is selected as one signal line (signal line) to be selected has been described as an example. However, one signal line to be selected is any one of SL1, SL3,. Even in such a case, the same actions and effects as described above can be obtained.

  In this embodiment, the case where there are non-selected signal lines SL1 and SL3 adjacent to both sides of one signal line SL2 (signal line) to be selected has been described as an example, but the present invention is limited to this. However, the present invention can also be applied to the case where there is an unselected signal line adjacent to only one side of one signal line to be selected.

  For example, in FIG. 1, when the signal line SL1 (signal line) is selected, the non-selected signal line adjacent to the signal line SL1 is SL2, and the non-selected signal line exists only on one side of the signal line SL1. In this case, the sample hold circuit 14 connected to the non-selected signal line SL2 is controlled to be in the hold state, the switch SA12 is turned on, and the switch SA22 is turned off, and the non-selected signal line SL2 is set to a low impedance. Thereafter, the sample hold circuit 12 of the selected signal line SL1 is switched from the sampling state to the hold state, and the switch SA21 is controlled to be on.

  Thereby, although it is only on one side of the selected signal line SL1, the impedance of the adjacent signal line SL2 is lowered, so that the formation of the coupling capacitance between the selected signal line SL1 and the signal line SL2 is suppressed, and The presence of the low impedance signal line SL2 provides an electrical and electromagnetic shielding effect. Therefore, crosstalk can be reduced without affecting an external circuit that sends an electric signal to the signal line SL1 connected to the input terminal Vin1.

[Second Embodiment]
Next, the signal selection circuit 30 according to the second embodiment will be described with reference to FIGS.
As shown in FIG. 7, in the signal selection circuit 30 according to the second embodiment, three common lines CL1, CL2, CL3 that can be connected to a plurality of input terminals Vin1, etc. via switches SB11, SB21, SB31, etc. Therefore, the configuration in which the three sample hold circuits 32, 34, and 36 can always be used without providing the sample hold circuit for each input terminal Vin1 or the like is adopted. For example, an A / D converter is connected to the output terminal Vout.

  In the signal selection circuit 10 of the first embodiment described above, for example, the sample hold circuit 12 is required corresponding to the plurality of input terminals Vin1, etc., that is, the sample hold circuit 12 is required for the number of channels. The signal selection circuit 30 according to the third embodiment is different from the first embodiment in that the sample and hold circuit suffices with three sample and hold circuits 32, 34, and 36 regardless of the number of signal lines SL1 and the like to be connected, that is, the number of channels. .

  Specifically, one end side of each of the three switches SB1n, SB2n, SB3n (n is an input terminal number and an integer of 1 or more) is connected to each input terminal Vin1, etc., and the other end of the switch SB1n The other side of the switch SB2n is connected to the common line CL2, and the other end of the switch SB3n is connected to the common line CL3. For example, a switch SB11 is provided between the input terminal Vin1 and the common line CL1, a switch SB21 is provided between the input terminal Vin1 and the common line CL2, and a switch SB31 is provided between the input terminal Vin1 and the common line CL3. Are connected to each other. Similarly, switches SB12, SB22, and SB32 are connected between the input terminal Vin2 and the common lines CL1, CL2, and CL3, and switches between the input terminal Vin3 and the common lines CL1, CL2, and CL3 are connected. SB13, SB23, and SB33 are connected to each other. These switches SB11 and the like are semiconductor switch elements that can be shifted to an on state or an off state by applying a control voltage from the outside, like the switch SA11 or the like of the first embodiment described above.

  The input IN of the sample hold circuit 32 is connected to the common line CL1 to which such switches SB11, SB12, SB13, SB14, SB15,... Are connected. The sample hold circuit 32 has a function to sample and hold an electric signal (mainly an analog signal) input to the input IN, like the sample hold circuit 12 of the signal selection circuit 10 described above. The output OUT is configured to be connectable to its own input IN through the switch SB41.

  Similarly, the input IN of the sample hold circuit 36 is connected to the common line CL3 to which the switches SB31, SB32, SB33, SB34, SB35,... Are connected, and this sample hold circuit 32 is also the above sample hold circuit. Similar to 12 or the like, it has a function of sampling and holding an electric signal (mainly an analog signal) input to the input IN. The output OUT can be connected to its own input IN via the switch SB51.

  On the other hand, to the common line CL2 to which the switches SB21, SB22, SB23, SB24, SB25,... Are connected, the input IN of the sample hold circuit 34 similar to the sample hold circuit 12 is connected. An output terminal Vout is connected to the output OUT of the circuit 34. That is, the sample and hold circuit 34 is an output-only sample and hold circuit to which the input terminal Vin1 selected by the control circuit 38 is connected as will be described later. The output terminal Vout is always connected to the output OUT. ing.

  On the other hand, the sample hold circuits 32 and 36 configured to be connected to the input IN through the switches SB41 and SB51 are adjacent to both sides of the input terminal Vin1 selected by the control circuit 38 as will be described later. In other words, it is a sample-and-hold circuit for shielding, to which a non-selected input terminal Vin1 and the like positioned are connected. The output terminal Vout is not connected to these outputs OUT.

  The control circuit 38 is configured by, for example, a predetermined logic circuit or a microcomputer, like the control circuit 18 of the first embodiment described above, and is described above according to the selection information #N input from the selection terminal SEL. The switches SB1n, SB2n, SB3n, SB41, SB51 can be turned on / off, and the switches SWa1, etc. (see FIG. 2) constituting the sample hold circuits 32, 34, 36 can be turned on / off. For this reason, as with the control circuit 18, control lines are connected between the sample hold circuit 32 and the switch SB11 and the like so that a control voltage can be applied to them (the dashed line, broken line and control shown in FIG. 7). Bus CB).

  The signal selection circuit 30 configured as described above is controlled by the control circuit 38 as shown in FIGS. That is, the signal selection circuit 30 has (1) pre-sampling state (FIG. 8), (2) sampling state 1 (FIG. 9), and (3) sampling state 2 as control states of the sample hold circuit 32 and the switch SB11. There are four states (FIG. 10) and (4) hold state (FIG. 11). For this reason, each state is demonstrated in order below.

  As shown in FIG. 8, first, in the state before the electrical signal is sampled by the signal selection circuit 30, that is, in the pre-sampling state (standby state), the control circuit 38 sets all the sample hold circuits 32, 34, and 36. The sampling state (“Samp” shown in FIG. 8), all the switches SB11 and the like and the switches SB41 and SB51 are controlled to be in the OFF state, respectively, and the selection information #N is input from the selection terminal SEL. The selection information #N is input from an external circuit connected to the selection terminal SEL. In this state, for example, # 0 meaning “no selection” is input.

  When selection information #N is input from the selection terminal SEL, the signal selection circuit 30 shifts to a sampling preparation state in which a sampling path for electrical signals is established. For example, as shown in FIG. 9, when the input terminal Vin3 is selected from the input terminal Vin1 or the like, the control circuit 38 turns on the switch SB23 connected to the selected input terminal Vin3, and this input terminal Vin3. The switch SB12 connected to the common line CL1 with the switch connected to the unselected (unselected) input terminal Vin2 arranged adjacent to the switch SB12 is turned on, and further to the input terminal Vin4 on the other side The switch SB34 connected to the common line CL3 is controlled to be turned on by the connected switch. In this state, each sample hold circuit 32 and the like maintain the sampling state.

  As a result, the selected input terminal Vin3 is connected to the input IN of the sample and hold circuit 34, the unselected input terminals Vin2 on both sides thereof are connected to the input IN of the sample and hold circuit 32, and the unselected input terminal Vin4 is sampled. Since it is connected to the input IN of the hold circuit 36, the electric signal from the signal line SL3 connected to the selected input terminal Vin3 can be sampled by the sample-and-hold circuit 34 dedicated to output, and the non-selected input The signal lines SL2 and SL4 connected to the terminals Vin2 and Vin4 can be shielded by the sample and hold circuits 32 and 36.

  When such a sampling preparation is completed, the process proceeds to the sampling state shown in FIG. That is, the sample and hold circuit 34 connected to the selected input terminal Vin3 samples the electric signal from the signal line SL3, and the sample and hold circuits 32 and 36 connected to the non-selected input terminals Vin2 and Vin4 are sampled. Switching control from the state to the hold state is performed (“Hold” shown in FIG. 10). The sample hold circuit 34 may not be in the sampling state in the previous pre-sampling state or the sampling preparation state as long as the sample hold is possible in this sampling state.

  As a result, the potential of the signal line SL2 connected to the input terminal Vin2 is maintained at the voltage of the electric signal when the sample hold circuit 32 shifts to the hold state, that is, the bias voltage is applied by the sample hold voltage. The impedance of the line SL2 can be lowered. Similarly, the potential of the signal line SL4 connected to the input terminal Vin4 is also reduced by the impedance of the signal line SL4 because the sample hold circuit 36 shifts to the hold state and a bias voltage is applied by the sample hold voltage. Is possible.

  After such control, as shown in FIG. 11, the control circuit 38 switches the sample hold circuit 34 connected to the selected input terminal Vin3 from the sampling state to the hold state (“Hold” shown in FIG. 11). In addition, the switch SB23 is switched from the on state to the off state. As a result, the sample hold voltage by the sample hold circuit 34, that is, the voltage of the electric signal of the signal line SL3 connected to the input terminal Vin3 is output to the output terminal Vout, so that the A / D converter connected to the output terminal Vout Can obtain an electric signal of the target signal line SL3.

  As described above, in the signal selection circuit 30 according to the present embodiment, the potentials of the non-selected signal lines SL2 and SL4 arranged adjacent to the one signal line SL3 to be selected are set to the potentials of the non-selected signal lines SL2 and SL4. Sample hold circuits 32 and 36 that can hold the voltage of the electric signal are provided. During the period in which the electrical signal is output from the selected signal line SL3 to the output terminal Vout, the sample hold circuits 32 and 36 hold the potentials of the non-selected signal lines SL2 and SL4 at the voltage of the electrical signal. For this reason, since an external circuit or the like that sends out such an electric signal to the signal lines SL2 and SL4 is maintained at the voltage of its own electric signal, the external circuit is not electrically affected. .

  Further, the signal line SL3 connected to the selected input terminal Vin3 is selected between the selected signal line SL3 and the signal line SL2 due to a decrease in impedance of the signal lines SL2 and SL4 located adjacent to both sides thereof. In addition to suppressing the formation of the coupling capacitance between the signal line SL3 and the signal line SL4, the presence of the signal lines SL2 and SL4 with reduced impedance provides an electrical and electromagnetic shielding effect. Therefore, it is possible to reduce crosstalk without affecting the external circuit that sends electric signals to the signal lines SL2 and SL4 connected to the input terminals Vin2 and Vin4.

  Further, in the signal selection circuit 30 according to the present embodiment, the required sample and hold circuits are the output dedicated sample and hold circuit 34 and the shielded sample and hold circuit regardless of the number of the signal lines SL1, SL2, SL3,. Therefore, the number of components can be reduced as compared with the signal selection circuit 10 of the first embodiment in which sample hold circuits are provided for the respective input terminals Vin1, Vin2, Vin3,. The scale can be reduced. Therefore, the crosstalk can be reduced without affecting the connected external circuit, and further, the device can be reduced in weight and size and the device cost can be reduced.

  In the embodiment described above, the case where SL3 is selected as one signal line (signal line) to be selected has been described as an example. However, one signal line to be selected is any one of SL1, SL2,. Even in such a case, the same actions and effects as described above can be obtained.

1 is a circuit diagram showing a configuration example of a signal selection circuit according to a first embodiment of the present invention. FIG. 2A is a circuit diagram showing an example of a sample and hold circuit, FIG. 2A is applied to this embodiment, and FIG. 2B is another circuit example. It is a circuit diagram which shows the structural example of a CMOS switch. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 1st Embodiment, and shows the state before sampling. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 1st Embodiment, and shows a sampling state. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 1st Embodiment, and shows a hold state. It is a circuit diagram which shows the structural example of the signal selection circuit which concerns on 2nd Embodiment of this invention. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 2nd Embodiment, and shows the state before sampling. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 2nd Embodiment, and shows a sampling preparation state. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 2nd Embodiment, and shows a sampling state. It is explanatory drawing which shows the operation example of the signal selection circuit which concerns on 2nd Embodiment, and shows a hold state.

Explanation of symbols

10, 30 ... Signal selection circuit 12, 16 ... Sample hold circuit (voltage holding means)
DESCRIPTION OF SYMBOLS 14 ... Sample hold circuit 18, 38 ... Control circuit 32 ... Sample hold circuit (Voltage holding means, 1st sample hold circuit)
34. Sample hold circuit (second sample hold circuit)
36: Sample hold circuit (voltage holding means, third sample hold circuit)
CL1 ... Common line (first common line)
CL2 ... Common line (second common line)
CL3 ... Common line (third common line)
SA11, SA12, SA13 ... switch (first switch)
SA21, SA22, SA23 ... switch (second switch)
SB11, SB12, SB13, SB14, SB15 ... switch (first switch)
SB21, SB22, SB23, SB24, SB25 ... switch (second switch)
SB31, SB32, SB33, SB34, SB35 ... switch (third switch)
SB41 ... switch (4th switch)
SB51 switch (5th switch)
SL0, SL1, SL2, SL3, SL4, SL5 ... signal lines (signal lines)
Vin1, Vin2, Vin3, Vin4, Vin5 ... Input terminal Vout ... Output terminal

Claims (3)

A signal selection circuit that selects one signal line from signal lines connected to a plurality of input terminals and outputs an electrical signal of the selected signal line to an output terminal,
Voltage holding means capable of holding the potential of a non-selected signal line arranged adjacent to one signal line to be selected as a voltage of an electric signal of the non-selected signal line;
The signal selection circuit, wherein the voltage holding unit holds the potential of the non-selected signal line at the voltage of the electric signal during a period in which the electric signal is output from the one signal line to the output terminal. One signal line (for example, SL2) is selected from signal lines (SL1, SL2, SL3) connected to a plurality of input terminals (Vin1, Vin2, Vin3), and an electric signal of the selected signal line (SL2) is selected. A signal selection circuit for outputting to an output terminal (Vout),
A plurality of sample-and-hold circuits (12, 14, 16) having respective inputs connected to the plurality of input terminals (Vin1, Vin2, Vin3);
A plurality of first switches (SA11, SA12, SA13) provided so as to be short-circuited and opened between the individual inputs and outputs of the plurality of sample-and-hold circuits (12, 14, 16);
Each input is connected to each output of the plurality of sample and hold circuits (12, 14, 16), and a plurality of second switches (SA21, SA) connected together to the output terminal (Vout). (SA22, SA23)
Control of sampling / holding of the plurality of sample and hold circuits (12, 14, 16), on / off control of the plurality of first switches (SA11, SA12, SA13) and the plurality of second switches (SA21, SA22, SA23) A control circuit (18) capable of ON / OFF control,
The control circuit (18) includes:
(1) A plurality of first switches (SA11, SA12, SA13) and a plurality of second switches (SA21, SA22, SA23) are all turned off, and the plurality of sample hold circuits (12, 14, 16) are all sampled. From the controlled state,
(2) The sample hold circuit (12, 16) connected to the non-selected signal lines (SL1, SL3) arranged adjacent to the one signal line (SL2) to be selected is in the hold state, and this sample hold circuit ( 12, 16) after controlling the first switch (SA11, SA13) connected to the ON state,
(3) A signal characterized by controlling the sample hold circuit (14) of the first signal line (SL2) to a hold state and turning on the second switch (SA22) of the sample hold circuit (14). Selection circuit. One signal line (for example, SL3) is selected from signal lines (SL1, SL2, SL3, SL4, SL5,...) Connected to a plurality of input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...) A signal selection circuit for outputting an electrical signal of a selected signal line (SL3) to an output terminal (Vout),
A plurality of first switches (SB11, SB12, SB13, SB14, SB15,...) Connected to the respective input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...);
A first common line (CL1) commonly connected to outputs of the plurality of first switches (SB11, SB12, SB13, SB14, SB15,...);
A first sample and hold circuit (32) having an input connected to the first common line (CL1);
A plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) Having respective inputs connected to the plurality of input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...);
A second common line (CL2) commonly connected to outputs of the plurality of second switches (SB21, SB22, SB23, SB24, SB25,...);
A second sample and hold circuit (34) having an input connected to the second common line (CL2) and an output connected to the output terminal (Vout);
A plurality of third switches (SB31, SB32, SB33, SB34, SB35,...) Having respective inputs connected to the plurality of input terminals (Vin1, Vin2, Vin3, Vin4, Vin5,...);
A third common line (CL3) connected in common to the outputs of the plurality of third switches (SB31, SB32, SB33, SB34, SB35,...);
A third sample and hold circuit (36) whose input is connected to the third common line (CL3);
A fourth switch (SB41) provided so that the input and output of the first sample hold circuit (32) can be short-circuited and opened;
A fifth switch (SB51) provided so that the input and output of the third sample and hold circuit (36) can be short-circuited and opened;
The plurality of first switches (SB11, SB12, SB13, SB14, SB15,...), The plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) And the plurality of third switches (SB31, SB32). , SB33, SB34, SB35,...) And the sampling / holding of each of the first sample hold circuit (32), the second sample hold circuit (34), and the third sample hold circuit (36). A control circuit (38) capable of controlling
The control circuit (38) includes:
(1) “Unselected signal line arranged on one side adjacent to one signal line (SL3) to be selected among the plurality of first switches (SB11, SB12, SB13, SB14, SB15,...) The first switch (SB12) connected to (SL2) is turned on, the first switch (SB13) connected to this one signal line (SL3) is turned off, the other side adjacent to this one signal line The first switch (SB14) connected to the non-selected signal line (SL4) arranged in the off state ”,“ among the plurality of second switches (SB21, SB22, SB23, SB24, SB25,...) The second switch (SB22) connected to the non-selected signal line (SL2) arranged on one side adjacent to the one signal line (SL3) to be selected is turned off, and the signal line (SL3) is connected to the first signal line (SL3). The second switch (SB23) to be connected is turned on, and a non-selected signal arranged on the other side adjacent to the one signal line (SL3) The second switch (SB24) connected to (SL4) is turned off "," one signal line (SL3) to be selected from among the plurality of third switches (SB31, SB32, SB33, SB34, SB35, ...) The third switch (SB32) connected to the non-selected signal line (SL2) disposed on one side adjacent to the third switch (SB32) connected to the one signal line (SL3) is turned off. The third switch (SB34) connected to the non-selected signal line (SL4) arranged on the other side adjacent to the one signal line (SL3) "," the fourth switch (SB41) and the fifth switch (SB51) are turned off "," all the first sample hold circuit (32), the second sample hold circuit (34) and the third sample hold circuit (36) are in a sampling state " From the controlled state,
(2) After controlling the first sample hold circuit (32) and the third sample hold circuit (36) to the hold state and the fourth switch (SB41) and the fifth switch (SB51) to the on state,
(3) A signal selection circuit that controls the second sample and hold circuit (34) to a hold state and the second switch (SB23) connected to the first signal line (SL3) to an off state.

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