JP2004214692A - Semiconductor integrated circuit device, d/a conversion device, and a/d conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a capacitive coupling between upper electrode wirings 5A, 5C, and a lower electrode wiring 4 and lower electrodes 2A-2D, without enlarging respective distances between cells 1A-1D, and between the cells 1A-1D and wiring 4, 5A-5D, in a capacity array comprising four unit capacity cells 1A-1D, and to enable enhancing thereby the relative precision of respective cells 1A-1D without causing the raise of a chip cost due to the degradation of relative precision and the increase of an area between the cells 1A-1D. <P>SOLUTION: In the both sides of an upper electrode wiring 5A, a shielding wiring 6 is provided, which suppresses a capacity coupling between the upper electrode wiring 5A and the lower electrode wiring 4, and a capacity coupling between the upper electrode wiring 5A and lower electrodes 2B, 2C, respectively. Moreover, by extending the shielding wiring 6 to surround an upper electrode wiring 5C, a capacity coupling between the upper electrode wiring 5C and the lower electrodes 2A-2D are also suppressed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device (LSI), a D / A converter, and an A / D converter, and more particularly to a measure for increasing the relative accuracy of a plurality of capacitors on an LSI chip.

  In general, when a plurality of capacitance cells are formed on a semiconductor integrated circuit, the relative accuracy of the capacitance cells is equal to the uniformity of an insulating layer between two electrodes constituting each capacitance cell, and the electrodes are connected to another circuit element. It is determined by the uniformity of the parasitic capacitance generated by the wiring. In order to avoid variation due to the element shape, when a capacitance of n times (n is an integer) of the unit capacitance value C is required, it is manufactured by connecting n unit capacitance cells in parallel.

  When a predetermined capacity is obtained by combining the unit capacity cells in the capacity array, the unit capacity cells are dispersed from the capacity array in consideration of the in-plane variation between the unit capacity cells in the capacity array. To be elected. For example, as shown in FIG. 15, in a capacitance array in which four unit capacitance cells 100A to 100D are arranged vertically and horizontally in a 2 × 2 state, the capacitance ratio is C1: C2: C3 = 1: 1: 1. The case where a capacity of 2 is obtained will be described. The capacity C1 and the capacity C2 correspond to the unit capacity cell 100A and the unit capacity cell 100B, respectively, and the capacity C3 corresponds to the two unit capacity cells 100C and 100D.

  At this time, the lower electrode wiring 300 is common to the lower electrodes 200A to 200D of the unit capacitance cells 100A to 100D and is arranged along the periphery of the capacitance array. The upper electrode wiring 500A to the upper electrode 400A is arranged along the lower electrode wiring 300, and the upper electrode wiring 500C of the unit capacitance cell 100D is arranged to pass near the unit capacitance cells 100A to 100D. Therefore, the parasitic capacitances 600, 600,. To avoid this, the interval between the capacity cells 100A to 100D may be made sufficiently wide.

  However, if the distance between the capacitance cells 100A to 100D is widened as described above, the variation in the capacitance array between the capacitance cells 100A to 100D is increased, which leads to deterioration of the relative accuracy between the capacitance cells 100A to 100D. In addition, the area of the entire capacitance array increases, which leads to an increase in chip cost.

  Here, in the case of a 10-bit charge distribution D / A converter having a capacitance array composed of a plurality of unit capacitance cells, how much area of the capacitance array is required will be described. In the following description, four unit capacity cells are arranged in a 2 × 2 state, and each unit capacity cell is provided between a conductive layer (thickness: 1 μm) and a conductive layer dedicated to a capacitor electrode. It has a pair of electrodes formed with an insulating layer (relative permittivity: 4) interposed therebetween, is a square of 14 μm on a side, and has a capacitance density of 1 fF / μm (unit capacitance: 196 fF). The wiring has a wiring width of 0.5 μm and is formed of the conductive layer.

In this case, the parasitic capacitance generated when one wiring is passed at a fixed distance L (unit: μm) between the unit capacitance cells between the unit capacitance cells is roughly calculated in terms of the area capacitance in terms of the opposing area capacitance.
14 × 1 × (1 / L) × 4 × 8.85E-18 = 0.5 fF / L
It is.

  On the other hand, in this case, the relative precision of the capacity of the most significant bit needs to be smaller than 0.05% of the unit capacity (196 fF).

Therefore, in order to reduce the magnitude of the parasitic capacitance to less than 0.05% of the unit capacitance, the distance L between the unit capacitance cell and the wiring must be:
0.5 fF / L <196 fF × 0.0005
By
L> 5.1 μm
And therefore the area of the capacitive array in this case is
(14 × 2 + 5.1 × 2 + 0.5) ² = 38.7 ² = 1497.69
Thus, it can be seen that the area is required to be approximately twice as large as the area (28 × 28 = 784) when four unit capacitance cells are simply arranged in a 2 × 2 state without any gap.

  Further, when two wirings are passed between the unit capacitance cells and the wirings are similarly separated from each other, the spacing between the unit capacitance cells is 16.3 μm. Under this condition, for example, 36 unit capacitances In the case of a capacitor array in which cells are arranged in a 6 × 6 state, the area of the entire capacitor array is approximately four times the area effectively used as a capacitor.

  As described above, in the conventional case, in consideration of the parasitic capacitance due to wiring in order to avoid deterioration of the relative accuracy of each capacitance cell, the distance between the capacitance cells becomes large, and as a result, the capacitance becomes large. Not only is the relative accuracy between cells deteriorated, but also the area is increased and the chip cost is increased.

  The present invention has been made in view of the above points, and a main object thereof is to provide a semiconductor integrated circuit device in which wiring is connected to circuit elements such as a plurality of capacitor cells on a semiconductor substrate. It is possible to reduce each parasitic capacitance between elements, between wirings, and between wirings and elements without increasing the distance between them, thereby deteriorating relative accuracy between elements and increasing chip area due to an increase in area. The object is to increase the relative accuracy of the elements without causing an increase in the element.

  In order to achieve the above object, according to the present invention, a shield wiring is added between the wiring and the element, and the parasitic capacitance is reduced by the shield wiring, so that the relative distance between the elements can be increased without increasing the distance between the elements. Accuracy can be increased.

  Specifically, according to the first aspect of the present invention, a capacitor cell having a first electrode and a second electrode, a first electrode wire connected to a first electrode of the capacitor cell, the first electrode wire and the capacitor And a shield wiring at least a part of which is disposed between the second electrode and the cell.

  According to a second aspect of the present invention, in the first aspect of the present invention, a second electrode wiring connected to a second electrode of the capacitor cell is further provided, and at least a part of the shield wiring is connected to the first electrode wiring. It is also arranged between the second electrode wiring and the second electrode wiring.

  In the invention according to claim 3, a plurality of capacitance cells each having a first electrode and a second electrode, a plurality of first electrode wires connected to the first electrodes of the plurality of capacitance cells, A plurality of second electrode wires connected to the second electrode, at least one first electrode wire of the plurality of first electrode wires, and a capacitor cell other than the capacitor cell connected to the first electrode wire; At least a part of the first electrode wiring is disposed between the first electrode wiring and the second electrode, and another capacitance cell other than the capacitance cell to which the first electrode wiring is connected. And a shield wiring at least a part of which is disposed between the second electrode wiring and the second electrode wiring connected to the second electrode.

  According to this configuration, between the capacitance cells, each first electrode is an individual electrode which is basically supplied with an individual potential for each capacitance cell, and each second electrode is a common potential common to the capacitance cells. Is supplied, the individual electrode wiring (first electrode wiring) of each capacitance cell, the common electrode (second electrode) and the second electrode wiring (common electrode wiring) of each of the other capacitance cells, Is suppressed.

  According to a fourth aspect of the present invention, in the third aspect of the invention, at least a part of the shield wiring is at least one of the plurality of second electrode wirings and at least one of the plurality of capacitance cells. It is also arranged between the first electrodes of one capacitor cell.

  According to this configuration, when the second electrode is basically an individual electrode in addition to the first electrode, the first electrode wiring of the capacitance cell and the second electrode and the second electrode wiring of each of the capacitance cells are connected to each other. In addition to suppressing the capacitive coupling, the capacitive coupling between the second electrode wiring of each capacitance cell and the first electrode of each capacitance cell is also suppressed.

  According to the third and fourth aspects of the present invention, one of the first and second electrodes of the capacitor cell can be formed of a diffusion layer, as in the sixth aspect of the present invention. In the case where the semiconductor device includes the first conductive layer, the second conductive layer provided on the first conductive layer, and the third conductive layer provided on the second conductive layer, As in the invention of Item 7, the first electrode of each capacitor cell is formed by electrically connecting the first conductive layer and the third conductive layer, while the second electrode of each capacitor cell is connected to the second electrode. It can be formed using a conductive layer.

  According to a fifth aspect of the present invention, in the first to fourth aspects, the potential of the shield wiring is set to a fixed potential.

  According to the invention of claim 8, a high-precision charge distribution type D / A converter can be realized by using the capacitance cell according to the invention of claims 1 to 7.

  According to the ninth aspect of the present invention, the charge distribution type D / A converter according to the eighth aspect is provided as a local D / A converter of the charge redistribution type A / D converter, thereby achieving high accuracy. An A / D converter can be realized.

  As described above, according to the first aspect of the present invention, the capacitive coupling between the first electrode wiring connected to the first electrode of the capacitor cell and the second electrode of the capacitor cell can be suppressed by the shield wiring. In addition, without increasing the distance between the first electrode wiring and the second electrode, it is possible to prevent a problem caused by such capacitive coupling from occurring.

  According to the second aspect of the present invention, it is possible to suppress the capacitive coupling between the first electrode wiring and the second electrode wiring of the capacitor cell, thereby preventing the occurrence of a problem due to such capacitive coupling. Can be.

  According to the third to seventh aspects of the present invention, the parasitic capacitance can be reduced without increasing the distance between the capacitance cells, so that the relative cost between the capacitance cells is degraded and the chip cost is increased due to an increase in area. Without inviting, the relative accuracy of the capacitance cell can be improved.

  According to the eighth and ninth aspects of the present invention, a highly accurate charge distribution D / A converter and a charge redistribution A / D converter can be obtained.

  Hereinafter, Embodiments 1 to 7 of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 schematically shows a configuration of a capacitance array according to the first embodiment of the present invention. This capacitance array includes, for example, a charge as a local D / A converter of a charge redistribution A / D converter. Used for distribution type D / A converter.

  In this capacitance array, four unit capacitance cells 1A to 1D are arranged in a 2 × 2 state, and these unit capacitance cells 1A to 1D have a capacitance of C1: C2: C3 = 1: 1: 2. They are combined so as to obtain a specific capacity. The capacity C1 corresponds to the unit capacity cell 1A (lower right in FIG. 1), the capacity C2 corresponds to the unit capacity cell 1B (upper left in the figure), and the capacity C3 corresponds to the unit capacity cell 1C (same as above). The upper right of the figure) and the unit capacity cell 1D (the lower left of the figure) correspond.

  Each of the unit capacitance cells 1A to 1D has a substantially square shape, and has lower electrodes 2A to 2D and upper electrodes 3A to 3D, respectively. The lower electrodes 2A to 2D are connected to a common lower electrode wiring 4 between the unit capacitance cells 1A to 1D. The lower electrode wiring 4 is arranged around the capacitance array so as to extend downward from above in FIG. 1, connect to the lower electrode 2C, and then connect to the remaining lower electrodes 2C, 2A, and 2B in order. ing.

  On the other hand, the upper electrode wiring 5A is connected to the upper electrode 3A of the unit capacitor cell 1A. The upper electrode wiring 5A extends downward from above in FIG. 1 and is disposed on the left side and lower side of the capacitor array in FIG. The upper electrode wiring 5B is connected to the upper electrode 3B of the unit capacitance cell 1B. The upper electrode wiring 5B is arranged so as to extend downward from above in the figure and reach the upper electrode 3B. The upper electrode wiring 5C is connected to the upper electrodes 3C and 3D of the remaining unit capacitance cells 1C and 1D. The upper electrode wiring 5C extends downward from above in the figure and is arranged to pass through the center of the capacitor array.

  In this embodiment, the upper electrode wiring 5A, the lower electrode wiring 4, and the lower sides of the unit capacitance cells 1B and 1D are provided on both sides of the main part of the upper electrode wiring 5A of the unit capacitor cell 1A in the capacitance array region. A shield wiring 6 for suppressing capacitive coupling with the electrodes 2B and 2D is provided. The shield wiring 6 extends so as to surround the main part of the upper electrode wiring 5C of the unit capacitance cells 1C and 1D from both the left and right sides, so that the upper electrode wiring 5C and the unit capacitance cells 1A to 1D are connected. Capacitive coupling with the lower electrodes 2A to 2D of 1D is also suppressed. By providing the shield wiring 6 in this manner, new parasitic capacitances 8, 8,... Are generated between the shield wiring 6 and the upper electrode wirings 5A, 5C. , 8,... Do not significantly affect the relative accuracy between the unit capacitance cells 1A to 1D.

  Therefore, according to this embodiment, it is possible to suppress the capacitive coupling between the upper electrode wiring 5A, the lower electrode wiring 4, and the lower electrodes 2B and 2D without increasing the distance between the unit capacitance cells 1A to 1D. In addition to this, the capacitive coupling between the upper electrode wiring 5C and the lower electrodes 2A to 2D can be suppressed, so that the relative accuracy between the unit capacitor cells 1A to 1D deteriorates and the chip cost increases due to an increase in area. Without inviting, the relative accuracy of the unit capacity cells 1A to 1D can be improved.

(Embodiment 2)
4 and 5 schematically show a configuration of a capacitance cell according to Embodiment 2 of the present invention.

  In this embodiment, on a substrate (not shown), a first conductive layer 11, a second conductive layer 12 located on the upper side of the first conductive layer 11, and a second conductive layer 12 And the third conductive layer 13 is provided. The capacitor cell 1 has the lower electrode 2 formed by the first conductive layer 11 and the second electrode so as to face the lower electrode 2 via the insulating layer 14. And the upper electrode 3 formed by the conductive layer 12. A lower electrode wiring 4 is connected to the lower electrode 2, and the lower electrode wiring 4 is formed by the first conductive layer 11. On the other hand, the upper electrode wiring 5 is connected to the upper electrode 3, and the upper electrode wiring 5 is formed of the third conductive layer 13 and is connected to the upper electrode 3 via the conductor 7. .

  In this embodiment, the shield wiring 6 formed by the first and second conductive layers 11 and 12 is arranged around the main part of the upper electrode wiring 5. At this time, the portion of the shield wiring 6 formed by the first conductive layer 11 and the portion formed by the second conductive layer 12 are electrically connected to each other via the conductor 7.

  Therefore, according to this embodiment, the same effect as that of the first embodiment can be obtained.

  In the above embodiment, the shield wiring 6 is formed by the first and second conductive layers 11 and 12, but may be formed by only the second conductive layer 12.

(Embodiment 3)
2 and 3 schematically show a configuration of a capacitance cell according to Embodiment 3 of the present invention. The same parts as those in the second embodiment are denoted by the same reference numerals.

  In this embodiment, similarly to the case of the second embodiment, the capacitor cell 1 is formed so as to face the lower electrode 2 formed by the first conductive layer 11 and the lower electrode 2 via the insulating layer 14. The lower electrode 2 is connected to the lower electrode wiring 4 formed by the first conductive layer 11. An upper electrode wiring 5 is connected to the upper electrode 3, and a connection portion of the upper electrode wiring 5 with the upper electrode 3 is formed by the third conductive layer 13. The difference from the second embodiment is that the main part of the upper electrode wiring 5 is formed of the first conductive layer 11 instead of the third conductive layer 13. The main part and the connection part of the upper electrode wiring 5 are electrically connected via the conductor 7.

  In the present embodiment, the main part of the upper electrode wiring 5 is surrounded by the shield wiring 6 formed by the first conductive layer 11, so that the main part of the upper electrode wiring 5 and the lower electrode Capacitive coupling between the wiring 4 and the upper and lower electrodes 2 and 3 is suppressed.

  Therefore, according to this embodiment, the same effect as that of the second embodiment can be obtained.

(Embodiment 4)
FIG. 6 schematically shows a configuration of a unit capacitor cell according to Embodiment 4 of the present invention.

  In this embodiment, the unit capacitance is constituted by the capacitance between the diffusion layer 2 and the polysilicon layer 3. The unit capacitance includes the polysilicon layer 3 and each part of the wiring which affect the capacitance accuracy of the unit capacitance. A cell 1 is formed.

  Specifically, the diffusion layer 2 has a substantially rectangular shape. Diffusion layer electrode wiring 4 for diffusion layer 2 includes first portions 4a, 4a,... Arranged so as to extend in a vertical direction and a horizontal direction between adjacent unit capacitance cells 1 and 1, respectively, and corresponding unit capacitance cells. The four second portions 4b, 4b,... Extending from the four first portions 4a, 4a,. It comprises a rectangular frame-shaped third portion 4c arranged. The first portions 4a, 4a,... Of the diffusion layer electrode wiring 4 are formed by a first conductive layer, and the second portions 4b, 4b,. The first portion 4a and the second portion 4b are connected via a second conductive layer. The third portion 4c is formed of the first conductive layer, and is connected to each of the second portions 4b via the second conductive layer.

  On the other hand, the polysilicon layer 3 is disposed on the inner peripheral side of the third portion 4c of the diffusion layer electrode wiring 4 and has a substantially rectangular first portion 3a overlapping the central portion of the diffusion layer 2; ., Each extending radially from the center of each side of the diffusion layer 2, and disposed on the outer peripheral side of the diffusion layer 2 so as to surround the diffusion layer 2. The third portion 3c has a substantially rectangular frame shape and forms a peripheral edge. The polysilicon layer electrode wiring 5 for the polysilicon layer 3 includes a first portion 5a disposed so as to overlap the first portion 4a in the vertical direction of the diffusion layer electrode wiring 4, and a polysilicon layer 3 from the first portion 5a. And the second portion 5b, 5b extending in the lateral direction toward the two corners of the third portion 3c, and the substantially rectangular frame-shaped third portion 3c arranged to overlap the third portion 3c of the polysilicon layer 3. And three parts 5c. The first to third portions 5a to 5c of the polysilicon layer electrode wiring 5 are all formed of a third conductive layer, and the third portion 5c is formed of the polysilicon layer 3 via the first and second conductive layers. It is connected to the third part 3c. The layers adjacent in the thickness direction are electrically insulated by an insulating layer (not shown). The white squares shown in FIG. 6 indicate conductors interposed between the corresponding layers.

  In this embodiment, the shield wiring 6 for suppressing the capacitive coupling between the diffusion layer electrode wiring 4 and the polysilicon layer electrode wiring 5 and the polysilicon layer 3 is provided, and the shield wiring 6 is fixed to the ground potential. It is supposed to be.

  Specifically, the shield wiring 6 includes a first portion 6a interposed between a first portion 4a of the diffusion layer electrode wiring 4 in the vertical direction and a first portion 5a of the polysilicon layer electrode wiring 5, and a diffusion layer electrode A second part 6b interposed between the second part 4b of the wiring 4 and the third part 5c of the polysilicon layer electrode wiring 5, a first part 4a of the diffusion layer electrode wiring 4 and a third part of the polysilicon layer electrode wiring 5; And a third portion 6c interposed between the third portion 5c and the third portion 3c of the polysilicon layer 3. The first and second portions 6a and 6b of the shield wiring 6 are formed by a second conductive layer, and the third portion 6c is formed by first to third conductive layers. The first to third conductive layers are electrically connected to each other.

  Here, for comparison, FIG. 7 shows a conventional case in which the parasitic capacitance coupling is suppressed without providing a shield wiring. In this figure, although the conductive layers forming the respective portions of the diffusion layer electrode wiring 4 and the polysilicon layer electrode wiring 5 are slightly different from those in the embodiment, their arrangement is substantially the same as in the embodiment. As is clear from the comparison between FIG. 6 and FIG. 7, it is understood that the distance between each first portion 4 a of the diffusion layer electrode wiring 4 and the unit capacitor cell 1 can be reduced by providing the shield wiring 6.

  Therefore, according to this embodiment, the unit capacitor cell 1 includes the region of the third portion 3c of the polysilicon layer 3 and the region of the third portion 5c of the polysilicon layer electrode wiring 5, which are regions that affect the relative accuracy of capacitance. Since the shield wiring 6 is formed between the diffusion layer electrode wiring 4 and the polysilicon layer electrode wiring 5 outside the region, the relative accuracy between the unit capacitor cells 1 and 1 is deteriorated and the area is increased. Therefore, the relative accuracy of each capacitance cell 1 can be improved.

(Embodiment 5)
FIG. 8 schematically shows a configuration of a capacitance array according to the fifth embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals.

  This capacitance array includes four unit capacitance cells 1A to 1D arranged in a 2 × 2 state.

  Each of the unit capacitance cells 1A to 1D has a substantially rectangular shape, and has lower electrodes 2A to 2D and upper electrodes 3A to 3D. The lower electrodes 2A to 2D are formed by a first conductive layer, and the upper electrodes 3A to 3D are formed by a second conductive layer on the first conductive layer.

  The lower electrodes 2A to 2D of the unit capacitance cells 1A to 1D are connected to a lower electrode wiring 4 common to the unit capacitance cells 1A to 1D. The lower electrode wiring 4 is formed by a third conductive layer on the second conductive layer.

  On the other hand, the upper electrode wiring 5A is connected to the upper electrode 3A of the unit capacitance cell 1A (lower right of FIG. 8). This upper electrode wiring 5A is formed of the second conductive layer. The upper electrode wiring 5B is connected to the upper electrode 3B of the unit capacity cell 1B (upper right in the figure). This upper electrode wiring 5B is also formed of the second conductive layer, as in the case of the upper electrode wiring 5A.

  In this embodiment, the lower electrodes 2B to 2D, the upper electrodes 3B to 3D, and the lower electrodes 5A and the unit capacitance cells 1B to 1D other than the unit capacitance cell 1A connected to the upper electrode wiring 5A. A shield wiring 6 for suppressing capacitive coupling with the electrode wiring 4 is provided. The shield wiring 6 is formed by portions of the first and second conductive layers other than the portions forming the lower electrodes 2A to 2D and the upper electrodes 3A to 3D of the unit capacitance cells 1A to 1D.

  Here, for comparison, FIG. 9 shows a case without the shield wiring. In this case, as illustrated in FIG. 10B, the parasitic capacitance 8 generated between the upper electrode wiring 5A of the unit capacitor cell 1A and the lower electrode 2B of the unit capacitor cell 1B causes the unit capacitor cell The capacity of 1A is increased by ΔC (C + ΔC), and the ratio accuracy of the charge storage capacity is lost. On the other hand, in the case of the embodiment, as shown in FIG. 10A, the capacitance of the unit capacitor cell 1A does not change, so that the relative accuracy is maintained.

  Therefore, according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 6)
FIG. 11 schematically shows a configuration of a unit capacitance cell according to Embodiment 6 of the present invention.

  In this unit capacitor cell, the polysilicon layer, the first conductive layer on the polysilicon layer, the second conductive layer on the first conductive layer, and the third conductive layer on the second conductive layer One electrode is formed. The first electrode 2 is constituted by the electrode of the polysilicon layer and the electrode of the second conductive layer, and the second electrode 3 is constituted by the electrode of the first conductive layer and the electrode of the third conductive layer. I have.

  The first electrode wiring 4 for the first electrode 2 includes first portions 4 a, 4 a,... Arranged so as to extend in a vertical direction between adjacent unit capacitance cells 1, 1, and four corners of the first electrode 2. And four second portions 4b, 4b,. These first and second portions 4a and 4b are both formed of a third conductive layer.

  On the other hand, the second electrode wiring 5 for the second electrode 3 includes first portions 5a, 5a,... Arranged so as to extend in a horizontal direction and a vertical direction between adjacent unit capacitance cells 1 and 1, and a corresponding unit capacitance. Are formed from four first parts 5a, 5a,... Adjacent to the cell 1 toward the center of each side of the second electrode 3, respectively. Each first portion 5a is formed by a first conductive layer. Each of the second portions 5b is formed of a first conductive layer on the side of the first portion 5a, and is formed of a third conductive layer on the side of the second electrode 3; They are connected to each other through layers.

  In this embodiment, the capacitive coupling between the first and second parts 4a and 4b of the first electrode wiring 4 and the first part 5a of the second electrode wiring 5 is suppressed, and each first electrode of the second electrode wiring 5 is formed. A shield wiring 6 for suppressing capacitive coupling between the portion 5a and the second electrode 3 is provided.

  Specifically, the shield wiring 6 includes a first portion 6 a disposed between the first portion 4 a of the first electrode wiring 4 in the vertical direction and the first portion 5 a of the second electrode wiring 5, and a first electrode 6. Each of the four first portions 4a, 4a,... Of the wiring 4 and a second portion 6b having a rectangular frame shape disposed between the first electrodes 2. The first portion 6a of the shield wiring 6 is formed by a second conductive layer, and the second portion 6b is formed by first to third conductive layers.

  Here, for comparison, FIG. 12 shows a conventional case in which parasitic capacitance coupling is suppressed without providing a shield wiring. In the figure, the conductive layers forming the respective portions of the first electrode wiring 4 and the second electrode wiring 5 are slightly different from those of the embodiment, but the arrangement is almost the same as that of the embodiment. As is clear from the comparison between FIG. 11 and FIG. 12, according to this embodiment, by providing the shield wiring 6, the distance between each first portion 5 a of the second electrode wiring 5 and the unit capacitor cell 1 is increased. It can be seen that the distance can be reduced.

(Embodiment 7)
FIG. 13 shows a configuration of a 10-bit charge redistribution A / D converter according to Embodiment 7 of the present invention. A charge distribution D / A converter using the capacitance array 20 according to the fourth embodiment (see FIG. 6) is incorporated.

  The capacitance array 20 has a capacitance having a capacitance ratio of 16: 8: 4: 2: 1: 1: 1: 1: 1: 1, and the D / A converter 10 is provided for each capacitance. And a switch group 30 including switches. Then, the switch of the capacitance corresponding to the most significant bit is switched to the Vrefh side, and the switches of the other capacitances are switched to the Vrefl side, and the comparator 40 compares the magnitude of the input analog signal Vin with the capacitance of the most significant bit. Then, based on the output of the comparator 40, when the capacity of the most significant bit is larger, the sequential conversion logic circuit 50 fixes the switch to the Vrefh side and determines the bit value to “1”, while the most significant bit is Is smaller than the reference value, the switch is switched to the Vrefl side to set the bit value to "0". Such an operation is sequentially performed for each capacitor for each clock to determine each bit, whereby the analog signal Vin is converted into a digital signal and output.

  Here, an experiment on the integration ratio linearity performed on the present A / D converter as an example of the invention will be described. For comparison, the integration ratio linearity of an A / D converter as a conventional example in which a D / A converter using a capacitance array without shield wiring (FIG. 7) is incorporated was also examined. . The results are also shown in FIG.

  As can be seen from FIG. 14, in the case of the conventional example, an error of about ± 1.7 LSB occurs, whereas in the invention example, the error is suppressed to ± 0.2 LSB or less.

  Therefore, according to this embodiment, in the charge redistribution A / D converter in which the charge distribution D / A converter 10 is incorporated as a local D / A converter, the charge distribution D / A converter 10 is used. In addition, since the capacitance array 20 according to the fourth embodiment is used, the relative accuracy of each unit capacitance cell in the capacitance array 20 can be improved without increasing the area of the capacitance array 20, and the charge distribution D / This can contribute to improving the accuracy of the A converter 10 and the charge redistribution A / D converter.

  In the above embodiment, the case where the fourth embodiment is applied to the capacitance array 10 of the charge distribution type D / A converter 10 is described. However, the first to third embodiments and the fifth and sixth embodiments are applied. You can also.

FIG. 2 is a plan view schematically showing a configuration of the capacitance array according to the first embodiment of the present invention. FIG. 9 is a plan view schematically showing a configuration of a unit capacitor cell according to Embodiment 3 of the present invention. FIG. 3 is a sectional view taken along line III-III of FIG. 2. FIG. 9 is a plan view schematically showing a configuration of a unit capacitor cell according to Embodiment 2 of the present invention. FIG. 5 is a sectional view taken along line VV of FIG. 4. FIG. 14 is a plan view schematically showing a configuration of a unit capacitor cell according to Embodiment 4 of the present invention. FIG. 7 is a diagram corresponding to FIG. 6, schematically illustrating a configuration of a unit capacitance cell without a shield wiring. FIG. 13 is a plan view schematically showing a configuration of a capacitance array according to Embodiment 5 of the present invention. FIG. 9 is a diagram corresponding to FIG. 8, schematically illustrating a configuration of a capacitance array without a shield wiring. FIG. 3 is a circuit diagram showing a comparison of a state of occurrence of a parasitic capacitance in a case where there is a shield wiring (a) and in a case where there is no shield wiring (b). FIG. 15 is a plan view illustrating a configuration of a unit capacitor cell according to Embodiment 6 of the present invention. FIG. 12 is an enlarged view of the configuration of a unit capacitor cell without a shield wiring, which corresponds to FIG. 11. FIG. 13 is a circuit diagram showing a configuration of a 10-bit charge redistribution A / D converter according to Embodiment 7 of the present invention. FIG. 9 is a characteristic diagram additionally showing each integration ratio linearity of the invention example and the conventional example in the 10-bit charge redistribution A / D converter. FIG. 2 is a diagram corresponding to FIG. 1 schematically illustrating a configuration of a conventional capacitance array.

Explanation of reference numerals

1,1A-1D unit capacity cell (capacitance cell, circuit element)
2, 2A-2D Lower electrode, diffusion layer, first electrode 3, 3A-3D Upper electrode, polysilicon layer, second electrode 4, 4A-4C Lower electrode wiring, diffusion layer electrode wiring, first electrode wiring 5 , 5A to 5C Upper electrode wiring, polysilicon layer electrode wiring, second electrode wiring 6 Shield wiring 10 Charge distribution type D / A converter 11 First conductive layer 12 Second conductive layer 13 Third conductive layer

Claims (9)

A capacitance cell having a first electrode and a second electrode;
A first electrode wiring connected to a first electrode of the capacitance cell;
A semiconductor integrated circuit device, comprising: a shield wiring at least a part of which is disposed between the first electrode wiring and the second electrode of the capacitance cell. The semiconductor integrated circuit device according to claim 1,
A second electrode wiring connected to a second electrode of the capacitor cell;
The semiconductor integrated circuit device, wherein at least a part of the shield wiring is disposed between the first electrode wiring and the second electrode wiring. A plurality of capacitance cells each having a first electrode and a second electrode;
A plurality of first electrode wires connected to first electrodes of the plurality of capacitance cells;
A plurality of second electrode wires connected to second electrodes of the plurality of capacitance cells;
At least a portion thereof is arranged between at least one first electrode wiring of the plurality of first electrode wirings and a second electrode of another capacitance cell other than the capacitance cell to which the first electrode wiring is connected; And at least one first electrode wiring of the plurality of first electrode wirings and the second electrode wiring connected to a second electrode of a capacitor cell other than the capacitor cell to which the first electrode wiring is connected. A semiconductor integrated circuit device, comprising: a shield wiring in which at least a part thereof is disposed. The semiconductor integrated circuit device according to claim 3,
At least a part of the shield wiring is also arranged between at least one second electrode wiring of the plurality of second electrode wirings and a first electrode of at least one capacitance cell of the plurality of capacitance cells. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1, wherein
A semiconductor integrated circuit device, wherein a potential of a shield wiring is set to a fixed potential. 5. The semiconductor integrated circuit device according to claim 3, wherein
A semiconductor integrated circuit device, wherein one of the first and second electrodes of each capacitance cell is formed by a diffusion layer. 5. The semiconductor integrated circuit device according to claim 3, wherein
A first conductive layer, a second conductive layer provided on the first conductive layer, and a third conductive layer provided on the second conductive layer,
The first electrode of each capacitor cell is formed by electrically connecting the first conductive layer and the third conductive layer,
A semiconductor integrated circuit device, wherein a second electrode of each of the capacitance cells is formed by the second conductive layer. A charge distribution type D / A converter, comprising the semiconductor integrated circuit device according to claim 1. A charge redistribution type A / D converter, comprising the charge distribution type D / A converter according to claim 8 as a local D / A converter.

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