JP2007142297A - Method of manufacturing package component - Google Patents

Method of manufacturing package component Download PDF

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Publication number
JP2007142297A
JP2007142297A JP2005336562A JP2005336562A JP2007142297A JP 2007142297 A JP2007142297 A JP 2007142297A JP 2005336562 A JP2005336562 A JP 2005336562A JP 2005336562 A JP2005336562 A JP 2005336562A JP 2007142297 A JP2007142297 A JP 2007142297A
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substrate
sealing
resin
sealing resin
electronic component
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JP4823656B2 (en
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Kiyoshi Arita
潔 有田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing package components which forms sealing resin only in a sealing target range with proper adhesion. <P>SOLUTION: The package component manufacturing method covers an electronic component 2, mounted on a substrate 1 with a sealing resin 18 to form a package component. After mounting electronic components 2, 3 on the substrate 1, the surface of the substrate 1 is reformed by a plasma process, to improve the wettability of the surface. An atmospheric pressure plasma unit 12 sprays an atmospheric pressure plasma jet 14a by using fluorine gas on a liquid repelling region set at the marginal edge of a sealing range with the sealing resin 18 on the reformed surface of the substrate 1, thereby causing the surface wettability of the liquid-repelling region to decrease. This prevents the seal resin 18 from expanding its wet zone from the sealing target range of the sealing resin 18, thus forming the sealing resin 18 only in the sealing target range with proper adhesion. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、基板に実装された電子部品を封止樹脂によって覆うことにより形成されたパッケージ部品を製造するパッケージ部品の製造方法に関するものである。   The present invention relates to a package component manufacturing method for manufacturing a package component formed by covering an electronic component mounted on a substrate with a sealing resin.

電子機器には、基板に実装された半導体素子などの電子部品を樹脂封止した構造のパッケージ部品が用いられる。このようなパッケージ部品の製造過程においては、基板に電子部品を実装した後の樹脂封止に先立って基板表面を改質することを目的としたプラズマ処理が行われる（例えば特許文献１，２参照）。このプラズマ処理は、基板表面にアルゴンガスや酸素ガスのプラズマを照射することにより行われ、これにより基板表面の濡れ性が向上し、封止樹脂との密着性が改善されるという効果を得る。
２００１−１２７０８５号公報 ２００２−８３８２９号公報 For electronic equipment, package parts having a structure in which electronic parts such as semiconductor elements mounted on a substrate are sealed with resin are used. In the manufacturing process of such a package component, plasma processing is performed for the purpose of modifying the substrate surface prior to resin sealing after mounting the electronic component on the substrate (see, for example, Patent Documents 1 and 2). ). This plasma treatment is performed by irradiating the substrate surface with plasma of argon gas or oxygen gas, thereby improving the wettability of the substrate surface and improving the adhesion with the sealing resin.
No. 2001-127085 No. 2002-83829

パッケージ部品においては一般に複数の電子部品が近接して配置され、これらの電子部品のうち、ワイヤボンディング後の半導体素子やバンプ接合されたフリップチップなど特定の電子部品のみが樹脂封止の対象となる。このため樹脂封止に際しては、対象となる電子部品のみを覆って樹脂を塗布する必要がある。ところが前述のように表面改質のためのプラズマ処理を行うと基板表面の濡れ性が向上するため、基板表面に塗布された樹脂が基板表面に沿って外側に濡れ拡がり易くなり、濡れ拡がった樹脂が隣接の電子部品と接触する不具合が生じる場合がある。   In package parts, a plurality of electronic parts are generally arranged close to each other, and among these electronic parts, only specific electronic parts such as semiconductor elements after wire bonding and flip-chips with bump bonding are subjected to resin sealing. . For this reason, at the time of resin sealing, it is necessary to cover only the target electronic component and apply the resin. However, since the wettability of the substrate surface is improved when the plasma treatment for surface modification is performed as described above, the resin applied to the substrate surface easily spreads outward along the substrate surface, and the wet spread resin May come into contact with adjacent electronic components.

このような不具合を防止するため上述の特許文献例においては、表面改質のためのプラズマ処理に際し、処理範囲を封止対象の電子部品のエリアに限定するためのマスキングを施す方法を用いていた。このため、基板種類毎に専用のマスクを準備してプラズマ処理時に各基板に装着する必要があり、表面改質のためのプラズマ処理に多大な手間とコストを要していた。このように従来方法においては、封止対象範囲のみに封止樹脂を良好な密着性で形成することが困難であるという問題があった。   In order to prevent such inconvenience, in the above-mentioned patent document example, a masking method for limiting the processing range to the area of the electronic component to be sealed was used in the plasma processing for surface modification. . For this reason, it is necessary to prepare a dedicated mask for each substrate type and attach it to each substrate at the time of plasma processing, which requires a great deal of labor and cost for plasma processing for surface modification. As described above, the conventional method has a problem that it is difficult to form the sealing resin with good adhesion only in the range to be sealed.

そこで本発明は、封止対象範囲のみに封止樹脂を良好な密着性で形成することができるパッケージ部品の製造方法を提供することを目的とする。   Then, an object of this invention is to provide the manufacturing method of the package components which can form sealing resin with favorable adhesiveness only in the sealing object range.

本発明のパッケージ部品の製造方法は、基板に実装された電子部品を封止樹脂で覆って形成されたパッケージ部品を製造するパッケージ部品の製造方法であって、前記基板に前記電子部品を実装する部品実装工程と、前記電子部品が実装された前記基板の表面を、減圧雰囲気下において酸素ガスもしくはアルゴンガスを用いたプラズマ処理によって改質して、前記表面の濡れ性を向上させる表面改質工程と、前記表面改質後の前記基板の表面において前記封止樹脂による封止範囲の外縁部に設定された撥液領域にフッ素系ガスを用いた大気圧プラズマを吹き付けることにより、前記撥液領域の表面の濡れ性を低下させる大気圧プラズマ処理工程と、前記大気圧プラズマ処理後の前記封止範囲に封止樹脂を塗布する樹脂塗布工程と、塗布された前記封止樹脂を硬化させる樹脂硬化工程とを含む。   A method for manufacturing a package component according to the present invention is a method for manufacturing a package component that is formed by covering an electronic component mounted on a substrate with a sealing resin, and the electronic component is mounted on the substrate. A component mounting step and a surface modification step for improving the wettability of the surface by modifying the surface of the substrate on which the electronic component is mounted by plasma treatment using oxygen gas or argon gas in a reduced pressure atmosphere And spraying atmospheric pressure plasma using a fluorine-based gas on the liquid repellent area set at the outer edge of the sealing range by the sealing resin on the surface of the substrate after the surface modification, An atmospheric pressure plasma treatment step for reducing the surface wettability, a resin application step for applying a sealing resin to the sealing range after the atmospheric pressure plasma treatment, and And a resin curing step of curing the Kifutome resin.

本発明によれば、基板の表面の濡れ性を改善するための表面改質後に、封止樹脂による
封止範囲の外縁部にフッ素系ガスを用いた大気圧プラズマを吹き付けて表面の濡れ性を低下させることにより、封止対象範囲のみに封止樹脂を良好な密着性で形成することができる。 According to the present invention, after surface modification for improving the surface wettability of the substrate, atmospheric pressure plasma using a fluorine-based gas is sprayed on the outer edge of the sealing range by the sealing resin to improve the surface wettability. By lowering, the sealing resin can be formed with good adhesion only in the sealing target range.

次に本発明の実施の形態を図面を参照して説明する。図１、図２、図３は本発明の一実施の形態のパッケージ部品の製造方法の工程説明図、図４は本発明の一実施の形態のパッケージ部品の製造方法において用いられる大気圧プラズマ発生装置の部分断面図、図５は本発明の一実施の形態のパッケージ部品の製造方法の工程説明図である。   Next, embodiments of the present invention will be described with reference to the drawings. 1, 2, and 3 are process explanatory views of a method for manufacturing a package component according to an embodiment of the present invention, and FIG. 4 is an atmospheric pressure plasma generator used in the method for manufacturing a package component according to an embodiment of the present invention FIG. 5 is a process cross-sectional view of a method for manufacturing a package component according to an embodiment of the present invention.

図１、図２、図３を参照して、パッケージ部品の製造方法について説明する。このパッケージ部品は、基板に実装された電子部品を封止樹脂で覆って形成されるものである。図１（ａ）に示すように、基板１には、電子部品２、電子部品３が実装される（部品実装工程）。電子部品２は上面に回路形成面２ａが形成された半導体チップであり、電子部品３は両端に半田接合用の接続用端子３ａが設けられた抵抗やコンデンサなどの矩形チップ部品である。   With reference to FIGS. 1, 2, and 3, a method for manufacturing a package component will be described. This package component is formed by covering an electronic component mounted on a substrate with a sealing resin. As shown in FIG. 1A, the electronic component 2 and the electronic component 3 are mounted on the substrate 1 (component mounting process). The electronic component 2 is a semiconductor chip having a circuit forming surface 2a formed on the upper surface, and the electronic component 3 is a rectangular chip component such as a resistor or a capacitor provided with connection terminals 3a for solder bonding at both ends.

図１（ｂ）に示すように、電子部品２は基板１に接着剤４によって接着された後、回路形成面２ａの電極と基板１上の電極１ａとをワイヤ５によって接続するワイヤボンディングの対象となる。また電子部品３は接続用端子３ａを基板１上に設けられた電極１ｂに半田フィレット６によって半田接合することにより実装される（図３（ａ）参照）。ここで、基板１において電子部品２と電子部品３とは近接して実装されており、電極１ａと電極１ｂとは挟間隔で配置されている。   As shown in FIG. 1B, after the electronic component 2 is bonded to the substrate 1 with an adhesive 4, the wire bonding target connects the electrode on the circuit forming surface 2a and the electrode 1a on the substrate 1 with a wire 5. It becomes. The electronic component 3 is mounted by soldering the connection terminal 3a to the electrode 1b provided on the substrate 1 with a solder fillet 6 (see FIG. 3A). Here, the electronic component 2 and the electronic component 3 are mounted close to each other on the substrate 1, and the electrode 1 a and the electrode 1 b are arranged with a gap therebetween.

次に部品実装後の基板１は、図１（ｃ）に示すプラズマ処理装置７に送られる。プラズマ処理装置７は真空密の真空チャンバ８によって形成された処理室８ａの内部に放電電極９を配置した構成となっており、プラズマ処理対象の基板１は放電電極９上に載置される。プラズマ処理に際しては、処理室８ａ内を真空排気して減圧し、次いで処理室８ａ内に酸素ガスやアルゴンガスなどのプラズマ発生用ガスを供給しながら、高周波電源１０によって放電電極９に高周波電圧を印加する。   Next, the substrate 1 after component mounting is sent to the plasma processing apparatus 7 shown in FIG. The plasma processing apparatus 7 has a configuration in which a discharge electrode 9 is disposed inside a processing chamber 8 a formed by a vacuum-tight vacuum chamber 8, and the substrate 1 to be plasma processed is placed on the discharge electrode 9. In plasma processing, the processing chamber 8a is evacuated and depressurized, and then a high-frequency voltage is applied to the discharge electrode 9 by the high-frequency power source 10 while supplying a plasma generating gas such as oxygen gas or argon gas into the processing chamber 8a. Apply.

これにより処理室８ａ内には、酸素ガスやアルゴンガスのプラズマ（斜線部１１参照）が発生し、これにより基板１の上面のプラズマ処理が行われる。このプラズマ処理により、基板１の表面が改質され、表面の濡れ性が向上する。すなわちここでは、電子部品が実装された前記基板の表面を、減圧雰囲気下において酸素ガスもしくはアルゴンガスを用いたプラズマ処理によって改質して、表面の濡れ性を向上させる（表面改質工程）。   As a result, plasma of oxygen gas or argon gas (see the hatched portion 11) is generated in the processing chamber 8a, whereby plasma processing of the upper surface of the substrate 1 is performed. By this plasma treatment, the surface of the substrate 1 is modified and the wettability of the surface is improved. That is, here, the surface of the substrate on which electronic components are mounted is modified by plasma treatment using oxygen gas or argon gas in a reduced-pressure atmosphere to improve surface wettability (surface modification step).

ここで基板１の表面改質について説明する。基板１の樹脂表面層を構成するポリイミドなどの樹脂は各種の有機結合によって構成されており、樹脂表面層には炭素単結合基（Ｃ−Ｃ）やカルボニル基（Ｃ＝Ｏ）など、炭素と酸素、水素等を含む原子同士が固有の形態で結合した有機結合が多数存在する。有機結合はそれぞれ固有の結合エネルギを有しており、この結合エネルギ値より大きなエネルギが外部から与えられることによって、これらの有機結合は分解する。   Here, the surface modification of the substrate 1 will be described. Resins such as polyimide constituting the resin surface layer of the substrate 1 are composed of various organic bonds, and the resin surface layer includes carbon and carbon such as carbon single bond groups (C—C) and carbonyl groups (C═O). There are many organic bonds in which atoms including oxygen, hydrogen, etc. are bonded in a unique form. Each organic bond has a specific binding energy, and these organic bonds are decomposed when energy larger than the binding energy value is given from the outside.

基板１の表面改質を目的としたプラズマ処理においては、樹脂表面層に存在する複数種類の有機結合のうち、カルボニル基など親水性の有機結合基を残して、他の結合基を選択的に除去することが可能なプラズマ処理条件が設定される。すなわち、プラズマによって発生する荷電粒子のエネルギを制御することにより、結合エネルギの大きいカルボニル基などの有機結合基を残して、結合エネルギの低い炭素単結合基等を選択的に除去することが可能なエネルギ域の荷電粒子を衝突させるようにする。これにより、基板１の樹脂表面
層ではカルボニル基など親水性の有機結合基の割合が増加し、濡れ性が大幅に向上する。水接触角測定による濡れ性評価の結果によれば、プラズマ処理前の基板表面での水接触角が約７０°であったものが、プラズマ処理後の基板表面で水接触角は約１０°まで低下している。 In the plasma treatment for the purpose of surface modification of the substrate 1, among the plurality of types of organic bonds existing in the resin surface layer, other organic bonding groups are selectively left, leaving a hydrophilic organic bonding group such as a carbonyl group Plasma treatment conditions that can be removed are set. That is, by controlling the energy of the charged particles generated by the plasma, it is possible to selectively remove carbon single bond groups and the like having low bond energy while leaving organic bond groups such as carbonyl groups having high bond energy. Make charged particles in the energy range collide. Thereby, in the resin surface layer of the board | substrate 1, the ratio of hydrophilic organic coupling groups, such as a carbonyl group, increases, and wettability improves significantly. According to the results of wettability evaluation by water contact angle measurement, the water contact angle on the substrate surface before plasma treatment was about 70 °, but the water contact angle on the substrate surface after plasma treatment was up to about 10 °. It is falling.

次に表面改質後の基板１は、大気圧プラズマ処理工程に送られる。ここでは、図２（ａ）に示すように、大気圧プラズマ処理装置１２を用いた撥液領域形成が行われる。ここで図４を参照して大気圧プラズマ処理装置１２の構造を説明する。大気圧プラズマ処理装置１２は、大気圧下で発生したプラズマを噴射するプラズマノズル１３を備えている。プラズマノズル１３には、ガス供給装置（図示省略）によってフッ素系ガスを成分とするプラズマ発生用ガス１４が供給される。プラズマ発生用ガス１４は、プラズマノズル１３内部を通過する過程で高周波電源部１５による電界中でプラズマ化し、フッ素ラジカルを含む大気圧プラズマジェット１４ａとなってノズル孔１３ａから下方へ噴射される。プラズマノズル１３は、多関節ロボットやＸＹＺテーブル機構などの移動機構３０に装着されている。移動機構３０は、封止樹脂による封止範囲の外縁部の位置を示す座標データを記憶部３１より読み取って、プラズマノズル１３をこの外縁部となる位置に沿って移動させる。   Next, the substrate 1 after the surface modification is sent to an atmospheric pressure plasma treatment process. Here, as shown in FIG. 2A, the liquid-repellent region is formed using the atmospheric pressure plasma processing apparatus 12. Here, the structure of the atmospheric pressure plasma processing apparatus 12 will be described with reference to FIG. The atmospheric pressure plasma processing apparatus 12 includes a plasma nozzle 13 that ejects plasma generated under atmospheric pressure. The plasma nozzle 13 is supplied with a plasma generating gas 14 containing a fluorine-based gas as a component by a gas supply device (not shown). The plasma generating gas 14 is converted into plasma in the electric field generated by the high-frequency power source 15 in the process of passing through the inside of the plasma nozzle 13, and becomes an atmospheric pressure plasma jet 14a containing fluorine radicals and injected downward from the nozzle hole 13a. The plasma nozzle 13 is attached to a moving mechanism 30 such as an articulated robot or an XYZ table mechanism. The moving mechanism 30 reads coordinate data indicating the position of the outer edge portion of the sealing range by the sealing resin from the storage unit 31, and moves the plasma nozzle 13 along the position serving as the outer edge portion.

大気圧プラズマ処理においては、プラズマノズル１３から大気圧プラズマジェット１４ａを基板１の表面に対して噴射しながら、プラズマノズル１３を電子部品２の周囲で、所定の軌跡で移動させながら周回させる。これにより、図３（ｂ）に示すように、電子部品２の周囲には、基板１の表面がフッ素系ガスの大気圧プラズマによって処理された幅約０．１ｍｍの線状の処理領域、すなわち一旦表面改質されて濡れ性が向上した樹脂表面層に、フッ素ラジカルが作用することによって濡れ性が低下した撥液領域１６が、閉形状で形成される。ここで、電子部品２と電子部品３とは近接して実装されているため、図３（ｂ）に示すように、撥液領域１６は屈曲軌跡で電極１ａと電極１ｂとの挟間隔の中間を通過している。   In the atmospheric pressure plasma treatment, the atmospheric pressure plasma jet 14a is jetted from the plasma nozzle 13 onto the surface of the substrate 1, and the plasma nozzle 13 is rotated around the electronic component 2 while moving along a predetermined locus. As a result, as shown in FIG. 3B, around the electronic component 2, a linear processing region having a width of about 0.1 mm in which the surface of the substrate 1 is processed by the atmospheric pressure plasma of the fluorine-based gas, that is, The liquid-repellent region 16 whose wettability has been lowered by the action of fluorine radicals is formed in a closed shape on the resin surface layer once surface-modified and wettability improved. Here, since the electronic component 2 and the electronic component 3 are mounted close to each other, as shown in FIG. 3 (b), the liquid repellent region 16 is in the middle of the interval between the electrode 1a and the electrode 1b with a bending locus. Is going through.

この撥液領域１６においては、大気圧プラズマジェット１４ａ中のフッ素ラジカルが、基板１の表面樹脂層のカルボニル基などの親水基と結合している。これにより、撥液領域１６では図１（ｃ）に示す表面改質によって一旦向上した濡れ性が大幅に低下し、表面改質工程によって約１０°程度にまで低下した水接触角は、上述の大気圧プラズマ処理により、８０°〜８５°程度まで増大する。すなわちここでは、表面改質後の基板１の表面において、封止樹脂による封止範囲の外縁部に設定された撥液領域１６に、フッ素系ガスを用いた大気圧プラズマを吹き付けることにより、前記撥液領域の表面の濡れ性を低下させる（大気圧プラズマ処理工程）。   In the liquid repellent region 16, fluorine radicals in the atmospheric pressure plasma jet 14 a are bonded to a hydrophilic group such as a carbonyl group of the surface resin layer of the substrate 1. Thereby, in the liquid repellent region 16, the wettability once improved by the surface modification shown in FIG. 1 (c) is greatly reduced, and the water contact angle reduced to about 10 ° by the surface modification process is as described above. It increases to about 80 ° to 85 ° by the atmospheric pressure plasma treatment. That is, here, by spraying atmospheric pressure plasma using a fluorine-based gas on the liquid-repellent region 16 set at the outer edge of the sealing range by the sealing resin on the surface of the substrate 1 after the surface modification, The wettability of the surface of the liquid repellent region is reduced (atmospheric pressure plasma treatment step).

次に、大気圧プラズマ処理工程後の基板１の表面の封止範囲に封止樹脂を塗布する（樹脂塗布工程）。すなわち図２（ｂ）に示すように、塗布ノズル１７から熱硬化性の封止樹脂１８を吐出させることにより、電子部品２を対象に設定された封止範囲を封止樹脂１８によって覆う。この樹脂塗布において、封止樹脂１８は基板１の表面で塗布点から外側に向かって流動するが、前述のように封止範囲の外縁部には濡れ性が低下した撥液領域１６が形成されていることから、図３（ｃ）に示すように、封止樹脂１８は撥液領域１６を越えて外側に流動することなく、所定の封止範囲のみを覆う。これにより、電子部品２に近接して電子部品３が実装されて、電極１ａと電極１ｂとが近接して配置されている場合にあっても、封止樹脂１８が電子部品３の領域まで拡がることによる不具合が発生しない。   Next, sealing resin is apply | coated to the sealing range of the surface of the board | substrate 1 after an atmospheric pressure plasma processing process (resin application process). That is, as shown in FIG. 2B, the sealing range set for the electronic component 2 is covered with the sealing resin 18 by discharging the thermosetting sealing resin 18 from the application nozzle 17. In this resin application, the sealing resin 18 flows outward from the application point on the surface of the substrate 1, but as described above, the liquid repellent region 16 having reduced wettability is formed at the outer edge of the sealing range. Therefore, as shown in FIG. 3C, the sealing resin 18 covers only a predetermined sealing range without flowing outward beyond the liquid repellent region 16. Thereby, even when the electronic component 3 is mounted in the vicinity of the electronic component 2 and the electrode 1a and the electrode 1b are disposed in close proximity, the sealing resin 18 extends to the region of the electronic component 3. There will be no malfunctions.

この後、封止樹脂１８が塗布された基板１はキュア炉に送られ、ここで基板１を所定温度で加熱することにより、封止樹脂１８を硬化させる（樹脂硬化工程）。これにより、図２（ｃ）に示すように、基板１に、電子部品２、電子部品３を実装し、電子部品２を封止樹脂１８で覆ったパッケージ部品の製造が完了する。   Thereafter, the substrate 1 coated with the sealing resin 18 is sent to a curing furnace, where the sealing resin 18 is cured by heating the substrate 1 at a predetermined temperature (resin curing step). As a result, as shown in FIG. 2C, the electronic component 2 and the electronic component 3 are mounted on the substrate 1, and the manufacture of the package component in which the electronic component 2 is covered with the sealing resin 18 is completed.

上記説明したように、本発明のパッケージ部品の製造方法においては、基板の表面の濡れ性を改善するための表面改質後に、封止樹脂による封止範囲の外縁部にフッ素系ガスを用いた大気圧プラズマを吹き付けて表面の濡れ性を低下させるようにしている。これにより、基板種類毎に専用のマスクを準備してプラズマ処理時に各基板に装着する手間とコストを要することなく、封止対象範囲のみに封止樹脂を良好な密着性で形成することができる。   As described above, in the method for manufacturing a package component according to the present invention, after the surface modification for improving the wettability of the surface of the substrate, a fluorine-based gas is used at the outer edge of the sealing range by the sealing resin. Atmospheric pressure plasma is sprayed to reduce surface wettability. This makes it possible to form a sealing resin with good adhesion only in a sealing target range without preparing a dedicated mask for each type of substrate and attaching it to each substrate during plasma processing. .

なお、実装対象の電子部品が、図５（ａ）、（ｂ）に示す電子部品２２のように、下面に半田バンプ２２ａが設けられたバンプ付き部品であるような場合には、電子部品２２と基板１Ａとの間は狭隙間となり、プラズマ処理による表面改質効果が及びにくい。このような場合には、図１（ｃ）に示すプラズマ処理において、酸素ガスをプラズマ発生用ガスとして用いる。   When the electronic component to be mounted is a bumped component having solder bumps 22a on the lower surface, such as the electronic component 22 shown in FIGS. 5A and 5B, the electronic component 22 A narrow gap is formed between the substrate and the substrate 1A, and the surface modification effect by the plasma treatment is difficult to reach. In such a case, oxygen gas is used as a plasma generating gas in the plasma treatment shown in FIG.

これにより、図５（ｃ）に示すように、プラズマ放電によって発生した酸素ラジカルＯ＊が電子部品２２と基板１Ａとの間の隙間に侵入し、酸素ラジカルＯ＊の化学作用によって隙間内が表面改質される。すなわち、プラズマによって発生したイオンなどの物理作用が及びにくい狭隘箇所を処理対象とするような場合においても、酸素ガスをプラズマ発生用ガスとして用いることにより、良好な表面改質効果を得ることができる。 As a result, as shown in FIG. 5C, oxygen radicals O * generated by plasma discharge enter the gap between the electronic component 22 and the substrate 1A, and the inside of the gap is surfaced by the chemical action of the oxygen radical O *. Reformed. That is, even when a narrow part where physical action such as ions generated by plasma is difficult to be processed is used as a processing target, a favorable surface modification effect can be obtained by using oxygen gas as a plasma generating gas. .

本発明のパッケージ基板の製造方法は、封止樹脂を封止対象範囲のみに良好な密着性で形成することができるという効果を有し、基板に実装された電子部品を封止樹脂で覆って形成されたパッケージ部品の製造において有用である。   The method for manufacturing a package substrate of the present invention has an effect that the sealing resin can be formed with good adhesion only in the sealing target range, and the electronic component mounted on the substrate is covered with the sealing resin. Useful in the manufacture of formed package parts.

本発明の一実施の形態のパッケージ部品の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the package components of one embodiment of this invention 本発明の一実施の形態のパッケージ部品の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the package components of one embodiment of this invention 本発明の一実施の形態のパッケージ部品の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the package components of one embodiment of this invention 本発明の一実施の形態のパッケージ部品の製造方法において用いられる大気圧プラズマ発生装置の部分断面図The fragmentary sectional view of the atmospheric pressure plasma generator used in the manufacturing method of the package component of one embodiment of the present invention 本発明の一実施の形態のパッケージ部品の製造方法の工程説明図Process explanatory drawing of the manufacturing method of the package components of one embodiment of this invention

符号の説明Explanation of symbols

１ 基板
２ 電子部品
３ 電子部品
７ プラズマ処理装置
１２ 大気圧プラズマ処理装置
１４ａ 大気圧プラズマジェット
１６ 撥液領域
１８ 封止樹脂 DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Electronic component 3 Electronic component 7 Plasma processing apparatus 12 Atmospheric pressure plasma processing apparatus 14a Atmospheric pressure plasma jet 16 Liquid repellent area 18 Sealing resin

Claims (1)

基板に実装された電子部品を封止樹脂で覆って形成されたパッケージ部品を製造するパッケージ部品の製造方法であって、
前記基板に前記電子部品を実装する部品実装工程と、
前記電子部品が実装された前記基板の表面を、減圧雰囲気下において酸素ガスもしくはアルゴンガスを用いたプラズマ処理によって改質して、前記表面の濡れ性を向上させる表面改質工程と、
前記表面改質後の前記基板の表面において前記封止樹脂による封止範囲の外縁部に設定された撥液領域にフッ素系ガスを用いた大気圧プラズマを吹き付けることにより、前記撥液領域の表面の濡れ性を低下させる大気圧プラズマ処理工程と、
前記大気圧プラズマ処理後の前記封止範囲に封止樹脂を塗布する樹脂塗布工程と、
塗布された前記封止樹脂を硬化させる樹脂硬化工程とを含むことを特徴とするパッケージ部品の製造方法。
A package component manufacturing method for manufacturing a package component formed by covering an electronic component mounted on a substrate with a sealing resin,
A component mounting step of mounting the electronic component on the substrate;
A surface modification step for improving the wettability of the surface by modifying the surface of the substrate on which the electronic component is mounted by a plasma treatment using oxygen gas or argon gas in a reduced pressure atmosphere;
By spraying atmospheric pressure plasma using a fluorine-based gas to the liquid repellent region set at the outer edge of the sealing range by the sealing resin on the surface of the substrate after the surface modification, the surface of the liquid repellent region Atmospheric pressure plasma treatment process to reduce the wettability of
A resin application step of applying a sealing resin to the sealing range after the atmospheric pressure plasma treatment;
And a resin curing step of curing the applied sealing resin.
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JP2012231030A (en) * 2011-04-26 2012-11-22 Apic Yamada Corp Degate method, degate device, transfer molding device, and semiconductor package manufacturing method
JP2013098566A (en) * 2011-10-31 2013-05-20 Nordson Corp Methods of fabricating electronics assemblies
JP2017022421A (en) * 2011-10-31 2017-01-26 ノードソン コーポレーションＮｏｒｄｓｏｎ Ｃｏｒｐｏｒａｔｉｏｎ Methods of fabricating electronics assemblies
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