CN113161246B - Technological method for filling chip edge area with underfill - Google Patents
Technological method for filling chip edge area with underfill Download PDFInfo
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- CN113161246B CN113161246B CN202110437178.2A CN202110437178A CN113161246B CN 113161246 B CN113161246 B CN 113161246B CN 202110437178 A CN202110437178 A CN 202110437178A CN 113161246 B CN113161246 B CN 113161246B
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- chip
- substrate
- underfill
- edge
- edge area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Abstract
The invention provides a process method for filling an edge area of a chip with underfill, which comprises the following steps: step S1, providing a substrate, and modifying the surface of the substrate to be attached with a chip to form non-infiltration of underfill colloid; s2, mounting a chip on the surface of the substrate through a surface mounting process; and soldered by reflow soldering; during reflow soldering, soldering columns are distributed around the chip between the chip and the substrate; s3, modifying the edge area of the substrate at the edge of the chip to infiltrate the underfill; and S4, setting underfill in the edge area of the substrate at the edge of the chip, heating and reflowing to enable the edge of the chip and the edge area of the substrate to be filled with the underfill, and then curing to obtain the final module. The invention can avoid the chip surface area which is not required to be covered when the underfill filling process is carried out.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a process method for filling an edge area of a chip with underfill.
Background
The bottom mounting technology of the chip is a main mode of interconnection between the chip and the terminal at present, and in order to prevent the solder balls from being broken due to larger stress difference between the chip and the substrate, underfill filling treatment is often needed between the chip and the substrate.
However, the surface of the radio frequency chip often has an air bridge or a transmitting device, and if the surface is covered by underfill, the transmitting and receiving capability of the radio frequency product is seriously affected. Therefore, for the radio frequency module, different bottom glue filling areas need to be defined according to the positions of the air bridge or the emitting device, so that the glue can strictly avoid the sensitive positions and can adhere between chips to finish the bottom filling effect.
Disclosure of Invention
The invention aims to provide a process method for filling an edge area of a chip with underfill, which can avoid an area of the surface of the chip which is not required to be covered when the underfill filling process is carried out; in order to achieve the technical purpose, the invention adopts the following technical scheme:
the embodiment of the invention provides a process method for filling an edge area of a chip with underfill, which comprises the following steps:
step S1, providing a substrate, and modifying the surface of the substrate to be attached with a chip to form non-infiltration of underfill colloid;
s2, mounting a chip on the surface of the substrate through a surface mounting process; and soldered by reflow soldering; during reflow soldering, soldering columns are distributed around the chip between the chip and the substrate;
s3, modifying the edge area of the substrate at the edge of the chip to infiltrate the underfill;
and S4, setting underfill in the edge area of the substrate at the edge of the chip, heating and reflowing to enable the edge of the chip and the edge area of the substrate to be filled with the underfill, and then curing to obtain the final module.
Further, in step S1, the surface of the substrate to which the chip is to be mounted is specifically modified by a plasma cleaning or spraying of a thin film.
Further, in step S3, another plasma is used to clean or etch the surface of the substrate on which the chip is mounted, or a film is sprayed to infiltrate the underfill, so as to change the surface properties of the edge region of the substrate on the edge of the chip and infiltrate the underfill.
Or in the step S3, removing the film sprayed in the step S1 on the substrate edge area of the chip edge, so as to modify the substrate edge area of the chip edge to be infiltrated with the underfill colloid.
Further, in step S3, the jig is used to block the edge of the chip, and an opening non-wetting to the underfill is left at the edge of one side or both sides of the chip.
The invention has the advantages that: the surface properties of the middle area of the substrate surface under the chip are different from those of the edge area through modification treatment, and the middle area of the substrate surface under the chip which does not need to be underfilled is modified to be non-infiltrated with colloid, so that when the underfilling operation is carried out by the underfilling glue, the underfilling glue only underfilling is carried out on the edge area of the substrate which can be infiltrated by the underfilling glue, and the area which cannot be infiltrated is avoided; meanwhile, the welding columns are reasonably arranged, so that the colloid adsorption or blocking effect of local areas is difficult to realize, and the assistance is provided for realizing regional distribution of underfill.
Drawings
FIG. 1 is a schematic diagram of a first modification of a substrate surface in an embodiment of the invention.
Fig. 2 is a schematic diagram of a solder die attached to a surface of a substrate in an embodiment of the invention.
FIG. 3 is a schematic diagram of a second modification of the edge region of the substrate surface according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of the non-wetting openings for the colloid left in the second modification in the embodiment of the present invention.
Fig. 5 is a schematic diagram of a module after the underfill is filled in the chip edge according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, repeated reference numerals or designations may be used in the various embodiments. These repetition are for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Reference numerals referring to steps in the various embodiments of the invention are merely for convenience of description and do not substantially follow a sequential order. Different steps in each specific embodiment can be combined in different sequences, so that the aim of the invention is fulfilled.
The embodiment of the invention provides a process method for filling an edge area of a chip with underfill, which comprises the following steps:
step S1, providing a substrate 1, and modifying the surface of the substrate 1 to be attached with a chip to be non-infiltrated with underfill colloid;
specifically, as shown in fig. 1, a substrate 1 is provided, and then a film 2 is cleaned or sprayed on the surface of the substrate 1 to be mounted with chips by plasma, so that the surface of the substrate 1 is modified to be non-wetting to underfill;
step S2, mounting the chip 3 on the surface of the substrate 1 through a surface mounting process; and soldered by reflow soldering; during reflow soldering, soldering columns 4 are distributed around the chip between the chip 3 and the substrate 1;
specifically, as shown in fig. 2, the soldering flux is sprayed first, then the chip 3 is attached to the surface of the substrate 1 by a surface mount technology, and during the reflow soldering, a solder post 4 is formed between the chip 3 and the substrate 1 around the periphery of the chip; these solder columns 4 can subsequently block underfill at the chip edge from entering the chip bottom area; then removing the soldering flux;
step S3, modifying the edge area 101 of the substrate 1 at the edge of the chip 3 to infiltrate the underfill;
specifically, as shown in fig. 3, another plasma cleaning or etching may be performed on the surface of the substrate 1 on which the chip 3 is mounted, or a film that wets the underfill may be sprayed, so as to change the surface property of the edge area 101 of the substrate 1 on the edge of the chip 3 and wet the underfill; since the chip 3 is covered on the substrate 1, the middle area of the bottom surface of the chip 3 and the surface of the substrate 1 below the chip 3 (the corresponding substrate area in the middle of the chip) are not affected during the second modification;
or, removing the film 2 sprayed in step S1 from the edge area 101 of the substrate 1 at the edge of the chip 3;
further, the jig can be used to block the edge of the chip 3, and an opening 102 which is non-infiltrated to the underfill colloid is reserved at one side or two side edges of the chip 3; as shown in fig. 4; the air channel on the side surface of the bottom of the chip 3 can be reserved when the underfill process is carried out subsequently;
and S4, setting underfill 5 in the edge area 101 of the substrate 1 at the edge of the chip 3, heating and reflowing to enable the underfill 5 to be distributed on the edge of the chip 3 and the edge area 101 of the substrate 1, and then solidifying to obtain a final module.
Specifically, as shown in fig. 5, since the surface of the substrate 1 under the chip 3 is not modified at the time of the second modification, the underfill 5 does not enter the bottom area of the chip 3 because the underfill is kept non-wet and the solder columns 4 around the periphery of the chip 3 are blocked, as can be seen from fig. 5.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (5)
1. The process method for filling the edge area of the chip with the underfill is characterized by comprising the following steps of:
step S1, providing a substrate (1), and modifying the surface of the substrate (1) to be attached with a chip to be non-infiltrated with underfill colloid;
s2, attaching a chip (3) on the surface of the substrate (1) through a surface attaching process; and soldered by reflow soldering; during reflow soldering, soldering columns (4) are distributed around the chip between the chip (3) and the substrate (1);
s3, modifying an edge area (101) of a substrate (1) at the edge of a chip (3) to infiltrate the underfill colloid;
and S4, setting underfill (5) in the edge area (101) of the substrate (1) at the edge of the chip (3), heating and reflowing to enable the underfill (5) to be fully distributed on the edge of the chip (3) and the edge area (101) of the substrate (1), and then solidifying to obtain the final module.
2. The process for underfill to fill the edge area of a chip of claim 1,
in step S1, the surface of the substrate (1) to be mounted with chips is modified by plasma cleaning or spraying of the film (2) on the surface of the substrate (1).
3. The process for underfill to fill the edge area of a chip as recited in claim 2, wherein,
in step S3, another plasma is used to clean or etch the surface of the substrate (1) on which the chip (3) is mounted, or a film that wets the underfill is sprayed, so that the surface property of the edge area (101) of the substrate (1) at the edge of the chip (3) is changed, and the underfill is infiltrated.
4. The process for underfill to fill the edge area of a chip as recited in claim 2, wherein,
in the step S3, the film (2) sprayed in the step S1 is removed from the edge area (101) of the substrate (1) at the edge of the chip (3), so that the edge area (101) of the substrate (1) at the edge of the chip (3) is modified to be infiltrated with underfill colloid.
5. A process for filling the edge region of a chip with underfill according to claim 2 or 3,
in step S3, the jig is used to block the edge of the chip (3), and an opening (102) which is non-wetting to the underfill colloid is reserved at the edge of one side or two sides of the chip (3).
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Citations (7)
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US5800747A (en) * | 1996-07-02 | 1998-09-01 | Motorola, Inc. | Method for molding using an ion implanted mold |
JP2007142297A (en) * | 2005-11-22 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Method of manufacturing package component |
JP2010192525A (en) * | 2009-02-16 | 2010-09-02 | Namics Corp | Semiconductor device and method of manufacturing the same |
CN103594385A (en) * | 2012-08-15 | 2014-02-19 | 台湾积体电路制造股份有限公司 | Method to control underfill fillet width |
JP2014107306A (en) * | 2012-11-22 | 2014-06-09 | Shinko Electric Ind Co Ltd | Wiring board |
CN107026122A (en) * | 2015-09-18 | 2017-08-08 | 株式会社迪思科 | The processing method of chip |
CN111508903A (en) * | 2019-01-30 | 2020-08-07 | 相互股份有限公司 | Packaging substrate structure of electronic device and manufacturing method thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7045904B2 (en) * | 2003-12-10 | 2006-05-16 | Texas Instruments Incorporated | Patterned plasma treatment to improve distribution of underfill material |
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- 2021-04-22 CN CN202110437178.2A patent/CN113161246B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5800747A (en) * | 1996-07-02 | 1998-09-01 | Motorola, Inc. | Method for molding using an ion implanted mold |
JP2007142297A (en) * | 2005-11-22 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Method of manufacturing package component |
JP2010192525A (en) * | 2009-02-16 | 2010-09-02 | Namics Corp | Semiconductor device and method of manufacturing the same |
CN103594385A (en) * | 2012-08-15 | 2014-02-19 | 台湾积体电路制造股份有限公司 | Method to control underfill fillet width |
JP2014107306A (en) * | 2012-11-22 | 2014-06-09 | Shinko Electric Ind Co Ltd | Wiring board |
CN107026122A (en) * | 2015-09-18 | 2017-08-08 | 株式会社迪思科 | The processing method of chip |
CN111508903A (en) * | 2019-01-30 | 2020-08-07 | 相互股份有限公司 | Packaging substrate structure of electronic device and manufacturing method thereof |
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