JP2002118128A - Electronic component and manufacturing method thereof - Google Patents
Electronic component and manufacturing method thereofInfo
- Publication number
- JP2002118128A JP2002118128A JP2001216365A JP2001216365A JP2002118128A JP 2002118128 A JP2002118128 A JP 2002118128A JP 2001216365 A JP2001216365 A JP 2001216365A JP 2001216365 A JP2001216365 A JP 2001216365A JP 2002118128 A JP2002118128 A JP 2002118128A
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- JP
- Japan
- Prior art keywords
- substrate
- plasma processing
- electronic component
- plasma
- adhesion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/85009—Pre-treatment of the connector or the bonding area
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- H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
- H01L2224/85013—Plasma cleaning
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- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品製造方法
および電子部品に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component manufacturing method and an electronic component.
【０００２】[0002]
【従来の技術】電子部品の種類としてＢＧＡ（Ｂａｌｌ
Ｇｒｉｄ Ａｒｒａｙ）パッケージなどのように半導
体素子を基板上に搭載し、半導体素子を基板に形成され
た銅電極にワイヤボンディングによって電気的に接続す
る構造のものが知られている。ところでこの銅電極の表
面は、ワイヤボンディングに用いられる金ワイヤとの接
合性を確保するため基板の製造過程において金メッキさ
れる。この金メッキに先立ち、金メッキ後に銅が金メッ
キ層内へ拡散するのを防ぐ目的で、銅電極上にニッケル
を含むバリアメタル層が形成される。2. Description of the Related Art BGA (Ball) is a type of electronic component.
2. Description of the Related Art A structure in which a semiconductor element is mounted on a substrate, such as a Grid Array package, and the semiconductor element is electrically connected to a copper electrode formed on the substrate by wire bonding is known. By the way, the surface of the copper electrode is plated with gold in the process of manufacturing the substrate in order to secure the bonding property with the gold wire used for wire bonding. Prior to the gold plating, a barrier metal layer containing nickel is formed on the copper electrode for the purpose of preventing copper from diffusing into the gold plating layer after the gold plating.
【０００３】そして半導体素子を基板に搭載した後に
は、半導体素子を基板に接着する熱硬化性接着剤を硬化
させるため熱処理が行われる。このとき、メッキ工程で
金メッキ層中に混入したニッケルが金メッキ層の表面で
空気に触れることにより酸化膜などのニッケル化合物が
生成される。ところが、このニッケル化合物はワイヤボ
ンディング時に金ワイヤと金メッキ層の表面との接合を
阻害する。[0003] After the semiconductor element is mounted on the substrate, a heat treatment is performed to cure a thermosetting adhesive for bonding the semiconductor element to the substrate. At this time, nickel mixed in the gold plating layer in the plating step comes into contact with air on the surface of the gold plating layer, thereby generating a nickel compound such as an oxide film. However, this nickel compound hinders the bonding between the gold wire and the surface of the gold plating layer during wire bonding.
【０００４】そこでワイヤボンディングに先立って、こ
の接合阻害物を除去してワイヤボンディング時の接合性
を向上させる目的で基板の上面をプラズマ処理すること
が行われる。このプラズマ処理は、減圧雰囲気中でプラ
ズマを発生させ、アルゴンなどのイオンを電子部品の上
面に衝突させることにより、スパッタリング効果で金メ
ッキ層表面の接合阻害物を除去するものである。このと
き、接合阻害物を十分に除去するためには、金メッキ層
の表面を５０〜１００オングストローム程度の厚さで除
去することが必要とされる。Therefore, prior to the wire bonding, the upper surface of the substrate is subjected to plasma treatment for the purpose of removing the bonding obstacle and improving the bonding property at the time of the wire bonding. In this plasma treatment, a plasma is generated in a reduced-pressure atmosphere, and ions such as argon collide with the upper surface of the electronic component, thereby removing a bonding inhibitor on the surface of the gold plating layer by a sputtering effect. At this time, it is necessary to remove the surface of the gold plating layer with a thickness of about 50 to 100 angstroms in order to sufficiently remove the bonding inhibitor.
【０００５】[0005]
【発明が解決しようとする課題】ところで、ワイヤボン
ディング後の電子部品は樹脂封止工程に送られ、エポキ
シ樹脂などの樹脂によって封止され樹脂モールドが形成
される。この樹脂モールドは半導体素子やボンディング
ワイヤを樹脂で完全に包み込むことにより、外力による
ダメージや異物の侵入から電子部品を保護するためのも
のであり、封止に用いられる樹脂と基板との密着性が良
好であることが求められる。By the way, the electronic component after the wire bonding is sent to a resin sealing step, where it is sealed with a resin such as an epoxy resin to form a resin mold. This resin mold completely protects semiconductor elements and bonding wires with resin to protect electronic components from damage due to external force and penetration of foreign substances. It is required to be good.
【０００６】ところが、基板のレジストの材質によって
は封止樹脂との密着性が必ずしも良好でなく、封止後に
レジストと封止樹脂の接着面から剥離を生じる場合があ
る。このレジストと封止樹脂の密着性を阻害する要因と
して、前述のプラズマ処理の条件が関係していると推測
される。以下、封止樹脂と基板の密着性とプラズマ処理
条件との相関関係を見いだすために行った実験について
説明する。However, depending on the material of the resist on the substrate, the adhesiveness with the sealing resin is not always good, and peeling may occur from the bonding surface between the resist and the sealing resin after sealing. It is presumed that the above-described conditions of the plasma processing are related to the factor that hinders the adhesion between the resist and the sealing resin. Hereinafter, an experiment performed to find a correlation between the adhesion between the sealing resin and the substrate and the plasma processing conditions will be described.
【０００７】図１０（ａ）、（ｂ）は実験対象基板のレ
ジスト表面と封止樹脂の密着性を示すグラフ、図１１
（ａ）は実験対象基板の平断面図、図１１（ｂ）は同側
断面図である。図１０は、プラズマ発生用ガスとしてア
ルゴンガスを用いた場合の、基板のレジストと封止樹脂
の密着性と、プラズマ処理時間および高周波電源出力と
の関係を示したものである。図１０（ａ）、および
（ｂ）は、それぞれ高周波電源出力が５０Ｗ、および５
００Ｗの場合の、密着性（縦軸）とプラズマ処理時間
（横軸）をグラフに示している。FIGS. 10A and 10B are graphs showing the adhesion between the resist surface of the test object substrate and the sealing resin, and FIGS.
FIG. 11A is a plan sectional view of the test target substrate, and FIG. 11B is a side sectional view of the same. FIG. 10 shows the relationship between the adhesion between the resist on the substrate and the sealing resin, the plasma processing time, and the output of the high-frequency power supply when an argon gas is used as the plasma generating gas. FIGS. 10A and 10B show that the high-frequency power output is 50 W and 5 W, respectively.
In the case of 00 W, the graph shows the adhesion (vertical axis) and the plasma processing time (horizontal axis).
【０００８】ここで、図１１（ａ）、（ｂ）を参照して
この実験で採用されている封止樹脂の密着性の評価方法
について説明する。図１１（ａ）の電子部品の平面図に
おいて、基板１の表面にはリード状の電極２が形成され
ている。図１１（ｂ）の断面図に示すように基板１の表
面は電極２の表面も含めてレジスト３によって被覆され
ている。このレジスト３上に封止樹脂の樹脂モールド４
が形成される。この樹脂モールド４に外力が加えられた
場合には、樹脂モールド４は基板１の表面から剥離する
が、このとき樹脂モールド４とレジスト３の密着度によ
って、剥離の態様が異なる。Here, a method for evaluating the adhesion of the sealing resin employed in this experiment will be described with reference to FIGS. 11 (a) and 11 (b). In the plan view of the electronic component in FIG. 11A, a lead-shaped electrode 2 is formed on the surface of the substrate 1. As shown in the cross-sectional view of FIG. 11B, the surface of the substrate 1 is covered with the resist 3 including the surface of the electrode 2. A resin mold 4 of a sealing resin is formed on the resist 3.
Is formed. When an external force is applied to the resin mold 4, the resin mold 4 peels off from the surface of the substrate 1, but at this time, the manner of peeling differs depending on the degree of adhesion between the resin mold 4 and the resist 3.
【０００９】即ち、樹脂モールド４とレジスト３の密着
性が良好な場合には、樹脂モールド４に外力を加えた場
合の剥離面はレジスト３と基板１表面との接着面Ｂ（も
しくはレジスト３と電極２との接着面Ｂ’）となり、樹
脂モールド４とレジスト３の密着性が不良の場合には、
剥離は樹脂モールド４とレジスト３の接着面Ｃに発生す
る。ここで、基板１の表面とレジスト３の表面は色彩が
全く異なるので、外力を加えて樹脂モールド４を剥離さ
せたときに、どの接着面から剥離したかを目視により明
瞭に判別することができる。That is, when the adhesiveness between the resin mold 4 and the resist 3 is good, the peeling surface when an external force is applied to the resin mold 4 becomes the adhesive surface B between the resist 3 and the surface of the substrate 1 (or the resist 3 When the adhesive surface between the resin mold 4 and the resist 3 is poor,
Peeling occurs on the bonding surface C between the resin mold 4 and the resist 3. Here, since the surface of the substrate 1 and the surface of the resist 3 are completely different in color, when the resin mold 4 is peeled off by applying an external force, it is possible to visually determine from which adhesive surface the resin mold 4 has been peeled off. .
【００１０】したがって、全剥離面（図１１（ａ）に鎖
線にて示すＡ）に占める接着面Ｂ（またはＢ’）の剥離
面の割合、もしくは接着面Ｃの剥離面の割合を観察する
ことにより、樹脂モールド４とレジスト３面との密着度
を判断することができる。図１１（ａ）では、全剥離面
Ａのうち、ＢまたはＢ’での剥離面（斜線部で示してお
り、電極２が露呈している）が約４０％であり、その他
の部分ではレジスト３が基板１上に残留して電極２が覆
われたままとなっている。Therefore, it is necessary to observe the ratio of the peeled surface of the adhesive surface B (or B ') or the ratio of the peeled surface of the adhesive surface C to the total peeled surface (A shown by a chain line in FIG. 11A). Thereby, the degree of adhesion between the resin mold 4 and the surface of the resist 3 can be determined. In FIG. 11 (a), of all the peeled surfaces A, the peeled surface at B or B '(shown by hatching and the electrode 2 is exposed) is about 40%, and the resist is 3 remains on the substrate 1 and the electrode 2 remains covered.
【００１１】この実験では、前記剥離面の割合を目視に
より０から５までの６段階で評価している。剥離面の１
００％が接着面Ｂ，Ｂ’で剥離している場合（すなわ
ち、接着面Ｃは全く剥離しておらず、樹脂モールド４と
レジスト３の密着性が最良の場合）を評価５、１００〜
８０％を評価４、８０〜５０％を評価３、５０〜２０％
を評価２、２０〜０％を評価１、０％を評価０と定義し
ている。図１１（ａ）に示す例では、Ｂ、Ｂ’での剥離
面が約４０％であり、したがって評価２となる。In this experiment, the ratio of the peeled surface was visually evaluated on a scale of 0 to 5. Release surface 1
Evaluation of the case where 00% peeled off at the bonding surfaces B and B '(that is, the case where the bonding surface C was not peeled at all and the adhesion between the resin mold 4 and the resist 3 was the best) was evaluated.
80% evaluated 4, 80-50% evaluated 3, 50-20%
Is defined as evaluation 2, 20 to 0% as evaluation 1, and 0% as evaluation 0. In the example shown in FIG. 11A, the peeled surfaces at B and B ′ are about 40%, and accordingly, the evaluation is 2.
【００１２】ここで再び図１０に戻り、プラズマ処理に
よる接着面Ｃの剥離度合いの変化を説明する。図１０
（ａ）に示すように、プラズマ処理を行わない場合には
接着面Ｃの密着度を示す剥離度合いは最悪の評価０であ
るが、高周波電源出力５０Ｗで５秒程度プラズマ処理を
行うことにより評価は５まで上昇する。そしてプラズマ
処理を３０秒継続して行った場合でもこの結果は変わら
ない。Here, returning to FIG. 10 again, the change in the degree of peeling of the bonding surface C due to the plasma processing will be described. FIG.
As shown in (a), when the plasma processing is not performed, the peeling degree indicating the degree of adhesion of the bonding surface C is the worst evaluation 0, but is evaluated by performing the plasma processing for about 5 seconds at a high frequency power output of 50 W. Rises to 5. This result does not change even when the plasma processing is performed continuously for 30 seconds.
【００１３】これに対し、図１０（ｂ）に示す高周波電
源出力が５００Ｗの例では、プラズマ処理を行わない場
合に評価０であったサンプルが、プラズマ処理時間５秒
程度で評価５まで上昇する点では高周波電源出力５０Ｗ
の場合と同様であるが、高周波電源出力５００Ｗの場合
にはプラズマ処理時間が１０秒程度になると評価は急激
に低下し０となる。すなわち、ある程度以上の出力で所
定時間以上プラズマ処理を行うと樹脂モールド４とレジ
スト３の密着性は悪化する。なお、プラズマ処理の条件
を変えることにより、どのようなメカニズムで密着性に
悪影響を及ぼすかについてはまだ明確に解明されていな
い。On the other hand, in the example shown in FIG. 10B in which the high-frequency power supply output is 500 W, the sample which was evaluated 0 when the plasma processing was not performed rises to the evaluation 5 in about 5 seconds of the plasma processing time. In terms of high frequency power output 50W
However, in the case of the high-frequency power supply output of 500 W, the evaluation drops sharply to 0 when the plasma processing time is about 10 seconds. That is, if the plasma processing is performed for a predetermined time or more with an output of a certain level or more, the adhesion between the resin mold 4 and the resist 3 deteriorates. The mechanism by which the conditions of the plasma treatment are changed to adversely affect the adhesiveness has not yet been clearly elucidated.
【００１４】これらの結果から、樹脂モールド４とレジ
スト３の密着性を確保するためにはプラズマ処理の条件
を低出力もしくは高出力・短時間に限定すればよいよう
に見えるが、しかしながら、樹脂モールド４とレジスト
３の密着性が低下しないプラズマ処理条件（図１０
（ａ）の例）では、高周波電源出力が不足しているため
スパッタリング効果が小さく、プラズマ処理の目的であ
る電極２上の接合阻害物の除去という目的が達成できな
い。From these results, it seems that in order to secure the adhesion between the resin mold 4 and the resist 3, it is sufficient to limit the conditions of the plasma processing to low output or high output for a short time. Plasma treatment conditions under which the adhesion between the resist 4 and the resist 3 does not decrease (FIG. 10)
In example (a), the output of the high-frequency power supply is insufficient, so that the sputtering effect is small, and the object of the plasma treatment, that is, the removal of the bonding obstacle on the electrode 2 cannot be achieved.
【００１５】そして、この接合阻害物除去のために十分
な高周波電源出力の条件、すなわち５００Ｗ、１０秒以
上（図１０（ｂ）の例）では、上述のように樹脂モール
ド４を形成する封止樹脂とレジスト３面の密着性が阻害
される。このように、従来の電子部品製造方法では、電
極２上の接合阻害物除去のためのプラズマ処理を行うと
基板１のレジスト３と樹脂モールド４の密着性が低下
し、樹脂封止後に剥離を生じることがあるという問題点
があった。Under the condition of high-frequency power output sufficient for removing the joining obstacle, that is, 500 W, 10 seconds or more (example of FIG. 10B), the sealing for forming the resin mold 4 as described above is performed. Adhesion between the resin and the resist 3 surface is hindered. As described above, in the conventional electronic component manufacturing method, when plasma processing is performed to remove a bonding inhibitor on the electrode 2, the adhesion between the resist 3 on the substrate 1 and the resin mold 4 is reduced, and peeling after resin sealing is performed. There is a problem that it may occur.
【００１６】そこで本発明は、基板のレジストと樹脂モ
ールドとの密着性を向上させることができる電子部品製
造方法および電子部品を提供することを目的とする。Accordingly, an object of the present invention is to provide an electronic component manufacturing method and an electronic component that can improve the adhesion between a resist on a substrate and a resin mold.
【００１７】[0017]
【課題を解決するための手段】請求項１記載の電子部品
製造方法は、基板に半導体素子を搭載して両者を電気的
に接続し、その後基板上の半導体素子を樹脂封止する電
子部品製造方法であって、基板の電極表面上の接合阻害
物をスパッタリングにより除去する第１のプラズマ処理
工程と、前記第１のプラズマ処理後の基板のレジスト表
面を改質する第２のプラズマ処理工程とを含み、前記第
１のプラズマ処理工程は、少なくとも基板と半導体素子
とを電気的に接続する前に行い、前記第２のプラズマ処
理工程は第１のプラズマ処理を行った後、樹脂封止を行
う前に行うようにした。According to a first aspect of the present invention, there is provided a method of manufacturing an electronic component, comprising mounting a semiconductor element on a substrate, electrically connecting the two, and then sealing the semiconductor element on the substrate with a resin. A first plasma processing step of removing a bonding inhibitor on an electrode surface of a substrate by sputtering, and a second plasma processing step of modifying a resist surface of the substrate after the first plasma processing. The first plasma processing step is performed at least before electrical connection between the substrate and the semiconductor element, and the second plasma processing step is performed after performing the first plasma processing, and then performing resin sealing. It was done before doing.
【００１８】請求項２記載の電子部品製造方法は、請求
項１記載の電子部品製造方法であって、前記第２のプラ
ズマ処理工程において、酸素、塩素、臭素もしくはフッ
素の少なくとも１つ以上を含んだガスを用いたプラズマ
で基板のレジスト表面を改質するようにした。According to a second aspect of the present invention, there is provided the electronic component manufacturing method according to the first aspect, wherein the second plasma processing step includes at least one of oxygen, chlorine, bromine, and fluorine. The resist surface of the substrate is modified by plasma using a gas.
【００１９】請求項３記載の電子部品は、基板に半導体
素子を搭載して両者を電気的に接続し、その後基板上の
半導体素子を樹脂封止して成る電子部品であって、基板
の電極表面上の接合阻害物をスパッタリングにより除去
する第１のプラズマ処理工程と、前記第１のプラズマ処
理後の基板のレジスト表面を改質する第２のプラズマ処
理工程とを含み、前記第１のプラズマ処理工程は、少な
くとも基板と半導体素子とを電気的に接続する前に行
い、前記第２のプラズマ処理工程は第１のプラズマ処理
を行った後、樹脂封止を行う前に行う電子部品製造方法
によって製造された。According to a third aspect of the present invention, there is provided an electronic component comprising a semiconductor element mounted on a substrate, electrically connecting the two, and then sealing the semiconductor element on the substrate with a resin. A first plasma processing step of removing a bonding inhibitor on a surface by sputtering, and a second plasma processing step of modifying a resist surface of the substrate after the first plasma processing, wherein the first plasma The processing step is performed at least before electrical connection between the substrate and the semiconductor element, and the second plasma processing step is performed after performing the first plasma processing and before performing resin sealing. Manufactured by.
【００２０】本発明によれば、基板の電極の金膜表面に
生成された接合阻害物をスパッタリングにより除去する
第１のプラズマ処理後に、基板のレジスト表面を改質す
る第２のプラズマ処理工程を設けることにより、ワイヤ
ボンディング後に行われる樹脂封止時の、基板のレジス
ト表面と封止樹脂との密着性を向上させることができ
る。According to the present invention, after the first plasma treatment for removing a bonding inhibitor generated on the gold film surface of the electrode of the substrate by sputtering, the second plasma treatment step for modifying the resist surface of the substrate is performed. By providing this, it is possible to improve the adhesion between the resist surface of the substrate and the sealing resin during resin sealing performed after wire bonding.
【００２１】[0021]
【発明の実施の形態】（実施の形態１）図１は本発明の
実施の形態１の電子部品のプラズマ処理装置の断面図、
図２、図３、図４は本発明の実施の形態１の電子部品の
断面図、図５は本発明の実施の形態１の基板のレジスト
表面と封止樹脂との密着性を示すグラフ、図６、図７、
図８は本発明の実施の形態１の電子部品の断面図であ
る。(Embodiment 1) FIG. 1 is a sectional view of an electronic component plasma processing apparatus according to Embodiment 1 of the present invention.
2, 3, and 4 are cross-sectional views of an electronic component according to the first embodiment of the present invention. FIG. 5 is a graph illustrating adhesion between a resist surface of a substrate and a sealing resin according to the first embodiment of the present invention. 6, 7,
FIG. 8 is a sectional view of the electronic component according to the first embodiment of the present invention.
【００２２】まず図１を参照して電子部品のプラズマ処
理装置について説明する。図１において、真空チャンバ
１１は上部ケーシング１２および下部ケーシング１３に
より形成される。下部ケーシング１３の内部には、下部
電極１４が配設されており、下部電極１４上には基板と
半導体素子より成る電子部品１５が載置される。下部電
極１４は高周波電源１６と接続されており、高周波電源
１６は高周波電源制御部１７によって制御される。また
上部ケーシング１２には上部電極１８が装着され、上部
電極１８は接地部１９に接続された接地電極となってい
る。First, a plasma processing apparatus for electronic components will be described with reference to FIG. In FIG. 1, a vacuum chamber 11 is formed by an upper casing 12 and a lower casing 13. A lower electrode 14 is provided inside the lower casing 13, and an electronic component 15 including a substrate and a semiconductor element is mounted on the lower electrode 14. The lower electrode 14 is connected to a high-frequency power supply 16, which is controlled by a high-frequency power control unit 17. An upper electrode 18 is mounted on the upper casing 12, and the upper electrode 18 is a ground electrode connected to a grounding portion 19.
【００２３】下部ケーシング１３には、真空排気部２
０、第１のガス供給部２１、第２のガス供給部２２およ
び大気開放弁２３がそれぞれ管路により接続されてい
る。真空排気部２０は真空チャンバ１１内を吸引し、排
気する。第１のガス供給部２１、第２のガス供給部２２
はプラズマガス供給手段であり、それぞれ異る種類のプ
ラズマ発生用ガスを真空チャンバ１１に供給する。大気
開放弁２３は真空チャンバ１１内に大気を導入し、真空
を破壊する。制御部２４は、真空排気部２０、第１のガ
ス供給部２１、第２のガス供給部２２、大気開放弁２３
および高周波電源制御部１７を制御する。The lower casing 13 has a vacuum exhaust unit 2
0, a first gas supply unit 21, a second gas supply unit 22, and an atmosphere release valve 23 are respectively connected by pipes. The vacuum exhaust unit 20 sucks and exhausts the inside of the vacuum chamber 11. First gas supply unit 21, second gas supply unit 22
Is a plasma gas supply means for supplying different types of plasma generation gases to the vacuum chamber 11. The atmosphere release valve 23 introduces the atmosphere into the vacuum chamber 11 and breaks the vacuum. The control unit 24 includes a vacuum exhaust unit 20, a first gas supply unit 21, a second gas supply unit 22, an atmosphere release valve 23
And the high-frequency power supply controller 17.
【００２４】この電子部品のプラズマ処理装置は上記の
様に構成されており、以下この電子部品のプラズマ処理
装置を使用した電子部品製造方法について各図を参照し
て説明する。図２において、基板３１の上面には電極３
２が、また下面には電極３３が形成されており、基板３
１の表面はエポキシ樹脂などの樹脂より成るレジスト３
４で被覆されている。電極３２は銅電極３２ａ上にバリ
アメタル層としてニッケル膜３２ｂをニッケルメッキに
よりコーティングし、更にニッケル膜３２ｂの上面に金
膜３２ｃを金メッキによりコーティングして形成されて
いる。また電極３３も同様に銅電極３３ａ、ニッケル膜
３３ｂおよび金膜３３ｃより成る。電極３２と電極３３
は、内部回路３７によって接続されている。The plasma processing apparatus for an electronic component is configured as described above. Hereinafter, a method for manufacturing an electronic component using the plasma processing apparatus for an electronic component will be described with reference to the drawings. In FIG. 2, an electrode 3 is provided on the upper surface of a substrate 31.
2 and an electrode 33 is formed on the lower surface.
The surface of the resist 1 is made of a resin such as an epoxy resin.
4. The electrode 32 is formed by coating a nickel film 32b as a barrier metal layer on the copper electrode 32a by nickel plating, and further coating a gold film 32c on the upper surface of the nickel film 32b by gold plating. The electrode 33 also includes a copper electrode 33a, a nickel film 33b, and a gold film 33c. Electrode 32 and electrode 33
Are connected by an internal circuit 37.
【００２５】次に図３に示すように、基板３１上に半導
体素子４１が基板３１上面に予め塗布された接着剤４２
によって接着される。接着剤４２は熱硬化型であり、半
導体素子４１が搭載された基板３１を熱処理することに
より接着剤４２は硬化し、半導体素子４１は基板３１に
固定される。Next, as shown in FIG. 3, a semiconductor element 41 is provided on the substrate 31 with an adhesive 42 applied on the upper surface of the substrate 31 in advance.
Glued by The adhesive 42 is a thermosetting type, and the adhesive 42 is cured by heat-treating the substrate 31 on which the semiconductor element 41 is mounted, and the semiconductor element 41 is fixed to the substrate 31.
【００２６】図４はこの熱処理後の基板３１の電極３
２，３３の断面図である。金膜３２ｃ，３３ｃ表面には
ニッケル化合物３５，３６が生じている。このニッケル
化合物３５，３６は、メッキ工程で金膜３２ｃ，３３ｃ
中に混入したニッケルのうち、金膜３２ｃの表層付近に
あるものが、熱処理中に金膜３２ｃ，３３ｃの表面で空
気と接触することによって生じるものである。このニッ
ケル化合物３５、３６のうち、上面の電極３２上のニッ
ケル化合物３５は後工程のワイヤボンディングにおい
て、金ワイヤと金膜３２ｃとの接合性を阻害する。FIG. 4 shows the electrode 3 of the substrate 31 after this heat treatment.
It is sectional drawing of 2,33. Nickel compounds 35 and 36 are formed on the surfaces of the gold films 32c and 33c. The nickel compounds 35 and 36 are used as gold films 32c and 33c in the plating process.
Of the nickel mixed in, the one near the surface layer of the gold film 32c is generated by coming into contact with air on the surfaces of the gold films 32c and 33c during the heat treatment. Among the nickel compounds 35 and 36, the nickel compound 35 on the electrode 32 on the upper surface hinders the bondability between the gold wire and the gold film 32c in the wire bonding in a later step.
【００２７】次にこの接合性阻害物であるニッケル化合
物３５を除去するため、第１のプラズマ処理が行われ
る。基板３１を半導体素子４１の面を上向きにして図１
に示す真空チャンバ１１内の下部電極１４上に載置す
る。真空チャンバ１１を閉じた後、真空排気部２０を駆
動して真空チャンバ１１内を真空排気する。次いで第１
のガス供給部２１を駆動して真空チャンバ１１内にプラ
ズマ発生用のアルゴンガスを供給する。この後高周波電
源１６を駆動して下部電極１４に高周波電圧を印加する
ことにより、真空チャンバ１１内にプラズマ放電を発生
させる。これにより真空チャンバ１１内にはプラズマが
発生し、この結果アルゴンイオンや電子が電子部品１５
の上面に衝突する。Next, a first plasma treatment is performed in order to remove the nickel compound 35 which is a bonding inhibitor. FIG. 1 shows the semiconductor device 41 with the substrate 31 facing upward.
Is placed on the lower electrode 14 in the vacuum chamber 11 shown in FIG. After closing the vacuum chamber 11, the vacuum exhaust unit 20 is driven to evacuate the vacuum chamber 11. Then the first
Is driven to supply an argon gas for plasma generation into the vacuum chamber 11. Thereafter, the high-frequency power supply 16 is driven to apply a high-frequency voltage to the lower electrode 14, thereby generating a plasma discharge in the vacuum chamber 11. As a result, plasma is generated in the vacuum chamber 11, and as a result, argon ions and electrons are generated in the electronic component 15.
Collides with the upper surface of.
【００２８】この第１のプラズマ処理における処理条件
は、プラズマ発生用ガスとしてのアルゴンガスの流量が
５ｃｃ／ｍｉｎ、真空チャンバ１１内のプラズマ発生用
ガスの圧力が１０Ｐａ、高周波電源出力が５００Ｗ、プ
ラズマ処理時間は１０秒である。このプラズマ処理によ
り電極３２の表面のニッケル化合物３５は除去される
が、前述のようにこのままの状態では封止樹脂とレジス
ト３４表面との密着性が悪く、封止のための樹脂モール
ド形成後に剥離を生じやすい。The processing conditions in the first plasma processing are as follows: the flow rate of argon gas as a plasma generating gas is 5 cc / min, the pressure of the plasma generating gas in the vacuum chamber 11 is 10 Pa, the high frequency power output is 500 W, the plasma Processing time is 10 seconds. Although the nickel compound 35 on the surface of the electrode 32 is removed by this plasma treatment, the adhesion between the sealing resin and the surface of the resist 34 is poor in this state as described above. Tends to occur.
【００２９】そこで、引き続き基板３１の表面を改質す
るための第２のプラズマ処理を行う。この第２のプラズ
マ処理における処理条件は、プラズマ発生用ガスとして
第２のガス供給部２２から供給される酸素ガスを用い、
酸素ガス流量が５０ｃｃ／ｍｉｎ、真空チャンバ１１内
のプラズマ発生用ガスの圧力が３０Ｐａ、高周波電源出
力が２０Ｗ、である。この条件で第二のプラズマ処理を
行った場合の樹脂モールド４の密着性確認のための実験
の結果を図５に示す。Then, a second plasma process for modifying the surface of the substrate 31 is performed. The processing conditions in the second plasma processing use oxygen gas supplied from the second gas supply unit 22 as a plasma generation gas,
The oxygen gas flow rate is 50 cc / min, the pressure of the plasma generating gas in the vacuum chamber 11 is 30 Pa, and the high frequency power output is 20 W. FIG. 5 shows the results of an experiment for confirming the adhesion of the resin mold 4 when the second plasma treatment was performed under these conditions.
【００３０】図５に示すように、第１のプラズマ処理を
行っただけのサンプルでは、密着性の評価は０であり樹
脂モールド４とレジスト３の密着性は悪いが、酸素ガス
による第２のプラズマ処理を５秒行うと、密着性の評価
は５に上昇する。そして同一条件で処理時間を３０秒ま
で延長しても密着性の評価は変わらない。このように、
第１のプラズマ処理によって密着性が低下した基板３１
の表面に上述の条件で第２のプラズマ処理を行うことに
より、基板３１のレジスト３４の表面が改質され後工程
での樹脂モールドとの密着性を向上させることができ
る。As shown in FIG. 5, in the sample subjected to only the first plasma treatment, the evaluation of the adhesiveness is 0, and the adhesiveness between the resin mold 4 and the resist 3 is poor. When the plasma treatment is performed for 5 seconds, the evaluation of the adhesion increases to 5. Even if the processing time is extended to 30 seconds under the same conditions, the evaluation of the adhesion does not change. in this way,
Substrate 31 having reduced adhesion due to first plasma processing
By performing the second plasma treatment on the surface of the substrate under the above-described conditions, the surface of the resist on the substrate 31 is modified, and the adhesion to the resin mold in a later step can be improved.
【００３１】次に図６に示すように、電子部品５はワイ
ヤボンディング装置に送られ、半導体素子４１の電極４
３と基板３１の電極３２を金ワイヤ４４で接続する。こ
れにより、半導体４１と電極３２が電気的に接続され
る。このとき、電極３２の金膜３２ｃの表面は第１のプ
ラズマ処理によりニッケル化合物の接合阻害物が除去さ
れているので、金ワイヤ４４は電極３２上に良好にボン
ディングされる。Next, as shown in FIG. 6, the electronic component 5 is sent to a wire bonding apparatus,
3 and the electrode 32 of the substrate 31 are connected by a gold wire 44. Thereby, the semiconductor 41 and the electrode 32 are electrically connected. At this time, since the surface of the gold film 32 c of the electrode 32 has been subjected to the first plasma treatment to remove the bonding inhibitor of the nickel compound, the gold wire 44 is favorably bonded onto the electrode 32.
【００３２】次に電子部品１５は樹脂封止される。図７
に示すように、半導体素子４１と金ワイヤ４４はエポキ
シ樹脂によって封止され樹脂モールド４５が形成され
る。このとき、基板３１のレジスト３４の表面は第２の
プラズマ処理によって改質されているので、封止樹脂で
あるエポキシ樹脂との密着性が改善されており、密着性
のよい良好な耐剥離性を有する樹脂モールド４５を形成
することができる。Next, the electronic component 15 is sealed with a resin. FIG.
As shown in (1), the semiconductor element 41 and the gold wire 44 are sealed with an epoxy resin to form a resin mold 45. At this time, since the surface of the resist 34 on the substrate 31 has been modified by the second plasma treatment, the adhesion with the epoxy resin as the sealing resin is improved, and the separation resistance is good with good adhesion. Can be formed.
【００３３】この後、図８に示すように基板３１の下面
の電極３３上に半田バンプ４６が形成されて電子部品１
５が完成する。このとき、電極３３の金膜３３ｃの表面
にはニッケル化合物が存在しているが、半田バンプ４６
の形成に際してはフラックス４７が塗布されてニッケル
化合物は還元されるため半田接合性を損なうことはな
い。なお実施の形態１では、第２のプラズマ処理のプラ
ズマ発生用ガスとして酸素を用いているが、塩素やフッ
素、臭素を用いてもよく、またはこれらを混合したもの
でも良い。Thereafter, as shown in FIG. 8, a solder bump 46 is formed on the electrode 33 on the lower surface of the substrate 31 so that the electronic component 1
5 is completed. At this time, although the nickel compound exists on the surface of the gold film 33c of the electrode 33, the solder bump 46
When the flux 47 is formed, the flux 47 is applied and the nickel compound is reduced, so that the soldering property is not impaired. Note that in Embodiment 1, oxygen is used as the plasma generation gas in the second plasma treatment, but chlorine, fluorine, or bromine may be used, or a mixture of these may be used.
【００３４】（実施の形態２）図９は本発明の実施の形
態２の電子部品のプラズマ処理装置の断面図である。こ
こで図１に示す実施の形態１と同様の要素には同符号を
付して説明を省略する。本実施の形態２では、プラズマ
ガス供給手段として、ガス供給部５０と流量制御部５１
を備えている。すなわち、プラズマガス発生用ガスの種
類は１つであり、このガスの真空チャンバ１１への供給
流量を制御部２４により制御するようになっている。(Embodiment 2) FIG. 9 is a sectional view of a plasma processing apparatus for electronic components according to Embodiment 2 of the present invention. Here, the same elements as those of the first embodiment shown in FIG. In the second embodiment, as the plasma gas supply means, the gas supply unit 50 and the flow control unit 51
It has. That is, the type of the plasma gas generating gas is one, and the flow rate of the gas supplied to the vacuum chamber 11 is controlled by the control unit 24.
【００３５】次に本実施の形態２の電子部品の製造方法
について説明する。ここで基板３１上に半導体素子４１
を搭載する工程までは、実施の形態１の図２〜図４に示
す工程と同様である。この後に行われる第１および第２
のプラズマ処理について説明する。図９において、真空
チャンバ１内に電子部品１５を搬入した後、真空チャン
バ１１内にはプラズマ発生用ガスとして酸素ガスが供給
される。次いで高周波電源１６を駆動して下部電極１４
に高周波電圧を印加することにより、真空チャンバ１１
内には酸素のプラズマが発生し、発生した酸素イオンや
酸素ラジカルのスパッタリング効果により電子部品１５
の表面のプラズマ処理を行う。この第１のプラズマ処理
で適用される処理条件は、電極３２の金膜３２ｃ上面の
ニッケル化合物を除去するのに十分なスパッタリング効
果を生じるプラズマ処理条件であり、この結果電極３２
の金膜３２ｃ表面のニッケル化合物４３が除去される。Next, a method for manufacturing an electronic component according to the second embodiment will be described. Here, the semiconductor element 41 is provided on the substrate 31.
The steps up to the step of mounting are the same as the steps shown in FIGS. The first and second
Will be described. In FIG. 9, after the electronic component 15 is carried into the vacuum chamber 1, oxygen gas is supplied into the vacuum chamber 11 as a plasma generating gas. Next, the high frequency power supply 16 is driven to drive the lower electrode 14.
By applying a high-frequency voltage to the vacuum chamber 11
Oxygen plasma is generated inside the electronic component 15 due to the sputtering effect of generated oxygen ions and oxygen radicals.
Of the surface of is performed. The processing conditions applied in the first plasma processing are plasma processing conditions that produce a sputtering effect sufficient to remove the nickel compound on the upper surface of the gold film 32c of the electrode 32. As a result, the electrode 32
The nickel compound 43 on the surface of the gold film 32c is removed.
【００３６】次に、基板３１の表面を改質するための第
２のプラズマ処理が行われる。ここではプラズマ発生用
ガスとして引き続き酸素ガスが使用されるが、酸素ガス
の流量が流量制御弁５１によって制御され、第１のプラ
ズマ処理時のガス供給量より少ない流量のガスが真空チ
ャンバ１１に供給される。また高周波電源１６の出力も
第１のプラズマ処理よりも低い処理条件に設定され、具
体的には、実施の形態１における第２のプラズマ処理の
条件と同様である。Next, a second plasma treatment for modifying the surface of the substrate 31 is performed. Here, oxygen gas is continuously used as the plasma generation gas. The flow rate of the oxygen gas is controlled by the flow control valve 51, and a gas having a flow rate smaller than the gas supply amount during the first plasma processing is supplied to the vacuum chamber 11. Is done. The output of the high-frequency power supply 16 is also set to a processing condition lower than that of the first plasma processing, and specifically, is the same as the condition of the second plasma processing in the first embodiment.
【００３７】これにより、実施の形態１と同様に基板３
１のレジスト３４の表面が改質され、樹脂封止時のエポ
キシ樹脂との密着性が向上する。なお、プラズマ発生用
ガスとして本実施の形態２では酸素を用いているが、塩
素やフッ素、臭素を用いてもよく、またはこれらを混合
したものを用いることもできる。これ以降の工程につい
ては、実施の形態１と同様である。Thus, as in the first embodiment, the substrate 3
The surface of the first resist 34 is modified, and the adhesion to the epoxy resin during resin sealing is improved. Although oxygen is used as the plasma generation gas in the second embodiment, chlorine, fluorine, or bromine may be used, or a mixture of these may be used. The subsequent steps are the same as in the first embodiment.
【００３８】本発明は上記実施の形態１、２に限定され
ないのであって、例えば上記実施の形態１、２では第１
および第２のプラズマ処理を同一のプラズマ処理装置を
用いて連続して行うようにしているが、これらを分離し
１つのプラズマ処理装置にて第１のプラズマ処理を行
い、その後ワイヤボンディングを行った後に他のプラズ
マ処理装置にて第２のプラズマ処理を行うようにしても
よい。このようにすることにより、プラズマ処理条件を
その都度切り換える必要がなく、連続して効率よくプラ
ズマ処理を行うことができる。さらに、基板と半導体素
子を電気的に接続する工程として、ワイヤボンディング
を例に説明したが、ワイヤ以外の接合材（半田、導電性
接着材、異方性導電材等）を使用したフェイスダウンボ
ンディングでもよい。The present invention is not limited to the first and second embodiments. For example, in the first and second embodiments, the first
And the second plasma processing are continuously performed using the same plasma processing apparatus. However, these are separated, the first plasma processing is performed in one plasma processing apparatus, and then the wire bonding is performed. The second plasma processing may be performed later by another plasma processing apparatus. By doing so, it is not necessary to switch the plasma processing conditions each time, and the plasma processing can be continuously and efficiently performed. Further, wire bonding has been described as an example of a process for electrically connecting a substrate and a semiconductor element. However, face-down bonding using a bonding material other than wires (solder, conductive adhesive, anisotropic conductive material, etc.) May be.
【００３９】[0039]
【発明の効果】本発明によれば、基板の電極の金膜表面
に生成された接合阻害物をスパッタリングにより除去す
る第１のプラズマ処理後に、基板のレジスト表面を改質
する第２のプラズマ処理工程を設けるようにしたので、
電極のワイヤボンディング性の向上目的に行われる第１
のプラズマ処理によって基板のレジスト表面が過剰処理
された場合でも、基板のレジストの樹脂材料に応じて第
２のプラズマ処理の条件を適切に設定することにより、
基板のレジストと封止樹脂との密着性を向上させること
ができる。したがって従来は電極上の接合阻害物除去の
ためのプラズマ処理後に密着性が低下することを理由と
して選択することができなかった材質でも、第２のプラ
ズマ条件の設定によって選択が可能となり、基板や封止
材の樹脂材料の選択の自由度を拡大することができる。According to the present invention, after the first plasma treatment for removing the bonding inhibitor generated on the surface of the gold film of the electrode of the substrate by sputtering, the second plasma treatment for modifying the resist surface of the substrate. Since we set up a process,
The first is performed for the purpose of improving the wire bonding property of the electrode.
Even if the resist surface of the substrate is excessively treated by the plasma treatment, by appropriately setting the conditions of the second plasma treatment according to the resin material of the resist of the substrate,
The adhesion between the resist on the substrate and the sealing resin can be improved. Therefore, even a material which could not be selected conventionally because the adhesion is reduced after the plasma treatment for removing the bonding inhibitor on the electrode can be selected by setting the second plasma condition, and the substrate and the The degree of freedom in selecting a resin material for the sealing material can be increased.
【図１】本発明の実施の形態１の電子部品のプラズマ処
理装置の断面図FIG. 1 is a cross-sectional view of an electronic component plasma processing apparatus according to a first embodiment of the present invention.
【図２】本発明の実施の形態１の電子部品の断面図FIG. 2 is a cross-sectional view of the electronic component according to the first embodiment of the present invention.
【図３】本発明の実施の形態１の電子部品の断面図FIG. 3 is a cross-sectional view of the electronic component according to the first embodiment of the present invention.
【図４】本発明の実施の形態１の電子部品の断面図FIG. 4 is a cross-sectional view of the electronic component according to the first embodiment of the present invention.
【図５】本発明の実施の形態１の基板のレジスト表面と
封止樹脂の密着性を示すグラフFIG. 5 is a graph showing the adhesion between the resist surface of the substrate and the sealing resin according to the first embodiment of the present invention.
【図６】本発明の実施の形態１の電子部品の断面図FIG. 6 is a sectional view of the electronic component according to the first embodiment of the present invention.
【図７】本発明の実施の形態１の電子部品の断面図FIG. 7 is a sectional view of the electronic component according to the first embodiment of the present invention.
【図８】本発明の実施の形態１の電子部品の断面図FIG. 8 is a sectional view of the electronic component according to the first embodiment of the present invention.
【図９】本発明の実施の形態２の電子部品のプラズマ処
理装置の断面図FIG. 9 is a sectional view of a plasma processing apparatus for an electronic component according to a second embodiment of the present invention.
【図１０】（ａ）実験対象基板のレジスト表面と封止樹
脂の密着性を示すグラフ （ｂ）実験対象基板のレジスト表面と封止樹脂の密着性
を示すグラフ10A is a graph showing the adhesion between the resist surface of the test target substrate and the sealing resin, and FIG. 10B is a graph showing the adhesion between the resist surface of the test target substrate and the sealing resin.
【図１１】（ａ）実験対象基板の平断面図 （ｂ）実験対象基板の側断面図FIG. 11A is a cross-sectional plan view of the test target substrate. FIG.
【符号の説明】 １１ 真空チャンバ １４ 下部電極 １５ 電子部品 １６ 高周波電源 １７ 高周波電源制御部 ２０ 真空排気部 ２１ 第１のガス供給部 ２２ 第２のガス供給部 ３１ 基板 ３２、３３ 電極 ３４ レジスト ３２ａ、３３ａ 銅電極 ３２ｂ、３３ｂ ニッケル膜 ３２ｃ、３３ｃ 金膜 ３５、３６ ニッケル化合物 ４１ 半導体素子 ４４ 金ワイヤ ４５ 樹脂モールドDESCRIPTION OF SYMBOLS 11 Vacuum chamber 14 Lower electrode 15 Electronic component 16 High frequency power supply 17 High frequency power supply control unit 20 Vacuum exhaust unit 21 First gas supply unit 22 Second gas supply unit 31 Substrate 32, 33 Electrode 34 Resist 32a, 33a Copper electrode 32b, 33b Nickel film 32c, 33c Gold film 35, 36 Nickel compound 41 Semiconductor element 44 Gold wire 45 Resin mold
───────────────────────────────────────────────────── フロントページの続き (72)発明者 森迫 勇 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 吉田 尚人 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F044 AA03 CC01 CC02 JJ03 5F061 AA01 BA03 CB02 CB12 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Isamu Morisako 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. F term (reference) 5F044 AA03 CC01 CC02 JJ03 5F061 AA01 BA03 CB02 CB12
Claims (3)
に接続し、その後基板上の半導体素子を樹脂封止する電
子部品製造方法であって、基板の電極表面上の接合阻害
物をスパッタリングにより除去する第１のプラズマ処理
工程と、前記第１のプラズマ処理後の基板のレジスト表
面を改質する第２のプラズマ処理工程とを含み、前記第
１のプラズマ処理工程は、少なくとも基板と半導体素子
とを電気的に接続する前に行い、前記第２のプラズマ処
理工程は第１のプラズマ処理を行った後、樹脂封止を行
う前に行うことを特徴とする電子部品製造方法。1. A method for manufacturing an electronic component, comprising mounting a semiconductor element on a substrate, electrically connecting the two, and then sealing the semiconductor element on the substrate with a resin. A first plasma processing step of removing by sputtering, and a second plasma processing step of modifying the resist surface of the substrate after the first plasma processing, wherein the first plasma processing step includes at least An electronic component manufacturing method, wherein the method is performed before electrical connection with a semiconductor element, and the second plasma processing step is performed after performing the first plasma processing and before performing resin sealing.
素、塩素、臭素もしくはフッ素の少なくとも１つ以上を
含んだガスを用いたプラズマで基板のレジスト表面を改
質することを特徴とする請求項１記載の電子部品製造方
法。2. The method according to claim 1, wherein in the second plasma processing step, the resist surface of the substrate is modified with plasma using a gas containing at least one of oxygen, chlorine, bromine and fluorine. 2. The electronic component manufacturing method according to 1.
に接続し、その後基板上の半導体素子を樹脂封止して成
る電子部品であって、基板の電極表面上の接合阻害物を
スパッタリングにより除去する第１のプラズマ処理工程
と、前記第１のプラズマ処理後の基板のレジスト表面を
改質する第２のプラズマ処理工程とを含み、前記第１の
プラズマ処理工程は、少なくとも基板と半導体素子とを
電気的に接続する前に行い、前記第２のプラズマ処理工
程は第１のプラズマ処理を行った後、樹脂封止を行う前
に行う電子部品製造方法によって製造されたことを特徴
とする電子部品。3. An electronic component comprising a semiconductor element mounted on a substrate, electrically connecting the two, and then sealing the semiconductor element on the substrate with a resin. A first plasma processing step of removing by sputtering, and a second plasma processing step of modifying the resist surface of the substrate after the first plasma processing, wherein the first plasma processing step includes at least The semiconductor device is manufactured by an electronic component manufacturing method which is performed before electrical connection with a semiconductor element, and wherein the second plasma processing step is performed after performing the first plasma processing and before performing resin sealing. And electronic components.
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| JP2001216365A JP3671879B2 (en) | 2001-07-17 | 2001-07-17 | Electronic component manufacturing method and electronic component |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001216365A JP3671879B2 (en) | 2001-07-17 | 2001-07-17 | Electronic component manufacturing method and electronic component |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31016497A Division JP3427702B2 (en) | 1997-11-12 | 1997-11-12 | Plasma processing equipment for electronic parts |
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|---|---|
| JP2002118128A true JP2002118128A (en) | 2002-04-19 |
| JP3671879B2 JP3671879B2 (en) | 2005-07-13 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006098949A (en) * | 2004-09-30 | 2006-04-13 | Sumitomo Bakelite Co Ltd | Semiconductor device |
| JP2008066754A (en) * | 2007-11-22 | 2008-03-21 | Sanyo Electric Co Ltd | Method for manufacturing circuit device |
| US7364941B2 (en) | 2002-12-04 | 2008-04-29 | Sanyo Electric Co., Ltd. | Circuit device manufacturing method |
| JP2009231680A (en) * | 2008-03-25 | 2009-10-08 | Panasonic Corp | Surface treatment method and surface treatment device of substrate, and method of manufacturing semiconductor package |
| CN114823970A (en) * | 2022-03-25 | 2022-07-29 | 昆明物理研究所 | Method for increasing adhesiveness of photoresist on superlattice infrared focal plane chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0837182A (en) * | 1994-07-22 | 1996-02-06 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH08153833A (en) * | 1994-11-29 | 1996-06-11 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
-
2001
- 2001-07-17 JP JP2001216365A patent/JP3671879B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0837182A (en) * | 1994-07-22 | 1996-02-06 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH08153833A (en) * | 1994-11-29 | 1996-06-11 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7364941B2 (en) | 2002-12-04 | 2008-04-29 | Sanyo Electric Co., Ltd. | Circuit device manufacturing method |
| JP2006098949A (en) * | 2004-09-30 | 2006-04-13 | Sumitomo Bakelite Co Ltd | Semiconductor device |
| JP2008066754A (en) * | 2007-11-22 | 2008-03-21 | Sanyo Electric Co Ltd | Method for manufacturing circuit device |
| JP4642061B2 (en) * | 2007-11-22 | 2011-03-02 | 三洋電機株式会社 | Circuit device manufacturing method |
| JP2009231680A (en) * | 2008-03-25 | 2009-10-08 | Panasonic Corp | Surface treatment method and surface treatment device of substrate, and method of manufacturing semiconductor package |
| CN114823970A (en) * | 2022-03-25 | 2022-07-29 | 昆明物理研究所 | Method for increasing adhesiveness of photoresist on superlattice infrared focal plane chip |
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| Publication number | Publication date |
|---|---|
| JP3671879B2 (en) | 2005-07-13 |
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