JP5120004B2 - Substrate surface treatment method and semiconductor package manufacturing method - Google Patents

Substrate surface treatment method and semiconductor package manufacturing method Download PDF

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JP5120004B2
JP5120004B2 JP2008077308A JP2008077308A JP5120004B2 JP 5120004 B2 JP5120004 B2 JP 5120004B2 JP 2008077308 A JP2008077308 A JP 2008077308A JP 2008077308 A JP2008077308 A JP 2008077308A JP 5120004 B2 JP5120004 B2 JP 5120004B2
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substrate
region
semiconductor package
surface treatment
film
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JP2009231680A (en
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宏 土師
勇 森迫
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

本発明は、基板の表面処理方法および表面処理装置ならびに半導体パッケージの製造方法に関するものである。   The present invention relates to a substrate surface treatment method, a surface treatment apparatus, and a semiconductor package manufacturing method.

基板に実装したシリコンチップ（半導体装置）を樹脂で封止した半導体パッケージにおいては、基板のレジスト膜と樹脂との密着性は良好であるが、基板の電極部分はその表面を覆う金メッキ膜によって樹脂との密着性が劣っていることが分かっている（特許文献１乃至３参照）。
特開平１０−３４０９７７号公報 特開平１１−１４５１２０号公報 特開２００４−１７２４４４号公報 In a semiconductor package in which a silicon chip (semiconductor device) mounted on a substrate is sealed with a resin, the adhesion between the resist film of the substrate and the resin is good, but the electrode portion of the substrate is resinized by a gold plating film covering the surface It has been found that the adhesiveness is poor (see Patent Documents 1 to 3).
Japanese Patent Laid-Open No. 10-340977 JP-A-11-145120 JP 2004-172444 A

樹脂密着性の向上を目的として基板にプラズマ処理を施した場合、基板の表面の大部分を覆うレジスト膜は樹脂密着性が向上することになるが、電極部を覆う金メッキ膜の表面については逆に清浄化されてしまうため、樹脂密着性が低下する結果となってしてしまう。近年は半導体パッケージの小型化がますます進展し、基板の表面積に占める電極部分の面積の割合が相対的に大きくなってきているので、基板と封止用樹脂との接着強度を維持するためには金メッキ膜についても樹脂密着性を向上させることが望ましい。   When plasma treatment is performed on the substrate for the purpose of improving the resin adhesion, the resist film covering most of the surface of the substrate improves the resin adhesion, but the reverse of the surface of the gold plating film covering the electrode part. As a result, the resin adhesion deteriorates. In recent years, the miniaturization of semiconductor packages has progressed further, and the ratio of the area of the electrode portion to the surface area of the substrate has become relatively large. Therefore, in order to maintain the adhesive strength between the substrate and the sealing resin It is desirable to improve the resin adhesion also for the gold plating film.

本発明は、電極部分を含む基板の樹脂密着性を向上させる基板の表面処理方法等を提供することを目的とする。   An object of the present invention is to provide a substrate surface treatment method for improving the resin adhesion of a substrate including an electrode portion.

請求項１に記載の基板の表面処理方法は、樹脂が露出する第１の領域と金メッキ膜が露出する第２の領域を表面に有する基板の表面処理方法であって、真空チャンバ内に基板の表面と成膜用ターゲットとを対向させて配置し、真空チャンバ内に放電用ガスを供給してプラズマを発生させることで前記第１の領域のアッシングと前記成膜用ターゲットのスパッタリングを行い、前記第１の領域の活性化処理と前記第２の領域に前記成膜用ターゲットの組成物質を付着させる成膜処理とを並行して行う。   The substrate surface treatment method according to claim 1 is a substrate surface treatment method having a first region where a resin is exposed and a second region where a gold plating film is exposed on the surface, and the substrate is disposed in a vacuum chamber. The surface and the film-forming target are arranged to face each other, and a plasma is generated by supplying a discharge gas into the vacuum chamber to perform ashing of the first region and sputtering of the film-forming target, An activation process for the first region and a film formation process for attaching the composition material of the film formation target to the second region are performed in parallel.

請求項２に記載の基板の表面処理方法は請求項１記載の基板の表面処理方法であって、前記成膜用ターゲットが組成物質にＳｉＯ２を含む。 The substrate surface treatment method according to claim 2 is the substrate surface treatment method according to claim 1, wherein the film-forming target contains SiO 2 in a composition material.

請求項３に記載の基板の表面処理方法は請求項１または２記載の基板の表面処理方法であって、前記放電用ガスに少なくともアルゴンと酸素を含む。   A substrate surface treatment method according to a third aspect is the substrate surface treatment method according to the first or second aspect, wherein the discharge gas contains at least argon and oxygen.

請求項４に記載の基板の表面処理方法は請求項１乃至３の何れかに記載の基板の表面処理方法であって、基板の表面に露出する樹脂がソルダレジストである。   The substrate surface treatment method according to claim 4 is the substrate surface treatment method according to any one of claims 1 to 3, wherein the resin exposed on the surface of the substrate is a solder resist.

請求項５に記載の基板の表面処理方法は請求項１乃至４の何れかに記載の基板の表面処理方法であって、前記第１の領域に、基板に実装された半導体装置の表面を覆う有機膜を含む。   The substrate surface treatment method according to claim 5 is the substrate surface treatment method according to any one of claims 1 to 4, wherein the surface of the semiconductor device mounted on the substrate is covered in the first region. Includes organic films.

請求項６に記載の半導体パッケージの製造方法は、樹脂が露出する第１の領域と金メッキ膜が露出する第２の領域を表面に有する基板の表面に半導体装置を実装する工程と、真空チャンバ内に基板の表面と成膜用ターゲットとを間隔をおいて対向配置し、真空チャンバ内に放電用ガスを供給してプラズマを発生させることで前記第１の領域のアッシングと前記成膜用ターゲットのスパッタリングを行い、前記第１の領域の活性化処理と前記第２の領域に前記成膜用ターゲットの組成物質を付着させる成膜処理とを並行して行う表面処理工程と、表面処理された基板の表面を樹脂で封止する工程を含む。 The method of manufacturing a semiconductor package according to claim 6 includes: mounting a semiconductor device on a surface of a substrate having a first region where a resin is exposed and a second region where a gold plating film is exposed; The surface of the substrate and the film formation target are arranged opposite to each other with a space therebetween, and a discharge gas is supplied into the vacuum chamber to generate plasma, thereby ashing the first region and the film formation target. A surface treatment step of performing a sputtering process in parallel with the activation treatment of the first region and the film formation treatment of attaching the composition material of the film formation target to the second region; and a surface-treated substrate The process of sealing the surface of this with resin.

請求項７に記載の半導体パッケージの製造方法は請求項６に記載の半導体パッケージの製造方法であって、前記成膜用ターゲットが組成物質にＳｉＯ２を含む。 A semiconductor package manufacturing method according to a seventh aspect is the semiconductor package manufacturing method according to the sixth aspect , wherein the film-forming target contains SiO 2 in a composition material.

請求項８に記載の半導体パッケージの製造方法は請求項６または７に記載の半導体パッケージの製造方法であって、前記放電用ガスに少なくともアルゴンと酸素を含む。 The semiconductor package manufacturing method according to claim 8 is the semiconductor package manufacturing method according to claim 6 or 7 , wherein the discharge gas contains at least argon and oxygen.

請求項９に記載の半導体パッケージの製造方法は請求項６乃至８の何れかに記載の半導体パッケージの製造方法であって、前記表面に露出する樹脂がソルダレジストである。 The method for manufacturing a semiconductor package according to claim 9 is the method for manufacturing a semiconductor package according to any one of claims 6 to 8 , wherein the resin exposed on the surface is a solder resist.

請求項１０に記載の半導体パッケージの製造方法は請求項６乃至９の何れかに記載の半導体パッケージの製造方法であって、前記第１の領域に、基板に搭載された半導体装置の表面を覆う有機膜を含む。 A method for manufacturing a semiconductor package according to claim 10 is the method for manufacturing a semiconductor package according to any one of claims 6 to 9 , wherein a surface of a semiconductor device mounted on a substrate is covered in the first region. Includes organic films.

アッシング処理が施された第１の領域と、ターゲットの組成物質による膜が形成された第２の領域の両方の領域で樹脂密着性が向上することで、電極の形成箇所を含む基板の表面の略全面において樹脂密着性が向上し、基板と封止用樹脂とを強固に接合することが可能になるので、半導体パッケージの電気的、機械的な信頼性が大幅に向上する。   By improving the resin adhesion in both the first region subjected to the ashing process and the second region where the film made of the target composition material is formed, the surface of the substrate including the electrode formation site is improved. Resin adhesion is improved over almost the entire surface, and the substrate and the sealing resin can be firmly bonded, so that the electrical and mechanical reliability of the semiconductor package is greatly improved.

添付した図面を参照しながら本発明の実施の形態について説明する。図１は半導体パッケージの構造を示す側断面図、図２は本発明の実施の形態の表面処理装置の構造を示す側断面図である。   Embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a side sectional view showing the structure of a semiconductor package, and FIG. 2 is a side sectional view showing the structure of a surface treatment apparatus according to an embodiment of the present invention.

図１に半導体パッケージの構造を示す。半導体パッケージ１は、半導体装置２と基板３を電気的、機械的に接続させた状態で一体的に固定した電子部品である。半導体装置２はダイボンディング用接着剤４によって基板３の上部略中央に固着されている。半導体装置２の上部に形成されているボンディングパッド５と基板３の上部に形成されているワイヤ接続用電極６は導電性のワイヤ７で電気的に接続されている。   FIG. 1 shows the structure of a semiconductor package. The semiconductor package 1 is an electronic component that is integrally fixed in a state where the semiconductor device 2 and the substrate 3 are electrically and mechanically connected. The semiconductor device 2 is fixed to a substantially upper center of the substrate 3 by a die bonding adhesive 4. The bonding pad 5 formed on the upper part of the semiconductor device 2 and the wire connection electrode 6 formed on the upper part of the substrate 3 are electrically connected by a conductive wire 7.

基板３の裏面には表面に形成されているワイヤ接続用電極６と電気的に接続されているバンプ接続用電極８が形成されている。このバンプ接続用電極８は半導体パッケージ１の外部電極として機能する。バンプ接続用電極８には半導体パッケージ１をマザーボード等と接合するための半田製のバンプ９が融着されている。   On the back surface of the substrate 3, bump connection electrodes 8 that are electrically connected to the wire connection electrodes 6 formed on the front surface are formed. The bump connection electrode 8 functions as an external electrode of the semiconductor package 1. Solder bumps 9 for bonding the semiconductor package 1 to a mother board or the like are fused to the bump connection electrodes 8.

基板３の表裏面には、電極６、８以外の領域全体にレジスト膜１０、１１が形成されている。基板表面のレジスト膜１０およびワイヤ接続用電極６は半導体装置２とワイヤ接続用電極６とワイヤ７を封止する樹脂１２と接着されている。   On the front and back surfaces of the substrate 3, resist films 10 and 11 are formed in the entire region other than the electrodes 6 and 8. The resist film 10 and the wire connection electrode 6 on the substrate surface are bonded to the semiconductor device 2, the wire connection electrode 6, and a resin 12 that seals the wire 7.

図２に本発明の実施の形態の表面処理装置の構造を示す。半導体パッケージ１の製造過程では表面処理装置２０を用いて基板３の表面処理を行い、封止用の樹脂１２と基板３との接合性の向上を図る。表面処理装置２０は、密閉空間２１を形成する真空チャンバ２２と、密閉空間２１においてその表面を密閉空間２１の中央部に向けた状態で基板３を保持する基板保持ステージ２３と、密閉空間２１において中央部を挟んで基板３と対向する位置で成膜用ターゲット２４を保持する成膜用ターゲット保持部２５と、密閉空間２１の内圧を減ずる減圧装置２６と、密閉空間２１へ放電用ガスを供給する放電用ガス供給装置２７と、成膜用ターゲット保持部２５に高周波電圧を印加する高周波電源部２８と、密閉空間２１を大気開放する大気開放バルブ２９と、放電用ガスの供給量を調整する流量調整バルブ３０を備えている。   FIG. 2 shows the structure of the surface treatment apparatus according to the embodiment of the present invention. In the process of manufacturing the semiconductor package 1, the surface treatment of the substrate 3 is performed using the surface treatment device 20 to improve the bonding property between the sealing resin 12 and the substrate 3. The surface treatment apparatus 20 includes a vacuum chamber 22 that forms a sealed space 21, a substrate holding stage 23 that holds the substrate 3 with the surface thereof facing the center of the sealed space 21, and a sealed space 21. A deposition target holding unit 25 that holds the deposition target 24 at a position facing the substrate 3 across the center, a decompression device 26 that reduces the internal pressure of the sealed space 21, and a discharge gas to the sealed space 21 The discharge gas supply device 27, the high-frequency power supply unit 28 that applies a high-frequency voltage to the film-forming target holding unit 25, the air release valve 29 that opens the sealed space 21 to the atmosphere, and the supply amount of the discharge gas is adjusted. A flow rate adjusting valve 30 is provided.

表面処理装置２０を用いて表面処理を施す対象は多面取基板３１であり、表面処理を施した後に樹脂１２で封止し、最終的に個々の半導体パッケージ１に個片化することになる。多面取基板３１を基板保持ステージ２３に載置し、減圧した密閉室内２１に放電用ガスを充満させた状態で高周波電圧を印加すると、放電用ガスに含まれるアルゴンや酸素がプラズマ状態に遷移する。すると、プラズマに含まれるイオンは高周波電源部２８側に接続されている成膜用ターゲット２４に高速で衝突する。また、プラズマに含まれる酸素ラジカルは多面取基板３１のレジスト膜１０と反応してレジスト膜１０をガス化して除去する。一方、ワイヤ接続用電極６の表面は金メッキで覆われているため酸素ラジカルの影響を受けることはない。この結果、多面取基板３１のレジスト膜１０に対してはアッシング処理が行われ、成膜用ターゲット２４に対してはスパッタリング処理が行われる。多面取基板３１の表面は、半導体装置２の表面を覆う有機膜３２とレジスト膜１０が露出する第１の領域と、ワイヤ接続用電極６の表面に金メッキ膜が露出する第２の領域で構成されている。有機膜３２はポリイミド等の絶縁性樹脂で構成され、半導体装置２を保護するものである。   An object to be surface-treated using the surface treatment apparatus 20 is a multi-sided substrate 31, which is sealed with the resin 12 after being subjected to the surface treatment, and finally separated into individual semiconductor packages 1. When the multi-sided substrate 31 is placed on the substrate holding stage 23 and a high frequency voltage is applied in a state where the decompressed sealed chamber 21 is filled with the discharge gas, argon and oxygen contained in the discharge gas transition to a plasma state. . Then, ions contained in the plasma collide at high speed with the film-forming target 24 connected to the high-frequency power supply unit 28 side. Further, oxygen radicals contained in the plasma react with the resist film 10 on the multi-planar substrate 31 to gasify and remove the resist film 10. On the other hand, since the surface of the wire connection electrode 6 is covered with gold plating, it is not affected by oxygen radicals. As a result, the ashing process is performed on the resist film 10 of the multi-sided substrate 31, and the sputtering process is performed on the film formation target 24. The surface of the multi-sided substrate 31 includes a first region where the organic film 32 and the resist film 10 covering the surface of the semiconductor device 2 are exposed, and a second region where the gold plating film is exposed on the surface of the wire connection electrode 6. Has been. The organic film 32 is made of an insulating resin such as polyimide and protects the semiconductor device 2.

成膜用ターゲット２４は組成物質にＳｉＯ２を含んでおり、スパッタリング処理によって成膜用ターゲット２４から放出されたＳｉＯ２が成膜用ターゲット２４と対向して配置されている基板３の表面に成膜する。アッシング処理とスパッタリング処理は密閉空間２１で同時並行して進行するが、第１の領域では、ＳｉＯ２が付着したレジスト膜１０や有機膜３２はすぐにアッシングされてしまうため、ＳｉＯ２膜は形成されない。これに対しアッシングされない第２の領域にはＳｉＯ２膜が形成される。 Deposition target 24 includes a SiO 2 to the composition material formed on the surface of the substrate 3 to SiO 2 which is released from the deposition target 24 by sputtering is disposed opposite to the deposition target 24 Film. The ashing process and the sputtering process proceed in parallel in the sealed space 21, but in the first region, the resist film 10 and the organic film 32 to which SiO 2 is adhered are immediately ashed, so that the SiO 2 film is formed. Not. On the other hand, a SiO 2 film is formed in the second region that is not ashed.

アッシング処理が効果的に施された第１の領域は樹脂密着性が向上し、封止用樹脂１２と強固に接合する。これに対し第２の領域は、結果として金メッキ膜上に形成されたＳｉＯ２膜によって封止用の樹脂１２との接合性が向上することになる。これにより、第１の領域と第２の領域を有する多面取基板３１の表面はその略全面において樹脂密着性が向上し、封止用の樹脂１２と強固に接合することで、結果として半導体パッケージ１の電気的、機械的な信頼性が大幅に向上する。 The first region where the ashing treatment has been effectively performed has improved resin adhesion and is firmly bonded to the sealing resin 12. On the other hand, in the second region, as a result, the bonding property with the sealing resin 12 is improved by the SiO 2 film formed on the gold plating film. As a result, the surface of the multi-sided substrate 31 having the first region and the second region has improved resin adhesion over substantially the entire surface thereof, and is firmly bonded to the sealing resin 12, resulting in a semiconductor package. 1 greatly improves the electrical and mechanical reliability.

半導体パッケージ１が小型化した今日においては第１の領域に対する第２の領域の面積
の割合が高くなっているが、表面処理装置２０を用いた表面処理によれば、第１の領域に対してアッシングによる表面処理を施すと同時に第２の領域には成膜用ターゲットの組成物質を付着させる成膜処理を施すことで、両領域の面積比に関係なく基板３の表面の略全面において樹脂密着性を向上させることが可能である。 In the present day when the semiconductor package 1 is downsized, the ratio of the area of the second region to the first region is high. However, according to the surface treatment using the surface treatment apparatus 20, At the same time as the surface treatment by ashing, the second region is subjected to a film-forming process for adhering the composition material of the film-forming target, so that the resin adheres substantially over the entire surface of the substrate 3 regardless of the area ratio of both regions. It is possible to improve the property.

本発明は、電極の形成箇所を含む基板の表面の略全面における樹脂密着性を向上させ、基板と封止用樹脂とを強固に接合することを可能にするので、高品質な半導体パッケージの製造分野において有用である。   Since the present invention improves the resin adhesion on almost the entire surface of the substrate including the electrode forming portion and enables the substrate and the sealing resin to be firmly bonded, manufacturing a high-quality semiconductor package Useful in the field.

半導体パッケージの構造を示す側断面図Side sectional view showing the structure of a semiconductor package 本発明の実施の形態の表面処理装置の構造を示す側断面図Side sectional view which shows the structure of the surface treatment apparatus of embodiment of this invention

符号の説明Explanation of symbols

１ 半導体パッケージ
２ 半導体装置
３ 基板
６ ワイヤ接続用電極
１０ レジスト膜
１２ 封止用の樹脂
２０ 表面処理装置
２１ 密閉空間
２２ 真空チャンバ
２３ 基板保持ステージ
２４ 成膜用ターゲット
２５ 成膜用ターゲット保持部
２６ 減圧装置
２７ 放電用ガス供給装置
２８ 高周波電源部
３１ 多面取基板
３２ 有機膜 DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Semiconductor device 3 Substrate 6 Wire connection electrode 10 Resist film 12 Resin for sealing 20 Surface treatment device 21 Sealed space 22 Vacuum chamber 23 Substrate holding stage 24 Target for film formation 25 Target holding part for film formation 26 Depressurization Equipment 27 Discharge gas supply equipment 28 High frequency power supply 31 Multi-sided substrate 32 Organic film

Claims (10)

樹脂が露出する第１の領域と金メッキ膜が露出する第２の領域を表面に有する基板の表面処理方法であって、
真空チャンバ内に基板の表面と成膜用ターゲットとを対向させて配置し、真空チャンバ内に放電用ガスを供給してプラズマを発生させることで前記第１の領域のアッシングと前記成膜用ターゲットのスパッタリングを行い、前記第１の領域の活性化処理と前記第２の領域に前記成膜用ターゲットの組成物質を付着させる成膜処理とを並行して行うことを特徴とする基板の表面処理方法。 A surface treatment method for a substrate having a first region where a resin is exposed and a second region where a gold plating film is exposed,
In the vacuum chamber, the surface of the substrate and the deposition target are arranged to face each other, and a discharge gas is supplied into the vacuum chamber to generate plasma, thereby ashing the first region and the deposition target. The substrate surface treatment is characterized in that the first region activation treatment and the film formation treatment for attaching the composition material of the film formation target to the second region are performed in parallel. Method. 前記成膜用ターゲットが組成物質にＳｉＯ２を含むことを特徴とする請求項１記載の基板の表面処理方法。 The substrate surface treatment method according to claim 1, wherein the deposition target contains SiO 2 in a composition material. 前記放電用ガスに少なくともアルゴンと酸素を含むことを特徴とする請求項１または２記載の基板の表面処理方法。   3. The substrate surface processing method according to claim 1, wherein the discharge gas contains at least argon and oxygen. 基板の表面に露出する樹脂がソルダレジストであることを特徴とする請求項１乃至３の何れかに記載の基板の表面処理方法。   4. The substrate surface treatment method according to claim 1, wherein the resin exposed on the surface of the substrate is a solder resist. 前記第１の領域に、基板に実装された半導体装置の表面を覆う有機膜を含むことを特徴とする請求項１乃至４の何れかに記載の基板の表面処理方法。   The substrate surface treatment method according to claim 1, wherein the first region includes an organic film that covers a surface of a semiconductor device mounted on the substrate. 樹脂が露出する第１の領域と金メッキ膜が露出する第２の領域を表面に有する基板の表面に半導体装置を実装する工程と、真空チャンバ内に基板の表面と成膜用ターゲットとを間隔をおいて対向配置し、真空チャンバ内に放電用ガスを供給してプラズマを発生させることで前記第１の領域のアッシングと前記成膜用ターゲットのスパッタリングを行い、前記第１の領域の活性化処理と前記第２の領域に前記成膜用ターゲットの組成物質を付着させる成膜処理とを並行して行う表面処理工程と、表面処理された基板の表面を樹脂で封止する工程を含むことを特徴とする半導体パッケージの製造方法。   A step of mounting the semiconductor device on the surface of the substrate having a first region where the resin is exposed and a second region where the gold plating film is exposed; and a distance between the surface of the substrate and the deposition target in the vacuum chamber. The first region is ashed and the film-forming target is sputtered by supplying a discharge gas into the vacuum chamber and generating a plasma, thereby activating the first region. And a surface treatment step of performing a film formation process for attaching the composition material of the film formation target to the second region in parallel, and a step of sealing the surface of the surface-treated substrate with a resin. A method of manufacturing a semiconductor package. 前記成膜用ターゲットが組成物質にＳｉＯ２を含むことを特徴とする請求項６に記載の半導体パッケージの製造方法。 The method of manufacturing a semiconductor package according to claim 6 , wherein the deposition target includes SiO 2 in a composition material. 前記放電用ガスに少なくともアルゴンと酸素を含むことを特徴とする請求項６または７に記載の半導体パッケージの製造方法。 The method of manufacturing a semiconductor package according to claim 6 or 7, characterized in that it comprises at least argon and oxygen in the discharge gas. 前記表面に露出する樹脂がソルダレジストであることを特徴とする請求項６乃至８の何れかに記載の半導体パッケージの製造方法。 The method of manufacturing a semiconductor package according to any one of claims 6 to 8 resin exposed on the surface, characterized in that a solder resist. 前記第１の領域に、基板に搭載された半導体装置の表面を覆う有機膜を含むことを特徴とする請求項６乃至９の何れかに記載の半導体パッケージの製造方法。 Wherein the first region, a method of manufacturing a semiconductor package according to any one of claims 6-9, characterized in that it comprises an organic film covering the surface of the semiconductor device mounted on the substrate.
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