JP2007250834A - Manufacturing method of electronic component device - Google Patents

Manufacturing method of electronic component device Download PDF

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Publication number
JP2007250834A
JP2007250834A JP2006072349A JP2006072349A JP2007250834A JP 2007250834 A JP2007250834 A JP 2007250834A JP 2006072349 A JP2006072349 A JP 2006072349A JP 2006072349 A JP2006072349 A JP 2006072349A JP 2007250834 A JP2007250834 A JP 2007250834A
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Prior art keywords
electrode film
metal plate
electronic component
component device
semiconductor chip
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Japanese (ja)
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Takatoshi Ishikawa
隆稔 石川
Kozo Kinki
浩三 金氣
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2006072349A priority Critical patent/JP2007250834A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To inexpensively manufacture a light-weighted and thin electronic component device. <P>SOLUTION: An electrode film 13 is formed of a resist pattern formed on the surface of a metallic plate 10. A terminal 3 formed on a semiconductor chip 2 after removal of the resist pattern is electrically connected with the electrode film 13 via a bump 5. After the semiconductor chip 2 and the electrode film 13 are molded with resin 6, they are exfoliated from the metallic plate 10. Thus, the electronic component device 1 can be manufactured without using a lead frame, and the light-weighted and thin device 1 can be manufactured. In addition, no separating (cutting) step of the lead frame is necessary, thereby reducing a cost and shortening time required for the manufacture. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体チップがパッケージされた電子部品装置の製造方法に関するものである。   The present invention relates to a method for manufacturing an electronic component device in which a semiconductor chip is packaged.

近年、電子機器の軽量化、薄型化に伴って、これに搭載される電子部品装置にも小型軽量化、薄型化が要求されている。従来、半導体パッケージに代表される電子部品装置は、リードフレームを用いて半導体チップの表面に形成された端子と外部端子とのワイヤーボンディングを行う方法により電子部品装置の製造が行われていた（特許文献１参照）。
特許第３０８７３９５号公報 In recent years, with the reduction in weight and thickness of electronic devices, the electronic component devices mounted thereon are also required to be reduced in size, weight, and thickness. Conventionally, an electronic component device represented by a semiconductor package has been manufactured by a method of wire bonding between a terminal formed on the surface of a semiconductor chip and an external terminal using a lead frame (patent) Reference 1).
Japanese Patent No. 3087395

リードフレームを用いる方法により製造された電子部品装置には、リードフレームが内包された状態となっているため、リードフレーム自体の有する重量や厚さの影響により軽量化、薄型化に限界があった。また、金属製のリードフレームの個片化工程（切断工程）にコストと時間を要していた。   The electronic component device manufactured by the method using the lead frame is in a state in which the lead frame is included, and thus there is a limit to reducing the weight and thickness due to the weight and thickness of the lead frame itself. . Moreover, cost and time are required for the individualization process (cutting process) of the metal lead frame.

そこで本発明は、軽量かつ薄型の電子部品装置を低コストで製造することができる電子部品装置の製造方法を提供することを目的とする。   Therefore, an object of the present invention is to provide a method of manufacturing an electronic component device that can manufacture a lightweight and thin electronic component device at low cost.

請求項１記載の発明は、半導体チップの表面に形成された端子に外部端子が電気的に接続された電子部品装置の製造方法であって、前記外部端子の形状および配列に対応したパターン孔を有するレジストパターンを金属板の表面に形成する工程と、前記金属板の表面に形成された前記パターン孔に前記外部端子を構成する電極膜を形成する工程と、前記電極膜を形成した後に、前記レジストパターンを前記金属板の表面から除去する工程と、前記半導体チップに形成された端子をバンプにより前記電極膜に電気的に接続する工程と、前記端子をバンプにより前記電極膜に電気的に接続した後に、前記電極膜を前記金属板の表面から剥離する工程と、を含む。   The invention according to claim 1 is a method of manufacturing an electronic component device in which an external terminal is electrically connected to a terminal formed on a surface of a semiconductor chip, and a pattern hole corresponding to the shape and arrangement of the external terminal is provided. Forming a resist pattern on the surface of the metal plate, forming an electrode film constituting the external terminal in the pattern hole formed on the surface of the metal plate, and after forming the electrode film, Removing the resist pattern from the surface of the metal plate; electrically connecting a terminal formed on the semiconductor chip to the electrode film by a bump; and electrically connecting the terminal to the electrode film by a bump. And then peeling the electrode film from the surface of the metal plate.

請求項２記載の発明は、半導体チップの表面に形成された端子に外部端子が電気的に接続された電子部品装置の製造方法であって、前記外部端子の形状および配列に対応したパターン孔を有するレジストパターンを金属板の表面に形成する工程と、前記金属板の表面に形成された前記パターン孔に前記外部端子を構成する電極膜を形成する工程と、前記電極膜を形成した後に、前記レジストパターンを前記金属板の表面から除去する工程と、前記レジストパターンを前記金属板の表面から除去した後に、前記金属板の表面および前記電極膜の表面にプラズマ処理を施す工程と、前記金属板の表面および前記電極膜の表面にプラズマ処理を施した後に、前記半導体チップに形成された端子をバンプにより前記電極膜に電気的に接続する工程と、少なくとも前記端子と前記電極膜との接続箇所を樹脂で封止する工程と、前記電極膜を前記金属板の表面から剥離する工程と、を含む。   The invention according to claim 2 is a method of manufacturing an electronic component device in which an external terminal is electrically connected to a terminal formed on a surface of a semiconductor chip, and a pattern hole corresponding to the shape and arrangement of the external terminal is provided. Forming a resist pattern on the surface of the metal plate, forming an electrode film constituting the external terminal in the pattern hole formed on the surface of the metal plate, and after forming the electrode film, Removing the resist pattern from the surface of the metal plate; removing the resist pattern from the surface of the metal plate; and performing plasma treatment on the surface of the metal plate and the surface of the electrode film; and Electrically connecting the terminals formed on the semiconductor chip to the electrode film by bumps after performing plasma treatment on the surface of the electrode film and the surface of the electrode film; Even without comprising the step of sealing with resin the connecting portion between the electrode layer and the terminal, a step of removing the electrode film from the surface of the metal plate, the.

請求項３記載の発明は、請求項２記載の発明において、前記半導体チップと前記電極膜を被覆する領域を樹脂で封止する工程をさらに含み、前記半導体チップと前記電極膜を被覆する領域を樹脂で封止した後に、前記電極膜および前記樹脂を前記金属板の表面から剥離する。   The invention according to claim 3 further includes a step of sealing the region covering the semiconductor chip and the electrode film with a resin in the invention according to claim 2, and further comprising a region covering the semiconductor chip and the electrode film. After sealing with resin, the electrode film and the resin are peeled off from the surface of the metal plate.

請求項４記載の発明は、請求項１乃至３の何れかに記載の発明において、前記金属板の表面に形成された前記パターン孔に前記外部端子を構成する電極膜を形成する工程が、前記金属板の表面に、Ｃｕ膜、Ｎｉ膜、Ａｕ膜の順にメッキを施すことにより行われる。   The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the step of forming an electrode film constituting the external terminal in the pattern hole formed on the surface of the metal plate comprises the step of: This is done by plating the surface of the metal plate in the order of the Cu film, Ni film, and Au film.

本発明によれば、半導体チップがパッケージされた電子部品装置の製造にリードフレームを必要としないので、軽量かつ薄型の電子部品装置を低コストで製造することができる。   According to the present invention, since a lead frame is not required for manufacturing an electronic component device packaged with a semiconductor chip, a lightweight and thin electronic component device can be manufactured at low cost.

本発明の実施の形態について図面を参照して説明する。図１は本発明の実施の形態の電子部品装置の構成を示す側断面図、図２および図３は本発明の実施の形態の電子部品装置の製造方法を工程順に示す説明図、図４は本発明の実施の形態の電子部品装置の製造方法におけるプラズマ処理方法を示す説明図である。   Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a side sectional view showing a configuration of an electronic component device according to an embodiment of the present invention, FIGS. 2 and 3 are explanatory views showing a method of manufacturing the electronic component device according to the embodiment of the present invention in order of steps, and FIG. It is explanatory drawing which shows the plasma processing method in the manufacturing method of the electronic component apparatus of embodiment of this invention.

最初に、本実施の形態における電子部品装置の構成について、図１を参照して説明する。図１において、電子部品装置１は、半導体チップ２の下面に形成された端子３にさらに端子４が電気的に接続された半導体パッケージである。端子３は、金や半田等により形成されたバンプ５を介して端子４と電気的に接続されており、接続箇所を樹脂６で封止することにより接合強度を向上させている。それ以外の領域も樹脂６で封止されており、電子部品装置１を衝撃等の外的阻害要因から保護している。端子４は、電子部品装置１を基板等に電気的に接続する際の外部端子として機能し、ここでは、接続用の半田バンプ８が端子４の下面に予め設けられている。端子４は、例えば、Ｃｕ膜４ａ、Ｎｉ膜４ｂ、Ａｕ膜４ｃを順に積層した電極膜として構成するのが望ましく、このように構成すると、半導体チップ２側はＡｕ、半田バンプ８側はＣｕとなり、半田バンプ８へのＡｕ溶出や、Ｎｉと半田バンプ８のＳｎとの合金化とそれに伴うＮｉに含有されるＰの界面析出による接合強度低下を防止することができる。また、半田とのなじみが良いＣｕ膜４ａが最下層にあるので、外装用の半田メッキ等の処理を要することなくＣｕ膜４ａに直接半田バンプ８を形成することが可能である。   Initially, the structure of the electronic component apparatus in this Embodiment is demonstrated with reference to FIG. In FIG. 1, an electronic component device 1 is a semiconductor package in which a terminal 4 is further electrically connected to a terminal 3 formed on the lower surface of a semiconductor chip 2. The terminal 3 is electrically connected to the terminal 4 via bumps 5 formed of gold, solder, or the like, and the bonding strength is improved by sealing the connection portion with the resin 6. Other areas are also sealed with resin 6 to protect electronic component device 1 from external obstruction factors such as impact. The terminal 4 functions as an external terminal when the electronic component device 1 is electrically connected to a substrate or the like. Here, a solder bump 8 for connection is provided in advance on the lower surface of the terminal 4. The terminal 4 is preferably configured as an electrode film in which, for example, a Cu film 4a, a Ni film 4b, and an Au film 4c are sequentially stacked. With this configuration, the semiconductor chip 2 side is Au and the solder bump 8 side is Cu. Further, it is possible to prevent the elution of Au from the solder bumps 8, the alloying of Ni and Sn of the solder bumps 8, and the accompanying decrease in bonding strength due to the interface precipitation of P contained in Ni. In addition, since the Cu film 4a that is compatible with the solder is in the lowermost layer, it is possible to form the solder bumps 8 directly on the Cu film 4a without requiring a solder plating process for exterior packaging.

次に、本実施の形態における電子部品装置の製造方法について、図２および図３を参照して工程順に説明する。   Next, a method for manufacturing the electronic component device according to the present embodiment will be described in the order of steps with reference to FIGS.

最初に、電子部品装置１の外部端子となる端子４を製造する。端子４は、レジストパターンにより所定のパターンで成形された多層の電極膜により形成される。レジストパターンは、金属板１０の上面にレジスト１１を塗布した後に（図２（ａ）参照）、端子４の形状および配列に対応するパターンでレジスト１１の一部を除去してパターン孔１２とすることにより形成される（図２（ｂ）参照）。パターン孔１２内において、金属板１０の表面にＣｕ膜、Ｎｉ膜、Ａｕ膜の順にメッキを施し、３層からなる電極膜１３を形成する（図２（ｃ）参照）。電極膜１３が固化したら、レジスト１１を除去して金属板１０の上面に電極膜１３を露出させる（図２（ｄ）参照）。以上の工程により、電子部品装置１の外部端子となる端子４が金属板１０上に形成される。   Initially, the terminal 4 used as the external terminal of the electronic component apparatus 1 is manufactured. The terminal 4 is formed of a multilayer electrode film formed in a predetermined pattern with a resist pattern. After the resist 11 is applied to the upper surface of the metal plate 10 (see FIG. 2A), a part of the resist 11 is removed in a pattern corresponding to the shape and arrangement of the terminals 4 to form pattern holes 12. (See FIG. 2B). In the pattern hole 12, the surface of the metal plate 10 is plated in the order of the Cu film, the Ni film, and the Au film to form an electrode film 13 composed of three layers (see FIG. 2C). When the electrode film 13 is solidified, the resist 11 is removed to expose the electrode film 13 on the upper surface of the metal plate 10 (see FIG. 2D). Through the steps described above, the terminal 4 serving as the external terminal of the electronic component device 1 is formed on the metal plate 10.

金属板１０の材質としては種々のものを使用することができるが、例えば銅やステンレス等の金属で厚さが０．２ｍｍ程度の比較的剛性の低い板材を使用すると、後の工程において端子４を金属板１０から剥離する際に、金属板１０を撓ませることで容易に剥離することができる。また、レジスト１１の除去は、アルコール等の有機溶剤により溶解させる方法や、酸素プラズマでレジストを分解して灰化するアッシング等を用いて行う。   Various materials can be used as the material of the metal plate 10. For example, when a plate material having a relatively low rigidity and having a thickness of about 0.2 mm made of metal such as copper or stainless steel is used, the terminal 4 is used in a later process. Can be easily peeled by bending the metal plate 10. The resist 11 is removed by a method of dissolving with an organic solvent such as alcohol, or ashing that decomposes the resist with oxygen plasma and ashes it.

次に、金属板１０の上面および電極膜１３の上面にプラズマ処理を施す（図２（ｅ）参
照）。プラズマ処理は対象面の不純物除去と改質を目的として施され、図４に示すようにプラズマ発生用ガスを充満させた雰囲気内に金属板１０および電極膜１３を配置し、高周波電圧を印加することにより行われる。プラズマ処理により金属板１０の上面の酸化膜が除去され、後の工程において樹脂を剥離する際の剥離性が向上する。また、電極膜１３の最上層にあるＡｕ膜の有機汚染物が除去され、後の工程において半導体チップ２のバンプ５を接合する際の接合性が向上する。 Next, plasma treatment is performed on the upper surface of the metal plate 10 and the upper surface of the electrode film 13 (see FIG. 2E). The plasma treatment is performed for the purpose of removing impurities and modifying the target surface. As shown in FIG. 4, the metal plate 10 and the electrode film 13 are arranged in an atmosphere filled with a plasma generating gas, and a high frequency voltage is applied. Is done. The oxide film on the upper surface of the metal plate 10 is removed by the plasma treatment, and the releasability when the resin is peeled off in the subsequent process is improved. Further, organic contaminants of the Au film on the uppermost layer of the electrode film 13 are removed, and the bonding property when bonding the bumps 5 of the semiconductor chip 2 in the subsequent process is improved.

次に、電極膜１３に半導体チップ２を搭載する（図３（ａ）参照）。半導体チップ２は、下面に形成された端子３を電極膜１３の上面に電気的に接続させた状態で搭載される。端子３と電極膜１３の接続には例えば金で形成されたバンプ５が用いられ、保持ノズル７により電極膜１３に搭載された半導体チップ２に荷重と超音波振動を印加することにより端子３と電極膜１３が接続される。電極膜１３は、樹脂等と比較して剛性の高い金属板１０上に形成されているので、保持ノズル７により印加される荷重と超音波振動のロスが少なく効率的に接続することができる。   Next, the semiconductor chip 2 is mounted on the electrode film 13 (see FIG. 3A). The semiconductor chip 2 is mounted in a state in which the terminals 3 formed on the lower surface are electrically connected to the upper surface of the electrode film 13. For the connection between the terminal 3 and the electrode film 13, for example, bumps 5 made of gold are used. By applying a load and ultrasonic vibration to the semiconductor chip 2 mounted on the electrode film 13 by the holding nozzle 7, the terminal 3 and the electrode film 13 are connected. The electrode film 13 is connected. Since the electrode film 13 is formed on the metal plate 10 having higher rigidity than that of resin or the like, the load applied by the holding nozzle 7 and the loss of ultrasonic vibration can be reduced and the electrodes can be efficiently connected.

次に、端子３と電極膜１３の接続箇所および半導体チップ２と電極膜１３を被覆する領域を樹脂６で封止する（図３（ｂ）参照）。なお、電極膜１３に半導体チップ２を搭載する前段階で、電極膜１３と半導体チップ２の間を充填する樹脂６を予め供給しておくこともできる。   Next, the connection portion between the terminal 3 and the electrode film 13 and the region covering the semiconductor chip 2 and the electrode film 13 are sealed with the resin 6 (see FIG. 3B). Note that the resin 6 filling the space between the electrode film 13 and the semiconductor chip 2 can be supplied in advance before the semiconductor chip 2 is mounted on the electrode film 13.

次に、電極膜１３と樹脂６を金属板１０から剥離し（図３（ｃ）参照）、電極膜１３と樹脂６が金属板１０から完全に剥離されると、電子部品装置１の製造が終了する。電子部品装置１の下面には、電極膜１３の最下層にあるＣｕ膜が露出し、電子部品装置１を基板等に電気的に接続する際の外部端子の接続面として機能する。なお、電子部品装置１を基板等に実装する際の便宜を考慮して、Ｃｕ膜に予め半田バンプ８を設けてもよい（図３（ｅ）参照）。   Next, the electrode film 13 and the resin 6 are peeled from the metal plate 10 (see FIG. 3C), and when the electrode film 13 and the resin 6 are completely peeled from the metal plate 10, the electronic component device 1 is manufactured. finish. The Cu film in the lowermost layer of the electrode film 13 is exposed on the lower surface of the electronic component device 1, and functions as a connection surface for external terminals when the electronic component device 1 is electrically connected to a substrate or the like. In consideration of convenience when mounting the electronic component device 1 on a substrate or the like, solder bumps 8 may be provided in advance on the Cu film (see FIG. 3E).

以上の工程による電子部品装置の製造方法によれば、パッケージの内部における端子３と端子４（電極膜１３）の接続にバンプ５を介在させているだけなので、従来のリードフレームを用いてワイヤーボンディングを行う製造方法に比べ、薄く、かつ軽量な電子部品装置を製造することが可能である。これにより、軽量化、薄型化が要求される電子機器に搭載可能な電子部品装置を製造することができる。また、金属製のリードフレームの個片化工程（切断工程）を必要としないので、コストの低減および製造に要する時間の短縮が可能になる。   According to the manufacturing method of the electronic component device according to the above steps, the bumps 5 are merely interposed between the terminals 3 and 4 (electrode film 13) inside the package, so that the conventional lead frame is used for wire bonding. Compared with the manufacturing method which performs this, it is possible to manufacture a thin and lightweight electronic component device. Thereby, the electronic component apparatus which can be mounted in the electronic device in which weight reduction and thickness reduction are requested | required can be manufactured. Further, since a metal lead frame singulation process (cutting process) is not required, the cost can be reduced and the time required for manufacturing can be shortened.

なお、上述した製造方法の各工程のうち、樹脂６で封止する工程、プラズマ処理を施す工程は、電子部品装置１の強度や電気的な信頼性の向上のために施されるものであるため、電子部品装置１に要求される品質に応じて省略することも可能である。   Of the steps of the manufacturing method described above, the step of sealing with the resin 6 and the step of performing the plasma treatment are performed for improving the strength and electrical reliability of the electronic component device 1. Therefore, it can be omitted according to the quality required for the electronic component device 1.

本発明によれば、軽量かつ薄型の電子部品装置を低コストで製造することができるので、半導体チップがパッケージされた電子部品装置の製造分野において有用である。   According to the present invention, a lightweight and thin electronic component device can be manufactured at low cost, which is useful in the field of manufacturing an electronic component device packaged with a semiconductor chip.

本発明の実施の形態の電子部品装置の構成を示す側断面図1 is a side sectional view showing a configuration of an electronic component device according to an embodiment of the present invention. 本発明の実施の形態の電子部品装置の製造方法を工程順に示す説明図Explanatory drawing which shows the manufacturing method of the electronic component apparatus of embodiment of this invention in order of a process 本発明の実施の形態の電子部品装置の製造方法を工程順に示す説明図Explanatory drawing which shows the manufacturing method of the electronic component apparatus of embodiment of this invention in order of a process 本発明の実施の形態の電子部品装置の製造方法におけるプラズマ処理方法を示す説明図Explanatory drawing which shows the plasma processing method in the manufacturing method of the electronic component apparatus of embodiment of this invention

符号の説明Explanation of symbols

１ 電子部品装置
２ 半導体チップ
３ 端子
４ 端子（外部端子）
５ 半田バンプ
６ 樹脂
１０ 金属板
１１ レジスト
１２ パターン孔
１３ 電極膜 1 Electronic component device 2 Semiconductor chip 3 Terminal 4 Terminal (external terminal)
5 Solder bump 6 Resin 10 Metal plate 11 Resist 12 Pattern hole 13 Electrode film

Claims (4)

半導体チップの表面に形成された端子に外部端子が電気的に接続された電子部品装置の製造方法であって、
前記外部端子の形状および配列に対応したパターン孔を有するレジストパターンを金属板の表面に形成する工程と、
前記金属板の表面に形成された前記パターン孔に前記外部端子を構成する電極膜を形成する工程と、
前記電極膜を形成した後に、前記レジストパターンを前記金属板の表面から除去する工程と、
前記半導体チップに形成された端子をバンプにより前記電極膜に電気的に接続する工程と、
前記端子をバンプにより前記電極膜に電気的に接続した後に、前記電極膜を前記金属板の表面から剥離する工程と、
を含む電子部品装置の製造方法。 A method of manufacturing an electronic component device in which external terminals are electrically connected to terminals formed on a surface of a semiconductor chip,
Forming a resist pattern having a pattern hole corresponding to the shape and arrangement of the external terminals on the surface of the metal plate;
Forming an electrode film constituting the external terminal in the pattern hole formed on the surface of the metal plate;
Removing the resist pattern from the surface of the metal plate after forming the electrode film;
Electrically connecting terminals formed on the semiconductor chip to the electrode film by bumps;
After electrically connecting the terminal to the electrode film by a bump, peeling the electrode film from the surface of the metal plate;
A method for manufacturing an electronic component device including: 半導体チップの表面に形成された端子に外部端子が電気的に接続された電子部品装置の製造方法であって、
前記外部端子の形状および配列に対応したパターン孔を有するレジストパターンを金属板の表面に形成する工程と、
前記金属板の表面に形成された前記パターン孔に前記外部端子を構成する電極膜を形成する工程と、
前記電極膜を形成した後に、前記レジストパターンを前記金属板の表面から除去する工程と、
前記レジストパターンを前記金属板の表面から除去した後に、前記金属板の表面および前記電極膜の表面にプラズマ処理を施す工程と、
前記金属板の表面および前記電極膜の表面にプラズマ処理を施した後に、前記半導体チップに形成された端子をバンプにより前記電極膜に電気的に接続する工程と、
少なくとも前記端子と前記電極膜との接続箇所を樹脂で封止する工程と、
前記電極膜を前記金属板の表面から剥離する工程と、
を含む電子部品装置の製造方法。 A method of manufacturing an electronic component device in which external terminals are electrically connected to terminals formed on a surface of a semiconductor chip,
Forming a resist pattern having a pattern hole corresponding to the shape and arrangement of the external terminals on the surface of the metal plate;
Forming an electrode film constituting the external terminal in the pattern hole formed on the surface of the metal plate;
Removing the resist pattern from the surface of the metal plate after forming the electrode film;
Applying plasma treatment to the surface of the metal plate and the surface of the electrode film after removing the resist pattern from the surface of the metal plate;
Electrically connecting the terminals formed on the semiconductor chip to the electrode film by bumps after performing plasma treatment on the surface of the metal plate and the surface of the electrode film;
Sealing at least a connection portion between the terminal and the electrode film with a resin;
Peeling the electrode film from the surface of the metal plate;
A method for manufacturing an electronic component device including: 前記半導体チップと前記電極膜を被覆する領域を樹脂で封止する工程をさらに含み、前記半導体チップと前記電極膜を被覆する領域を樹脂で封止した後に、前記電極膜および前記樹脂を前記金属板の表面から剥離する請求項２記載の電子部品装置の製造方法。   The method further includes sealing a region covering the semiconductor chip and the electrode film with a resin, and sealing the region covering the semiconductor chip and the electrode film with a resin, and then bonding the electrode film and the resin to the metal The manufacturing method of the electronic component apparatus of Claim 2 which peels from the surface of a board. 前記金属板の表面に形成された前記パターン孔に前記外部端子を構成する電極膜を形成する工程が、前記金属板の表面に、Ｃｕ膜、Ｎｉ膜、Ａｕ膜の順にメッキを施すことにより行われる請求項１乃至３の何れかに記載の電子部品装置の製造方法。   The step of forming an electrode film constituting the external terminal in the pattern hole formed on the surface of the metal plate is performed by plating the surface of the metal plate in the order of a Cu film, a Ni film, and an Au film. A method for manufacturing an electronic component device according to any one of claims 1 to 3.
JP2006072349A 2006-03-16 2006-03-16 Manufacturing method of electronic component device Pending JP2007250834A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008084959A (en) * 2006-09-26 2008-04-10 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008084959A (en) * 2006-09-26 2008-04-10 Shinko Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US8211754B2 (en) 2006-09-26 2012-07-03 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method thereof

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