JP2007141974A - Diamond semiconductor element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor element which assures excellent voltage resistance, heat resistance, radioactive ray resistance, and a high operation velocity, enables reduction in channel region, and ensures the high-precision manufacturing of a diamond semiconductor element ensuring a higher response characteristic of an element. <P>SOLUTION: On the front surface of a first diamond semiconductor region 1; an insulating film 2, an electrode metal layer 3, and a sacrifice layer 4 are laminated, and a resist 5 is patter-formed in a local area on the sacrifice layer 4. After etching the first sacrifice layer, the electrode metal layer and the insulating film using the resist 5 as a mask, the resist 5 is removed to form a pattern of the laminated material of the insulating film 2, the electrode metal layer 3, and the first sacrifice layer 4 on the first diamond semiconductor region 1. Thereafter, on the first diamond semiconductor region 1, a high concentration doped layer 7 (comprising the second and third diamond semiconductor regions) is formed by doping an impurity. Subsequently, the sacrifice layer 4 is removed by etching to form an electrode metal 8 on the high-concentration doped layer 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a diamond semiconductor element such as a field effect transistor using a diamond thin film.

Diamond has its thermal conductivity (20 W / cm · K), band gap (5.47 eV), saturated electron and hole mobility (electrons: 2000 cm ² / V · s, holes: 2100 cm ² / V · s), etc. Since the device characteristics are excellent, it is expected to be applied to electronic devices, high power devices, high frequency devices and the like that operate at high temperatures and radiation.

  As a structure of a field effect transistor (FET) using a diamond thin film, a MISFET in which an insulating layer is inserted between a gate electrode and an operation layer, that is, a channel layer has been proposed (Patent Document 1). The MISFET described in Patent Document 1 is a normally-on type. That is, the drain current is suppressed by making the gate potential positive with respect to the source potential. In order to greatly change the drain current with a small gate potential input, that is, to increase the transconductance, it is necessary to extend the depletion region of the carrier by influencing the gate potential to a deep region in the channel. There is. For this purpose, the donor or acceptor concentration must be kept low to some extent, and the thickness of the channel layer must be reduced within a range affected by the gate potential. On the other hand, in order to ensure the drain current, there is a conflicting requirement that the concentration of the donor or acceptor impurity must be increased and the carrier concentration must be increased.

  Also in Patent Document 2, as shown in FIG. 15 of Patent Document 2, a field effect transistor having a metal / insulating diamond / semiconductor diamond structure in a gate portion is proposed. The insulating diamond in Patent Document 2 plays a role of insulating between a semiconductor diamond layer which is a channel layer and a gate metal. The operation mechanism of the transistor is almost the same as that of Patent Document 1.

  The high mobility inherent in diamond is first manifested with minimal impurities and crystal defects. However, in a structure in which a donor or acceptor needs to be doped at a certain concentration in order to secure a channel layer carrier source as in the above-described conventional MISFET, the carrier mobility decreases as the impurity concentration increases. Therefore, it is inevitable that the high-frequency response is deteriorated.

  On the other hand, a field effect transistor having a structure using a high-resistance diamond layer as a channel layer is disclosed as a structure that can be applied to a high-frequency transistor by suppressing the impurity concentration of the channel layer as much as possible (Patent Document 3). ). That is, in Patent Document 3, the first semiconductor diamond layer 1 in contact with the source electrode 4 and the second semiconductor diamond layer 3 in contact with the drain battery 6 and having the same conductivity type as the first semiconductor diamond layer 1 are disclosed. And a high-resistance diamond layer 2 is provided between the first and second semiconductor diamond layers 1 and 3, and a field effect transistor that receives the action of the gate electrode 5 is disclosed. The specific resistance of the high and low anti-diamond layer 2 is 100 Ω · cm or more.

  In this transistor, as shown in FIG. 1 of Patent Document 3, carriers that reach the drain electrode 6 from the source electrode 4 flow in the semiconductor diamond layer 1, the high-resistance diamond layer 2, and the semiconductor diamond layer 3 in this order. . Then, by changing the voltage VG applied to the gate electrode 5, the potential of the high and low anti-diamond layer 2 is changed, and the amount of carriers injected from the semiconductor diamond layer 1 in contact with the source electrode 4 to the high resistance diamond layer 2 is changed. It comes to control. Therefore, unlike the MISFET or the like, since there is no mechanism for controlling the drain current by expanding the depletion layer in the channel layer 7, it is not necessary to form a thin diamond channel layer with a low doping concentration.

  The above conventional semiconductor elements are based on the structure of a field effect transistor. That is, a source electrode and a drain electrode are provided with a channel region interposed therebetween, and a gate electrode is provided in contact with the channel region. Since the contact resistance between the metal source and drain electrodes and the channel region causes power loss, it is generally performed to form an ohmic junction by providing a highly doped semiconductor in the contact region. On the other hand, if there is a leakage current between the channel and the gate electrode, it causes a decrease in performance such as a decrease in amplification factor. In order to prevent this, it is common to insert an insulating layer or form a Schottky junction interface between the channel and the gate electrode.

  In Patent Document 4, a semiconductor diamond layer serving as a source / drain is formed on an insulating diamond single crystal substrate, and a low-concentration B-doped p-type semiconductor diamond thin film serving as a channel layer is formed on these layers. A method of manufacturing a semiconductor device is disclosed in which an insulating film is formed on a gate electrode and then a gate electrode is formed between the source and drain.

  Further, in Patent Document 5, a mask material layer for selective growth in the shape of a source / drain electrode is formed on a first diamond layer, and the second diamond layer is formed so as to be wider at the end of growth than at the beginning of growth. Thereafter, a method is described in which the mask material layer is removed to form a source electrode, a drain electrode, and a gate electrode.

  Furthermore, in Patent Document 6, a diamond layer containing a p-type dopant is formed on a substrate. In a semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on the diamond layer, A semiconductor device is disclosed in which an intervening region containing an n-type dopant is provided in a surface region in contact with the gate electrode.

Japanese Patent Laid-Open No. 1-158774 JP-A-3-263872 JP-A-6-232388 JP 2002-57167 A (FIG. 2) Japanese Patent Laid-Open No. 5-29609 (FIG. 1) Japanese Patent No. 3269510 (FIGS. 1, 3, 5, and 6)

  By the way, in order to improve the performance of the field effect transistor, it is necessary to shorten the channel region. As a performance index of a transistor, there is an amount of flowing current. In order to realize a transistor having high performance, it is required to obtain a higher amount of current. Since the amount of current is the number of charges flowing per unit time, in order to obtain a high amount of current, it is effective to shorten the region where charges flow, that is, the channel region as much as possible.

  However, as the channel region is shortened, the demand for processing accuracy becomes more severe. An element such as a field effect transistor is manufactured through a plurality of processes such as film formation and etching. Elements are formed by processing a pattern of a necessary shape for each of these steps and aligning (aligning) the pattern positions with each other. Therefore, not only the improvement of the processing accuracy of a single process but also the control of the alignment accuracy between each process is an important point.

  In order to overcome this alignment processing accuracy, a method of forming the gate electrode, the source electrode, the drain electrode, and the like of the field effect transistor in a self-aligned manner is used in the silicon semiconductor. That is, after forming the gate electrode, it is possible to form a source electrode and a drain electrode aligned with the gate electrode by performing high concentration doping by ion implantation using this as a mask.

  However, in the case of diamond, this method cannot be applied as it is. That is, when impurity ions are implanted into diamond in order to obtain a highly doped layer, the crystal structure of the implanted region is destroyed and the region changes from diamond to graphite. This cannot be recovered by the subsequent heat treatment step or the like. Therefore, it is impossible to apply a process such as silicon semiconductor to semiconductor diamond as it is.

  Further, in the semiconductor element described in Patent Document 4, it is difficult to reduce the distance between the gate and the source / drain.

  In the semiconductor element described in Patent Document 5, the deposited metal also flows under the eaves diamond layer, and it is difficult to control the distance between the gate and the source / drain.

Furthermore, in the semiconductor element described in Patent Document 6, since a diamond layer doped with an impurity in the channel region is used, carrier mobility cannot be increased. Further, ion implantation and irradiation with NH ₃ plasma are performed to dope impurities, but this method has a problem of damage to the diamond layer. Although there is a tendency of improving the damage by performing the heat treatment after the ion implantation, once the crystal structure is destroyed by the ion implantation, it cannot be substantially recovered. In addition, although the intervening region can be formed by self-alignment with respect to the source / drain, since the gate electrode is formed after that, it is difficult to align the gap between the gate and the source / drain with high accuracy.

  The present invention has been made in view of such problems, and by forming a gate electrode in a self-aligned manner (self-aligned), the processing accuracy is improved and a semiconductor element such as a diamond field effect transistor having high performance is obtained. In addition, a semiconductor capable of producing a diamond semiconductor device with high accuracy with excellent voltage resistance, heat resistance, radiation resistance, and high speed, a short channel region, and high device responsiveness. An object is to provide a method for manufacturing an element.

  The method for manufacturing a diamond semiconductor device according to the present invention includes a step of laminating an insulating film and an electrode metal layer on the surface of the first diamond semiconductor region, and further laminating a first sacrificial layer, Patterning a resist locally at a desired position on the surface of one sacrificial layer, and etching the first sacrificial layer, the electrode metal layer, and the insulating film using the resist as a mask, Removing the resist, patterning a laminate of an insulating film, an electrode metal layer, and a first sacrificial layer on the surface of the first diamond semiconductor region; and the first diamond semiconductor region Forming a second and third diamond semiconductor region doped with a dopant on the surface, removing the first sacrificial layer by etching, and second and And forming an electrode metal on the surface of the third diamond semiconductor region, and having a.

  In the method for manufacturing a diamond semiconductor element, the second and third diamond semiconductor regions can be formed by a microwave CVD method at a temperature of 600 ° C. or lower.

  In this case, the second sacrificial layer is formed on the entire surface and etched back between the step of patterning the stacked body and the step of forming the second and third diamond semiconductor regions. A step of leaving the second sacrificial layer on the side surface of the laminate, and a lift-off step of removing the sacrificial layer and the second sacrificial layer after forming a highly doped layer on the entire surface, The second and third diamond semiconductor regions can be formed on the first diamond semiconductor region.

  Alternatively, a buffer layer including a semiconductor element layer containing at least a semiconductor element is stacked between the insulating film and the electrode metal layer, and the second and third diamond semiconductor regions have a temperature exceeding 600 ° C. and 1200 ° C. It can be formed by a microwave CVD method at a temperature of ℃ or lower. In this case, the buffer layer has, for example, a two-layer structure of the semiconductor element layer and the oxide layer of the semiconductor element, and the electrode metal layer and the semiconductor element layer are heated when heated at the temperature. It reacts. Also, for example, the semiconductor element is silicon or germanium, and the electrode metal layer is Au, Ag, Cu, W, Ti, Mo, Ni, Ta, Nb, Pt, Ce, Co, Cr, Dy, Fe, It is formed of at least one selected from the group consisting of Gd, Hf, Mn, Nd, Pd, Pr, Ru, Sr, Tb, V, Y, and Zr. In addition, the semiconductor element layer is a concept including a semiconductor layer and a metal element doped with a large amount of impurities. Therefore, the semiconductor element layer is distinguished from the semiconductor layer in this respect.

  In these methods for manufacturing a diamond semiconductor element, the method includes a step of forming a second sacrificial layer on both side surfaces of the stacked body before the step of forming the second and third diamond semiconductor regions. A step of removing the second sacrificial layer by etching may be included after the step of forming the second and third diamond semiconductor regions.

  In these methods for manufacturing a diamond semiconductor element, after patterning the laminate, the surface of the first diamond semiconductor region can be dug by further etching the surface of the first diamond semiconductor region.

  In addition, after the stacked body is formed, a step of forming a second insulating film on a side surface of the stacked body can be provided.

  The diamond semiconductor element according to the present invention is locally formed on a first diamond semiconductor region, and includes a laminate including a lower insulating film and an upper electrode metal layer, and the first diamond semiconductor region, It has the 2nd and 3rd diamond semiconductor area | region provided adjacent to the both sides of the laminated body, and the electrode each formed on the 2nd and 3rd diamond semiconductor area | region, It is characterized by the above-mentioned.

  In this diamond semiconductor element, the second diamond semiconductor region and the third diamond semiconductor region may be in contact with each other or may not be in contact. However, when both are in contact with each other, the second diamond semiconductor region and the third diamond semiconductor region are not in contact with the electrode of the stacked body and are in contact with only the insulating portion.

  In the diamond semiconductor element, the second and third diamond semiconductor regions are preferably made of microcrystalline diamond having a diamond grain size of 1 to 100 nm.

  Alternatively, in the diamond semiconductor element, a buffer layer is preferably disposed between the insulating film and the electrode metal layer, and the buffer layer preferably includes a semiconductor element layer containing at least a semiconductor element.

  In these diamond semiconductor elements, the second and third diamond semiconductor regions are preferably more highly doped than the first diamond semiconductor region.

  Furthermore, it is preferable that a second insulating film is formed on both side surfaces of the laminate.

  Furthermore, the second and third diamond semiconductor regions and the insulating film of the stacked body are disposed on the same plane as the first diamond semiconductor region, and the thickness of the insulating film is the first thickness. The thickness is preferably larger than the thicknesses of the second and third diamond semiconductor regions.

  Furthermore, it is preferable that the length (width) of the stacked body serving as a channel region is 100 m or more and 1 μm or less.

  The insulating film is made of, for example, one or more materials selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, metal fluorides, and nitrogen-doped diamond. Further, when the insulating film and the second and third diamond semiconductor regions are on the same plane, the thickness of each insulating film is larger than the thickness of the second and third diamond semiconductor regions. Thickness is preferred.

  According to the present invention, since the withstand voltage, heat resistance, radiation resistance, and high speed are excellent and the channel region can be shortened, a diamond semiconductor element with high element responsiveness and a method for manufacturing the same are manufactured with high accuracy. be able to. Further, in the present invention, diamond is used in the channel region, so that it has a higher withstand voltage than nitride semiconductors such as SiC and GaN, and since diamond has the highest thermal conductivity in the material, Use with voltage and high power is possible. Therefore, even when the channel size is shortened and the electric field is high, the material itself is not broken down. As a result, there are many advantages such as a high-speed response, a reduction in on-resistance, a reduction in off-state leakage current, high reverse voltage tolerance, and cost reduction due to a reduction in device size.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. 1A to 1J are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. FIG. 1A shows a first diamond semiconductor region 1 as a channel layer. The first diamond semiconductor region 1 is non-doped or doped at a lower concentration than the second and third diamond regions. As shown in FIG. 1B, an insulating film 2 is formed on the first diamond semiconductor region 1, a gate electrode layer (electrode metal layer) 3 is formed on the insulating film 2, and A sacrificial layer 4 is formed on the gate electrode layer 3. Thereafter, as shown in FIG. 1C, a resist 5 is formed on the sacrificial layer 4 in an electrode pattern. Next, as shown in FIG. 1D, the sacrificial layer 4, the gate electrode layer 3 and the insulating film 2 are etched using the pattern of the resist 5 as a mask. Thereby, a laminated body of electrode patterns composed of the sacrificial layer 4, the gate electrode layer 3 and the insulating film 2 is formed. Then, when the resist 5 is removed, an electrode pattern laminate including the sacrificial layer 4, the gate electrode layer 3 and the insulating film 2 is formed on the first diamond semiconductor region 1.

  Next, as shown in FIG. 1F, a second sacrificial layer 6 is deposited on the entire surface. As a result, the second sacrificial layer 6 is formed on the surface of the first semiconductor region 1, the side surface of the stacked body, and the surface of the stacked body. Thereafter, as shown in FIG. 1G, the second sacrificial layer 6 is left only on the side surface of the stacked body by etching back. Next, as shown in FIG. 1H, a high-concentration doped layer 7 to be the second and third diamond semiconductor regions is formed on the entire surface. That is, the highly doped layer 7 is a diamond film doped with impurities at a high concentration. Thereby, the highly doped layer 7 is formed on the surface of the first diamond semiconductor layer 1, on the second sacrificial layer 6 on the side surface of the stacked body, and on the surface of the stacked body. Thereafter, the sacrificial layer 4 and the second sacrificial layer 6 are dissolved and removed, and the highly doped layer 7 on the side surface of the stacked body and the surface of the stacked body is removed by a lift-off method. As a result, a heavily doped layer 7 separated from the stacked body by the thickness of the second sacrificial layer 6 is formed in the vicinity of the stacked body on the surface of the first diamond semiconductor region 1. Thereafter, as shown in FIG. 1 (j), a metal electrode 8 is formed on each highly doped layer 7.

  In the semiconductor element formed in this way, the pair of electrodes 8 serves as a source electrode and a drain electrode, and the current applied to the electrode 8 is supplied from the electrode 8 through the heavily doped layer 7 to the first diamond semiconductor region. 1 enters the channel layer constituted by 1, passes through the opposite high-concentration doped layer 7, and exits to the opposite electrode 8. The current flowing through the channel layer is controlled by the voltage applied to the gate electrode layer 3.

  In this case, the length of the channel region of the laminate, that is, the length (width) of the laminate in the direction connecting the highly doped layers 7 is 10 nm to 1 μm, preferably 20 nm to 0.5 μm. . The high-concentration doped layer 7 is only separated from the side surface of the stacked body by the thickness of the second sacrificial layer 6, and is very close. Therefore, in this embodiment, the length of the channel region can be extremely shortened. When the length of the channel region is short, the time during which electrons flow is short, and the responsiveness of the element is increased.

  The thickness of the insulating film 2 is preferably 1 to 100 nm. The thinner the insulating film 2, the higher the switching performance of the device, and the thicker the insulating film 2 is preferable in terms of gate insulation. Therefore, the thickness of the insulating film 2 is preferably 1 to 100 nm from the viewpoint of switching performance and gate insulation. The thickness of the gate electrode layer 3 is preferably 50 nm to 1 μm. When the thickness of the gate electrode layer 3 is less than 50 nm, the electrical resistance becomes too high, and when the thickness of the gate electrode layer 3 exceeds 1 μm, the workability deteriorates. Furthermore, the thickness of the sacrificial layer 4 is preferably 50 to 500 nm. If the thickness of the sacrificial layer 4 is less than 50 nm, it is not suitable as a mask for forming a diamond film. On the other hand, when the thickness of the sacrificial layer 4 exceeds 500 nm, the sacrificial layer 4 becomes too thick and the workability deteriorates.

  As described above, in the present embodiment, the heavily doped layer 7 is provided close to the stacked body by being separated by the thickness of the second sacrificial layer 6, so that it does not contact the gate electrode layer 3. In this state, since it can be provided very close to the stacked body, a channel region through which charges flow can be reduced.

  By making the highly doped layer 7 as the second and third semiconductor regions into a semiconductor element that is a diamond semiconductor doped more heavily than the first diamond semiconductor region 1, the second or third semiconductor A high-density charge can be injected from the region into the first semiconductor region. In addition, since the first semiconductor region 1 can be used that has few defects and impurities that hinder charge transfer, the charge transfer speed of the first semiconductor region can be increased and the device performance can be improved. Can be.

  The insulating film 2 is preferably selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, metal fluorides, and nitrogen-doped diamond from the standpoint of insulation performance. Examples of the metal used for the metal oxide, metal nitride, and metal oxynitride include silicon, aluminum, magnesium, titanium, zirconium, hafnium, scandium, yttrium, lanthanum, vanadium, niobium, and tantalum. Of these, silicon, aluminum, hafnium, and zirconium are preferable. These metals may be used alone as a metal oxide, metal nitride, or metal oxynitride, or may be a metal oxide, metal nitride, or metal oxynitride composed of two or more metals. Examples of the metal used for the metal fluoride include calcium, barium, magnesium, and strontium. Nitrogen-doped diamond has a deep level due to nitrogen and has high resistance.

  Since the first to third diamond semiconductor regions are formed of diamond, a semiconductor element excellent in high withstand voltage, heat resistance, radiation resistance, high speed and the like can be obtained.

  In addition, as shown in FIG. 1 (j), when the insulating film 2 and the second and third semiconductor regions (highly doped layers 7) are on the same surface of the diamond semiconductor region 1 and on the same plane, Further, by making the thickness of the insulating film 2 thicker than that of the second and third semiconductor regions (the heavily doped layer 7), it is possible to more effectively prevent undesirable contact with the gate electrode layer 3. be able to.

  By forming the high-concentration doped layers 7 in the second and third semiconductor regions at a temperature of 700 ° C. or lower, the insulating film / electrode metal laminate is prevented from being peeled off or damaged due to thermal expansion or the like. be able to. More preferably, it is 600 degrees C or less. Moreover, as a temperature minimum, formation at 200 degreeC or more is more preferable. This is because formation of diamond becomes difficult when the temperature is lower than 200 ° C.

  It is effective to use microcrystalline diamond for the second and third semiconductor regions. This is because it can be easily formed at a low temperature of 600 ° C. or lower. Further, by using microcrystalline diamond, it is possible to obtain both high-concentration N-type and P-type semiconductor characteristics. This makes it possible to form a complementary metal oxide semiconductor (CMOS) type transistor.

  The grain size of microcrystalline diamond is preferably 1 nm to 100 nm. When trying to obtain a particle diameter of 1 nm or less, the diamond characteristics are not exhibited. Further, when the diamond particle diameter is 100 nm or more, it causes a deviation of element dimensions.

  By forming the second and third semiconductor regions after forming the insulating film / electrode metal stack, the second and third semiconductor regions are self-aligned with the insulating film / electrode metal stack. The position can be determined.

  The second and third semiconductor regions are formed after forming the stacked body having the sacrificial layer on the upper surface and the side surface of the insulating film / electrode metal stacked body. 3 semiconductor regions can be removed by post-processing lines. Any sacrificial layer may be used as long as it can be selectively removed by etching with the insulating film and the electrode metal.

  That is, the insulating material other than the insulating film for the element can be an insulating material such as the metal oxide, metal nitride, metal oxynitride, or metal fluoride. Metals other than the electrode metal of the element can also be used.

  2A to 2J are cross-sectional views showing a method of manufacturing a diamond semiconductor device according to the second embodiment of the present invention in the order of steps. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is different from the embodiment shown in FIG. 1 in that, in the step shown in FIG. 2D, the stacked body of the sacrificial layer 4, the gate electrode layer 3 and the insulating film 2 is etched using the resist 5 as a mask. Further, even after the stacked body is removed, the etching is continued to slightly excavate the surface of the diamond semiconductor region 1.

  As a result, as shown in FIG. 2 (j), the obtained semiconductor element has a surface of the diamond semiconductor region 1 on which the heavily doped layer 7 is formed and a surface of the diamond semiconductor region 1 on which the insulating film 2 is formed. Therefore, contact between the heavily doped layer 7 and the gate electrode layer 3 can be reliably prevented.

  3A to 3J are cross-sectional views showing a method of manufacturing a diamond semiconductor device according to the third embodiment of the present invention in the order of steps. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is different from the embodiment shown in FIG. 1 in that the second insulating film 9 shown in FIG. As shown in FIG. 3 (e), after the laminated body (insulating film 2, gate electrode layer 3 and sacrificial layer 4) is patterned, the second insulating film 9 is formed on the entire surface as shown in FIG. 3 (f). Further, a second sacrificial layer 6 is formed on the second insulating film 9. After that, as shown in FIG. 3G, the second insulating film 9 and the second sacrificial layer 6 are etched back, and the second insulating film 9 and the second sacrificial film are formed only on the side surface of the stacked body. Leave layer 6. Thereafter, as shown in FIG. 3H, a highly doped layer 7 is formed on the entire surface. Next, as shown in FIG. 3I, the sacrificial layer 4 and the second sacrificial layer 6 are dissolved, and the heavily doped layer 7 on the sacrificial layer 4 and the second sacrificial layer 6 is formed by a lift-off method. When removed, a structure in which the second insulating film 9 covers the side surface of the stacked body is formed. Thereafter, as shown in FIG. 3J, a metal electrode 8 is formed on the heavily doped layer 7 on the diamond semiconductor region 1 to form a diamond field effect transistor.

  In the present embodiment, since the second insulating film 9 is provided on both side surfaces of the stacked body, an undesirable contact with the gate electrode layer 4 can be more effectively prevented.

  4A to 4G are cross-sectional views showing a method of manufacturing a diamond semiconductor device according to the fourth embodiment of the present invention in the order of steps. As shown in FIG. 4A, a first diamond semiconductor region 1 as a channel layer is prepared, and an insulating film 2 is formed on the first diamond semiconductor region 1 as shown in FIG. Then, the first buffer layer 11, the second buffer layer 12, the gate metal electrode layer 3, and the sacrificial layer 4 are formed in this order. The first buffer layer 11 is, for example, a semiconductor oxide, and the second buffer layer 12 is, for example, a semiconductor.

  4C, an electrode pattern resist 5 is formed on the sacrificial layer 4, and the resist film 5 is used as a mask to form the insulating film 2 and the first buffer as shown in FIG. 4D. The stacked body of the layer 11, the second buffer layer 12, the gate metal electrode layer 3, and the sacrificial layer 4 is etched. Next, as shown in FIG. 4E, the resist 5 is removed, and as shown in FIG. 4F, the heavily doped layer 7a is selectively formed only on the surface where the diamond semiconductor region 1 is exposed. accumulate. As a result, the second buffer layer 12 is silicided with the gate electrode layer 3 to form a silicide layer 13. Thereafter, as shown in FIG. 4G, metal electrodes 8 are formed on the pair of heavily doped layers 7a.

  Thus, in the present embodiment, the gate electrode layer 3 is formed on the first diamond semiconductor region 1 as the channel layer via the insulating film 2, the first buffer layer 11, and the silicide layer 13. Then, the heavily doped layer 7a is formed so as to be in contact with the side surface of the stacked body, and a field effect transistor having a structure in which the source / drain electrode 8 is in contact with the heavily doped layer 7a is formed. In this transistor, since the heavily doped layer 7a is in contact with the insulating film 2, a channel region is formed immediately below the stacked body, and the length of the channel region matches the width of the stacked body. The channel region can be further shortened.

  The second buffer layer 12 is a layer containing a semiconductor element as a main component. This layer containing a semiconductor element as a main component is stable at a high temperature, and the resistance value can be controlled by doping. The second buffer layer 11 is a semiconductor element oxide layer. However, the second buffer layer 11 is not necessarily provided. The buffer layer is preferably composed of a layer containing a semiconductor element as a main component (second buffer layer 12) and an oxide layer of the semiconductor element (first buffer layer 11). Since the second buffer layer 12 containing the semiconductor element as a main component becomes metallic by doping, good electrical contact with the metal layer of the gate electrode 3 can be realized. The first buffer layer 11 made of an oxide layer of a semiconductor element is a good insulating material and can form an insulating layer together with the insulating film 2. In addition, by combining the semiconductor element and the oxide layer of the semiconductor element, the adhesiveness to each other is good, so that a stable interface can be formed.

  The semiconductor source cord is, for example, silicon or germanium. The gate electrode layer 3 is, for example, a refractory metal. As a result, the gate electrode layer 3 can sufficiently withstand high-temperature processing.

  Further, as the gate electrode layer 3, for example, Au, Ag, Cu, W, Ti, Mo, Ni, Ta, Nb, Pt, Ce, Co, Cr, Dy, Fe, Gd, Hf instead of the refractory metal. At least one metal selected from the group consisting of Mn, Nd, Pd, Pr, Ru, Sr, Tb, V, Y, and Zr can be used. These metals are materials that form stable silicides.

  When the second buffer layer 12 is a silicon layer, the second buffer layer 12 is heated to silicide Au or the like of the gate electrode layer 3 in the step of forming the heavily doped layer 7a shown in FIG. As a result, the silicide layer 13 is formed. When the second buffer layer 12 is made of silicon, the reaction proceeds between the metal layer of the gate electrode layer 3 and the second buffer layer 11 when processing at a high temperature is performed, and the silicide layer 13 is formed. When the silicide layer 13 is formed, a stable bond is formed at the interface, so that the adhesion at the buffer layer / metal interface can be improved. Further, since silicide exhibits low resistance, it can be used as it is as a metal electrode. In general, it is preferable to make the insulating film as thin as possible and to reduce the distance between the semiconductor layer and the metal. Since the buffer layer forms silicide and acts as a metal, the distance between the semiconductor layer and the metal can be prevented from becoming unnecessarily large. This semiconductor layer means a channel portion of the semiconductor region. The second buffer layer 12 may be a silicide layer 13 depending on the processing time and processing temperature at a high temperature, or a part of the second buffer layer 12 may remain without being a silicide layer. Preferably, the second buffer layer 12 is all silicided.

  In the present embodiment, by disposing an insulating film / buffer layer / metal laminate on the semiconductor region, a capacitor in which the semiconductor is in contact with the metal via the insulating film can be stably formed.

  5A to 5J are cross-sectional views showing a method of manufacturing a diamond semiconductor device according to the fifth embodiment of the present invention in the order of steps. The steps shown in FIG. 5E are the same as the steps shown in FIGS. Next, as shown in FIG. 5F, a second sacrificial layer 6 is formed on the entire surface. Thereafter, as shown in FIG. 5G, the second sacrificial layer 6 is etched back to form the second sacrificial layer 6 only on the side surface of the stacked body. Next, as shown in FIG. 5 (h), a heavily doped layer 7 a is selectively formed on the exposed surface of the first diamond semiconductor region 1.

  Next, as shown in FIG. 5 (i), a metal electrode layer 14 is formed on the entire surface, and the sacrificial layer 4 and the second sacrificial layer 6 are dissolved as shown in FIG. Thus, the metal electrode layer 14 on the laminate is removed. As a result, a laminated body composed of the insulating film 2, the first buffer layer 11, the silicide layer 13 and the gate electrode layer 3 is formed on the first diamond semiconductor region 1, and the metal electrode layer 14 is formed in the vicinity of the laminated body. A highly doped layer 7 a is formed on the first diamond semiconductor region 1 by being separated from the stacked body by the thickness of the second sacrificial layer 6.

  6A to 6G are cross-sectional views showing a method of manufacturing a diamond semiconductor device according to the sixth embodiment of the present invention in the order of steps. In FIG. 6, the same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is different from the embodiment shown in FIG. 4 in that, as shown in FIG. 6D, the resist 5 is used as a mask, the insulating film 2, the first buffer layer 11, the second buffer layer 12, and the gate. When the electrode layer 3 and the sacrificial layer 4 are etched, the surface of the diamond semiconductor region 1 is dug to form a step on the surface of the diamond semiconductor region 1.

  This reliably prevents the heavily doped layer 7a from coming into contact with the gate electrode layer 4 as shown in FIG.

  7A to 7J are cross-sectional views showing a method of manufacturing a diamond semiconductor device according to the seventh embodiment of the present invention in the order of steps. 7, the same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is different from the embodiment shown in FIG. 4 in that the second insulating film 9 shown in FIG. 7F is formed. As shown in FIG. 7E, after the stacked body (insulating film 2, first buffer layer 11, second buffer layer 12, gate electrode layer 3 and sacrificial layer 4) is formed in a pattern, the structure shown in FIG. 2), a second insulating film 9 is formed on the entire surface. Thereafter, as shown in FIG. 7G, the second insulating film 9 is etched back to leave the second insulating film 9 only on the side surfaces of the stacked body. After that, as shown in FIG. 7 (h), a heavily doped layer 7a is selectively formed only on the exposed surface of the first diamond semiconductor region 1. Next, as shown in FIG. 7I, when the sacrificial layer 4 is dissolved, a structure in which the second insulating film 9 covers the side surface of the stacked body is formed. Thereafter, as shown in FIG. 7 (j), a metal electrode 8 is formed on the heavily doped layer 7a on the diamond semiconductor region 1 to form a diamond field effect transistor.

  In the present embodiment, since the second insulating film 9 is provided on both side surfaces of the stacked body, an undesirable contact with the gate electrode layer 4 can be more effectively prevented.

  In the present invention grasped by each of the above-described embodiments, the distance between the source / drain diamond layer and the gate electrode can be reduced as compared with the invention described in Patent Document 4. Thereby, the parasitic component of electrostatic capacitance can be reduced and high frequency characteristics can be improved. Further, the distance (offset) between the metal electrode of the sword / drain and the channel can be reduced. Thereby, the parasitic component of the resistance caused by the diamond layer of the source / drain (having higher resistance than the metal) can be reduced, and an increase in current can be realized. As described above, according to the present invention, the parasitic capacity can be reduced, and as a result, the amount of current that should be controlled increases, so that the responsiveness is improved.

  In the invention described in Patent Document 5, the processing accuracy is improved by making the upper part of the diamond layer thicker, but this is substantially difficult. That is, the vapor deposition method is used to form the source / drain electrodes, but the upper part of the diamond layer is not completely eaves, and the metal electrode goes around the bottom of the diamond layer. As a result, the metal electrodes may come into contact with each other and the diamond layer may not be insulated. On the other hand, in this invention, since a sacrificial layer is used, reliable insulation is possible.

Further, in the semiconductor element described in Patent Document 6, carriers are allowed to flow using an impurity-doped diamond layer (about 1 × 10 ¹⁹ cm ⁻³ ) as a channel. Even in the present invention, doping is performed slightly, but the doping amount is extremely low (about 1 × 10 ¹⁷ cm ⁻³ ). When doping up to about 1 × 10 ¹⁹ cm ⁻³ , conductive carriers are scattered by the doped impurities, and the mobility is significantly reduced. For this reason, a sufficient amount of current cannot be obtained. In the present invention, the doping level (about 1 × 10 ¹⁷ cm ⁻³ ) hardly causes scattering due to impurities, and a diamond layer that does not cause such scattering is used as a channel. A current can be obtained.

  As described above, in the present invention, the amount of current that should be controlled is increased with respect to the conventional technique, so that the response is improved.

  Next, examples for demonstrating the effects of the present invention will be described. In Example 1, a diamond semiconductor element is formed by the manufacturing method shown in FIG. Using a non-doped diamond single crystal as a base material, homoepitaxial diamond was formed on the surface to form a channel layer. Aluminum oxide 50 nm was deposited as the device insulating film 2, tungsten 200 nm was deposited as the gate metal layer 3, and silicon oxide 50 nm was deposited continuously as the sacrificial layer 4. A resist 5 was patterned thereon by electron beam lithography. Then, using this resist 5 as a mask, silicon oxide, tungsten, and aluminum oxide were etched by dry etching to obtain a laminate of insulating film 2 / gate electrode metal layer 3 / sacrificial layer 4. After removing the resist 5, silicon oxide was deposited again by 50 nm as the second sacrificial layer 6. Subsequently, etch back was performed by dry etching. Since dry etching is anisotropic etching, the second sacrificial layer 6 remains on the side wall of the stacked body. On this, 20 nm of microcrystalline diamond was deposited as the highly doped layer 7. Deposition was performed by microwave plasma CVD at 600 ° C. (˜time), using hydrogen, methane and carbon dioxide as source gases, and diborane was added for doping. The particle size of the microcrystalline diamond was 2-3 nm. After the deposition, silicon oxide was etched with dilute hydrofluoric acid, and then ultrasonic waves were applied in pure water to lift off the highly doped layer 7 that was not in contact with the channel layer. Thereafter, an electrode 8 to the heavily doped layer 7 was formed by photolithography and lift-off. As the electrode metal, for example, a metal exhibiting ohmic bonding characteristics such as Pt, Au, Ti, and W was used.

  Thus, the semiconductor element having the element structure shown in FIG. 1 was produced. Electrical characteristics were evaluated. The insulation between the gate metal layer 3 and the heavily doped layer 7 was sufficiently maintained, and the transistor operation by hole injection from the P-type heavily doped layer into the channel layer could be confirmed.

  In Example 2, a diamond semiconductor element is formed by the process shown in FIG. Using a diamond single crystal as a base material, a homoepitaxial diamond was formed on the surface to form a channel layer. As an insulating film for the device, 50 nm of aluminum oxide, 200 nm of tungsten as a gate metal, and 50 nm of silicon oxide as a sacrificial layer were successively deposited. A resist was patterned thereon by electron beam lithography. Then, using this resist as a mask, silicon oxide, tungsten, and aluminum oxide were etched by dry etching to obtain a laminate of insulating film / electrode metal / sacrificial layer. Further, the diamond surface of 20 nm was also etched. Thereafter, a heavily doped layer and an electrode metal were formed in the same manner as in Example 1.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 2 was produced. As a result of electrical characteristics evaluation, the insulation between the gate metal and the heavily doped layer is sufficiently maintained, and transistor operation by hole injection from the P-type heavily doped layer to the channel layer is confirmed. did.

  In Example 3, a diamond semiconductor element was formed by the process shown in FIG. Using a diamond single crystal as a base material, a homoepitaxial diamond was formed on the surface to form a channel layer. As an insulating film for the element, 50 nm of aluminum oxide, 200 nm of tungsten as a gate metal, and 50 nm of silicon oxide as a sacrificial layer were successively deposited. A resist was patterned thereon by electron beam lithography. Then, using this resist as a mask, silicon oxide, tungsten, and aluminum oxide were etched by dry etching to obtain a laminate of insulating film / electrode metal / sacrificial layer. After removing the resist, 50 nm of aluminum oxide was again deposited as the second insulating film, and 50 nm of silicon oxide was deposited as the second sacrificial layer. Subsequently, etch back was performed by dry etching. Since dry etching is anisotropic etching, the second insulating film and the second sacrificial layer remain on the side wall of the stacked body. To this, 20 nm of microcrystalline diamond was deposited as a highly doped layer. Deposition was performed at 600 ° C. by a microwave plasma CVD method, using hydrogen, methane, and carbon dioxide as source gases, and diborane was added for doping. After deposition, silicon oxide was etched with dilute hydrofluoric acid, and then ultrasonic waves were applied in pure water to lift off the highly doped layer that was not in contact with the channel layer. After lift-off, the laminated body was observed with an electron microscope. Most of the tip of the second insulating film was bent and adhered to the gate metal, and it was confirmed that there was no effect on device fabrication. Then, the electrode to the high concentration dope layer was formed by photolithography and lift-off. As the electrode metal, for example, a metal exhibiting ohmic bonding characteristics such as Pt, Au, Ti, and W was used.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 3 was produced. As a result of evaluating the electrical characteristics, the insulation between the gate metal and the heavily doped layer was sufficiently maintained, and the transistor operation by the hole injection from the high concentration of P-type into the channel layer was confirmed.

  In Example 4, a diamond semiconductor element was formed by the process shown in FIG. Using a diamond single crystal as a base material, a homoepitaxial diamond was formed on the surface to form a channel layer. Aluminum oxide 50 nm as an insulating film for the element, tungsten 200 nm as a gate metal, and silicon oxide 50 nm as a sacrificial layer were successively deposited. A resist was patterned thereon by electron beam lithography. Then, using this resist as a mask, silicon oxide, tungsten, and aluminum oxide were etched by dry etching to obtain a laminate of insulating film / electrode metal / sacrificial layer. After removing the resist, 50 nm of aluminum oxide was again deposited as the second insulating film, and 50 nm of silicon oxide was deposited as the second sacrificial layer. Subsequently, etch back was performed by dry etching. Since dry etching is anisotropic etching, the second insulating film and the second sacrificial layer remain on the side wall of the stacked body. On this, 20 nm of microcrystalline diamond is deposited as a highly doped layer. Deposition was performed at 600 ° C. by a microwave plasma CVD method. Hydrogen, methane, and carbon dioxide were used as source gases, and nitrogen was added for doping. The grain size of the microcrystalline diamond was 2-5 nm. After deposition, silicon oxide was etched with dilute hydrofluoric acid, and then ultrasonic waves were applied in pure water to lift off the highly doped layer that was not in contact with the channel layer. After lift-off, the laminated body was observed with an electron microscope. Most of the tip of the second insulating film was bent and adhered to the gate metal, and it was confirmed that there was no effect on device fabrication. After that, an electrode to the highly-dope doped layer was formed by photolithography and lift-off. As the electrode metal, for example, a metal exhibiting ohmic bonding characteristics such as Pt, Au, Ti, and W was used.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 3 was produced. As a result of the electrical characteristics evaluation, the insulation between the gate metal and the heavily doped layer was sufficiently maintained, and the transistor operation by the electron injection from the N-type heavily doped layer to the channel layer was confirmed. .

  In addition, as a method of forming a high concentration doped layer with diamond, there is a method of introducing a doping gas when chemical vapor synthesis of diamond is performed. Such chemical vapor synthesis of diamond is generally performed at a high temperature of 700 ° C. or higher. Since the process is performed at a high temperature, when the process is performed in a state where the metal electrode of the transistor is present, there arises a problem that the metal electrode is aggregated or peeled off. That is, it cannot be used after forming a gate electrode or the like, and cannot meet the above-described demand for improvement in processing accuracy.

  Next, Example 5 will be described. This Example 5 was manufactured by the manufacturing method of the diamond semiconductor element shown in FIG. Using a diamond single crystal as a base material, homoepitaxial diamond was formed on the surface to form a channel layer. Aluminum oxide 45 nm as the insulating film 2 for the element, silicon oxide 5 nm as the oxide of the semiconductor element of the first buffer layer 11, polysilicon 50 nm as the semiconductor element of the second buffer layer 12, tungsten as the gate metal layer 3 200 nm and silicon oxide 50 nm as the sacrificial layer 4 were continuously deposited. A resist 5 was patterned thereon by electron beam lithography. Then, using this resist 5 as a mask, etching of silicon oxide, tungsten and aluminum oxide is performed by dry etching, and insulating film 2 (aluminum oxide) / buffer layers 11 and 12 (silicon oxide / polysilicon) / gate metal electrode layer 3 ( A laminate of tungsten) / sacrificial layer 4 (silicon oxide) was obtained. After removing the resist 5, 20 nm of diamond was deposited as the high-concentration doped layer 7a. Deposition was performed at 800 ° C. by a microwave plasma CVD method. Hydrogen and methane were used as source gases, and diborane was added for doping. At this time, the diamond selectively grew only in the portion where the diamond on the surface of the substrate was exposed before the diamond was formed. After deposition, silicon oxide was etched with dilute hydrofluoric acid to remove it. Then, the electrode 8 to the high concentration doped layer 7a was formed by photolithography and lift-off. As the electrode metal, for example, a metal exhibiting ohmic bonding characteristics such as Pt, Au, Ti, and W was used.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 4 was produced. As a result of the electrical characteristic evaluation, the insulation between the gate metal layer 3 and the heavily doped layer 7a is sufficiently maintained, and the channel layer (first diamond semiconductor) is formed from the P-type heavily doped layer 7a. The transistor operation by hole injection into layer 1) was confirmed. The sacrificial layer 4 protects the surface of the gate metal electrode 3 at the stage of diamond formation, and is effective in preventing alteration of the gate metal.

  In Example 6, a diamond semiconductor element was manufactured by the process shown in FIG. A process similar to that in Example 5 was performed until the stacked body was formed, and a stacked body of insulating film (aluminum oxide) / buffer layer (silicon oxide / polysilicon) / metal (tungsten) / sacrificial layer (silicon oxide) was formed. After removing the resist, 50 nm of silicon oxide was deposited again as the second sacrificial layer 6. Subsequently, etch back was performed by dry etching. Since dry etching is anisotropic etching, the second sacrificial layer 6 remains on the side wall of the stacked body. To this, 20 nm of diamond was deposited as a highly doped layer. Deposition was performed at 800 ° C. by a microwave plasma CVD method. Hydrogen and methane were used as source gases, and diborane was added for doping. At this time, the diamond was selectively grown only on the portion of the substrate surface where the diamond was exposed in the stage before the diamond formation. An electrode metal for the heavily doped layer was deposited by sputtering. As the electrode metal, for example, a metal exhibiting ohmic bonding characteristics such as Pt, Au, Ti, and W was used. After the deposition, silicon oxide, which is the second sacrificial layer, was etched using dilute hydrofluoric acid to remove the second sacrificial layer and the electrode metal formed on the second sacrificial layer.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 5 was produced. As a result of the electrical characteristic evaluation, the insulation between the gate metal and the heavily doped layer is sufficiently maintained, and the transistor operation by the hole injection from the P-type heavily doped layer 7a to the channel layer is performed. confirmed. Moreover, the use of the second sacrificial layer 6 can add an effect of preventing inadvertent electrical contact between the highly doped diamond and the laminate. Moreover, it becomes possible to arrange | position the electrode metal for highly doped layers in the immediate vicinity of a laminated body. Thereby, the parasitic resistance of the element can be reduced.

  In Example 7, a diamond semiconductor element was manufactured by the process shown in FIG. A process similar to that in Example 5 was performed until the stacked body was formed, and a stacked body of insulating film (aluminum oxide) / buffer layer (silicon oxide / polysilicon) / metal (tungsten) / sacrificial layer (silicon oxide) was formed. Further, the diamond surface of 20 nm was also etched. Thereafter, a heavily doped layer and an electrode metal were formed in the same manner as in Example 1.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 6 was produced. As a result of electrical characteristics evaluation, the insulation between the gate metal and the heavily doped layer is sufficiently maintained, and transistor operation by hole injection from the P-type heavily doped layer to the channel layer is confirmed. did. Thus, by etching the diamond substrate, inadvertent electrical contact between the highly doped diamond layer 7a and the laminate can be reliably prevented.

  In Example 8, a diamond semiconductor element was manufactured by the process shown in FIG. The same process as in Example 5 was performed until the multilayer body was formed, and a multilayer body of insulating film (aluminum oxide) / buffer layer (silicon oxide / polysilicon) / metal (tungsten) / sacrificial layer (silicon oxide) was formed. After removing the resist, 50 nm of aluminum oxide was again deposited as the second insulating film 9. Subsequently, etch back was performed by dry etching. Since the dry etching is anisotropic etching, the second insulating film 9 remains on the side wall of the stacked body. Then, 20 nm of diamond was deposited as the high concentration doped layer 7a. Deposition was performed at 800 ° C. by a microwave plasma CVD method. Hydrogen and methane were used as source gases, and diborane was added for doping. At this time, the diamond selectively grew only in the portion where the diamond on the surface of the substrate was exposed before the diamond was formed. After deposition, silicon oxide was etched with dilute hydrofluoric acid to remove it. After etching of the silicon oxide, the laminated body was observed with an electron microscope. It was confirmed that most of the tip end portion of the second insulating film was bent along the gate electrode layer 3 and adhered to the device without affecting the device fabrication. Then, the electrode to the high concentration dope layer was formed by photolithography and lift-off. As the electrode metal, for example, a metal exhibiting ohmic bonding characteristics such as Pt, Au, Ti, and W was used.

  Thus, a diamond semiconductor element having the element structure shown in FIG. 7 was produced. As a result of electrical characteristics evaluation, the insulation between the gate metal and the heavily doped layer is sufficiently maintained, and transistor operation by hole injection from the P-type heavily doped layer to the channel layer is confirmed. did.

  Thus, by providing the second insulating film 9, inadvertent electrical contact between the diamond of the highly doped layer 7a and the laminate can be reliably prevented.

It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 1st Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 2nd Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 3rd Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 4th Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 5th Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 6th Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the diamond semiconductor element of 7th Embodiment of this invention in order of a process.

Explanation of symbols

1: First diamond semiconductor region 2: Insulating film 3: Gate electrode layer 4: Sacrificial layer 5: Resist 6: Second sacrificial layer
7, 7a: Highly doped layer 8: Electrode 9: Second insulating film 11: First buffer layer 12: Second buffer layer 13: Silicide layer

Claims (16)

A step of laminating an insulating film and an electrode metal layer on the surface of the first diamond semiconductor region, and further laminating a first sacrificial layer;
Patterning a resist locally on the surface of the first sacrificial layer;
Using the resist as a mask, the first sacrificial layer, the electrode metal layer, and the insulating film are etched, and then the resist is removed to form an insulating film and an electrode on the surface of the first diamond semiconductor region. Patterning a laminate composed of a metal layer and a first sacrificial layer;
Forming impurity doped second and third diamond semiconductor regions on the surface of the first diamond semiconductor region;
Removing the first sacrificial layer by etching;
Forming an electrode metal on the surfaces of the second and third diamond semiconductor regions;
A method for producing a diamond semiconductor element, comprising: 2. The method of manufacturing a diamond semiconductor element according to claim 1, wherein the second and third diamond semiconductor regions are formed by a microwave CVD method at a temperature of 600 ° C. or less. A side surface of the laminate is formed by etching back after forming a second sacrificial layer between the step of patterning the laminate and the step of forming the second and third diamond semiconductor regions. And the step of leaving the second sacrificial layer and a lift-off step of removing the sacrificial layer and the second sacrificial layer after forming a highly doped layer on the entire surface. The method of manufacturing a diamond semiconductor element according to claim 2, wherein a third diamond semiconductor region is formed on the first diamond semiconductor region. A buffer layer including a semiconductor element layer containing at least a semiconductor element is stacked between the insulating film and the electrode metal layer, and the second and third diamond semiconductor regions have a temperature exceeding 600 ° C. and not more than 1200 ° C. The method for producing a diamond semiconductor element according to claim 1, wherein the diamond semiconductor element is formed by a microwave CVD method at a temperature of 1 mm. The buffer layer has a two-layer structure of the semiconductor element layer and the oxide layer of the semiconductor element, and the electrode metal layer and the semiconductor element layer react when heated at the temperature. The method for producing a diamond semiconductor element according to claim 4. The semiconductor element is silicon or germanium, and the electrode metal layer is Au, Ag, Cu, W, Ti, Mo, Ni, Ta, Nb, Pt, Ce, Co, Cr, Dy, Fe, Gd, Hf, 6. The diamond semiconductor device according to claim 5, wherein the diamond semiconductor device is formed of at least one selected from the group consisting of Mn, Nd, Pd, Pr, Ru, Sr, Tb, V, Y, and Zr. Method. Before the step of forming the second and third diamond semiconductor regions, a step of forming a second sacrificial layer on both side surfaces of the stacked body is provided, and the second and third diamond semiconductor regions are formed. The method for manufacturing a diamond semiconductor element according to claim 4, further comprising a step of removing the second sacrificial layer by etching after the step of performing the step. 8. The method according to claim 1, wherein after the patterning of the laminated body, the surface of the first diamond semiconductor region is further etched to dig the surface of the first diamond semiconductor region. The manufacturing method of the diamond semiconductor element of description. 9. The method for manufacturing a diamond semiconductor element according to claim 1, further comprising a step of forming a second insulating film on a side surface of the stacked body after forming the stacked body. A laminate formed locally on the first diamond semiconductor region and comprising a lower insulating film and an upper electrode metal layer;
Second and third diamond semiconductor regions provided on both sides of the stacked body on the first diamond semiconductor region;
Electrodes respectively formed on the second and third diamond semiconductor regions;
A diamond semiconductor element comprising: 11. The diamond semiconductor element according to claim 10, wherein the second and third diamond semiconductor regions are made of microcrystalline diamond having a diamond grain size of 1 to 100 nm. 11. The diamond semiconductor according to claim 10, wherein a buffer layer is disposed between the insulating film and the electrode metal layer, and the buffer layer includes a semiconductor element layer containing at least a semiconductor element. element. 13. The diamond semiconductor element according to claim 10, wherein the second and third diamond semiconductor regions are more highly doped than the first diamond semiconductor region. 14. The diamond semiconductor element according to claim 10, wherein a second insulating film is formed on both side surfaces of the multilayer body. The second and third diamond semiconductor regions and the insulating film of the stacked body are disposed on the same plane as the first diamond semiconductor region, and the insulating film has a thickness of the second and second diamond semiconductor regions. 15. The diamond semiconductor element according to claim 10, wherein the diamond semiconductor element is larger than a thickness of the diamond semiconductor region of 3. 16. The diamond semiconductor element according to claim 10, wherein a length (width) of the stacked body serving as a channel region is 100 m or more and 1 μm or less.

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