JP2007141974A5 - - Google Patents

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JP2007141974A5
JP2007141974A5 JP2005330888A JP2005330888A JP2007141974A5 JP 2007141974 A5 JP2007141974 A5 JP 2007141974A5 JP 2005330888 A JP2005330888 A JP 2005330888A JP 2005330888 A JP2005330888 A JP 2005330888A JP 2007141974 A5 JP2007141974 A5 JP 2007141974A5
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diamond semiconductor
layer
diamond
insulating film
forming
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JP2005330888A
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JP2007141974A (en
JP4817813B2 (en
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第1のダイヤモンド半導体領域の表面上に、絶縁膜と電極金属層とを積層した上に、更に第1の犠牲層を積層する工程と、
前記第1の犠牲層の表面上に、局所的にレジストをパターン形成する工程と、
前記レジストをマスクとして、前記第1の犠牲層、前記電極金属層及び前記絶縁膜をエッチングした後、前記レジストを除去することにより、前記第1のダイヤモンド半導体領域の表面上に、絶縁膜と電極金属層と第1の犠牲層とからなる積層体をパターン形成する工程と、
前記積層体の側面に第2の犠牲層を形成する工程と、
全面に不純物がドープされた不純物層を形成する工程と、
前記第1及び第2の犠牲層をエッチングにより除去することによるリフトオフにより前記積層体及び前記第2の犠牲層の上の不純物層を除去して、前記第1のダイヤモンド半導体領域の上に残存した不純物層により第2及び第3のダイヤモンド半導体領域を形成する工程と、
前記第2及び第3のダイヤモンド半導体領域の表面上に電極金属を形成する工程と、
を有することを特徴とするダイヤモンド半導体素子の製造方法。
Laminating an insulating film and an electrode metal layer on the surface of the first diamond semiconductor region, and further laminating a first sacrificial layer;
Patterning a resist locally on the surface of the first sacrificial layer;
Using the resist as a mask, the first sacrificial layer, the electrode metal layer, and the insulating film are etched, and then the resist is removed to form an insulating film and an electrode on the surface of the first diamond semiconductor region. Patterning a laminate composed of a metal layer and a first sacrificial layer;
Forming a second sacrificial layer on a side surface of the laminate;
Forming an impurity layer doped with impurities on the entire surface ;
The impurity layer on the stacked body and the second sacrificial layer is removed by lift-off by removing the first and second sacrificial layers by etching , and remains on the first diamond semiconductor region. Forming second and third diamond semiconductor regions with an impurity layer ;
Forming an electrode metal on the surfaces of the second and third diamond semiconductor regions;
A method for producing a diamond semiconductor element, comprising:
前記不純物層の形成工程は、前記不純物層を600℃以下の温度でマイクロ波CVD法により形成するものであることを特徴とする請求項1に記載のダイヤモンド半導体素子の製造方法。 The step of forming the impurity layer, the manufacturing method of a diamond semiconductor device according to claim 1, characterized in that said impurity layer is to form by a microwave CVD method at 600 ° C. or lower. 前記第2の犠牲層の形成工程は、全面に第2の犠牲層を形成した後エッチバックすることにより、前記積層体の側面に前記第2の犠牲層を残すものであることを特徴とする請求項2に記載のダイヤモンド半導体素子の製造方法。 The step of forming the second sacrificial layer, and wherein the entire surface by etching back after the form form the second sacrificial layer is intended to leave the second sacrificial layer on the side surfaces of the laminate A method for producing a diamond semiconductor device according to claim 2. 第1のダイヤモンド半導体領域の表面上に、絶縁膜と電極金属層とを積層した上に、更に第1の犠牲層を積層する工程と、
前記第1の犠牲層の表面上に、局所的にレジストをパターン形成する工程と、
前記レジストをマスクとして、前記第1の犠牲層、前記電極金属層及び前記絶縁膜をエッチングした後、前記レジストを除去することにより、前記第1のダイヤモンド半導体領域の表面上に、絶縁膜と電極金属層と第1の犠牲層とからなる積層体をパターン形成する工程と、
前記第1のダイヤモンド半導体領域の表面上のみに前記電極金属層に接触しないように、不純物がドープされた不純物層を形成し、この不純物層により第2及び第3のダイヤモンド半導体領域を形成する工程と、
前記第1の犠牲層をエッチングにより除去する工程と、
前記第2及び第3のダイヤモンド半導体領域の表面上に電極金属を形成する工程と、
を有することを特徴とするダイヤモンド半導体素子の製造方法。
Laminating an insulating film and an electrode metal layer on the surface of the first diamond semiconductor region, and further laminating a first sacrificial layer;
Patterning a resist locally on the surface of the first sacrificial layer;
Using the resist as a mask, the first sacrificial layer, the electrode metal layer, and the insulating film are etched, and then the resist is removed to form an insulating film and an electrode on the surface of the first diamond semiconductor region. Patterning a laminate composed of a metal layer and a first sacrificial layer;
Forming an impurity layer doped with impurities so as not to contact the electrode metal layer only on the surface of the first diamond semiconductor region, and forming the second and third diamond semiconductor regions by the impurity layer ; When,
Removing the first sacrificial layer by etching;
Forming an electrode metal on the surfaces of the second and third diamond semiconductor regions;
A method for producing a diamond semiconductor element, comprising:
前記絶縁膜と前記電極金属層との間に、少なくとも半導体元素を含有した半導体元素層を具備する緩衝層を積層し、前記第2及び第3のダイヤモンド半導体領域は、600℃を超え1200℃以下の温度で、マイクロ波CVD法により形成することを特徴とする請求項に記載のダイヤモンド半導体素子の製造方法。 A buffer layer including a semiconductor element layer containing at least a semiconductor element is stacked between the insulating film and the electrode metal layer, and the second and third diamond semiconductor regions have a temperature exceeding 600 ° C. and not more than 1200 ° C. The method for producing a diamond semiconductor element according to claim 4 , wherein the diamond semiconductor element is formed by a microwave CVD method at a temperature of 5 ° C. 前記緩衝層は、前記半導体元素層と前記半導体元素の酸化物層との2層構造を有し、前記温度での加熱時に、前記電極金属層と前記半導体元素層とが反応することを特徴とする請求項に記載のダイヤモンド半導体素子の製造方法。 The buffer layer has a two-layer structure of the semiconductor element layer and the oxide layer of the semiconductor element, and the electrode metal layer and the semiconductor element layer react when heated at the temperature. A method for producing a diamond semiconductor device according to claim 5 . 前記半導体元素は、シリコン又はゲルマニウムであり、前記電極金属層はAu、Ag、Cu、W、Ti、Mo、Ni、Ta、Nb、Pt、Ce、Co、Cr、Dy、Fe、Gd、Hf、Mn、Nd、Pd、Pr、Ru、Sr、Tb、V、Y及びZrからなる群から選択された少なくとも1種により形成されていることを特徴とする請求項に記載のダイヤモンド半導体素子の製造方法。 The semiconductor element is silicon or germanium, and the electrode metal layer is Au, Ag, Cu, W, Ti, Mo, Ni, Ta, Nb, Pt, Ce, Co, Cr, Dy, Fe, Gd, Hf, The diamond semiconductor device according to claim 6 , wherein the diamond semiconductor device is formed of at least one selected from the group consisting of Mn, Nd, Pd, Pr, Ru, Sr, Tb, V, Y, and Zr. Method. 前記第2及び第3のダイヤモンド半導体領域を形成する工程の前に、前記積層体の両側面に第2の犠牲層を形成する工程を有し、前記第2及び第3のダイヤモンド半導体領域を形成する工程の後に、前記第2の犠牲層をエッチングにより除去する工程を有することを特徴とする請求項4乃至のいずれか1項に記載のダイヤモンド半導体素子の製造方法。 Before the step of forming the second and third diamond semiconductor regions, a step of forming a second sacrificial layer on both side surfaces of the stacked body is provided, and the second and third diamond semiconductor regions are formed. after the step of manufacturing a diamond semiconductor device according to any one of claims 4 to 7, characterized by comprising a step of removing by etching the second sacrificial layer. 前記積層体をパターン形成した後に、前記第1のダイヤモンド半導体領域の表面を更にエッチングして第1のダイヤモンド半導体領域の表面を掘り込むことを特徴とする請求項1乃至のいずれか1項に記載のダイヤモンド半導体素子の製造方法。 After patterning the laminate, in any one of claims 1 to 8, characterized in that recessing the surface of the first first and further etching the surface of the diamond semiconductor region of diamond semiconductor region The manufacturing method of the diamond semiconductor element of description. 前記積層体を形成した後、前記積層体の側面に第2の絶縁膜を形成する工程を有することを特徴とする請求項1乃至のいずれか1項に記載のダイヤモンド半導体素子の製造方法。 After the laminate was formed, a manufacturing method of a diamond semiconductor device according to any one of claims 1 to 9, characterized in that a step of forming a second insulating film on the side surface of the laminate. 第1のダイヤモンド半導体領域上に局所的に形成され、下層の絶縁膜と上層の電極金属層からなる積層体と、
前記第1のダイヤモンド半導体領域上で、前記積層体の両側に隣接して設けられた第2及び第3のダイヤモンド半導体領域と、
第2及び第3のダイヤモンド半導体領域上に夫々形成された電極と、
を有することを特徴とするダイヤモンド半導体素子。
A laminate that is locally formed on the first diamond semiconductor region and includes a lower insulating film and an upper electrode metal layer;
Second and third diamond semiconductor regions provided adjacent to both sides of the stack on the first diamond semiconductor region;
Electrodes respectively formed on the second and third diamond semiconductor regions;
A diamond semiconductor device comprising:
前記第2及び第3のダイヤモンド半導体領域は、ダイヤモンドの粒径が乃至100nmの微結晶のダイヤモンドからなることを特徴とする請求項11に記載のダイヤモンド半導体素子。 12. The diamond semiconductor element according to claim 11 , wherein the second and third diamond semiconductor regions are made of microcrystalline diamond having a diamond grain size of 1 to 100 nm. 前記絶縁膜と前記電極金属層との間に緩衝層が配置されており、この緩衝層は、少なくとも半導体元素を含有する半導体元素層を具備することを特徴とする請求項11に記載のダイヤモンド半導体素子。 The diamond semiconductor according to claim 11 , wherein a buffer layer is disposed between the insulating film and the electrode metal layer, and the buffer layer includes a semiconductor element layer containing at least a semiconductor element. element. 前記第2及び第3のダイヤモンド半導体領域は、前記第1のダイヤモンド半導体領域よりも高濃度ドープされていることを特徴とする請求項11乃至13のいずれか1項に記載のダイヤモンド半導体素子。 The second and third diamond semiconductor regions, the diamond semiconductor device according to any one of claims 11 to 13, characterized in that it is heavily doped than said first diamond semiconductor region. 前記積層体の両側面に第2の絶縁膜が形成されていることを特徴とする請求項11乃至14のいずれか1項に記載のダイヤモンド半導体素子。 Diamond semiconductor device according to any one of claims 11 to 14, characterized in that the second insulating film on both sides of the laminate is formed. 前記第2及び第3のダイヤモンド半導体領域と、前記積層体の前記絶縁膜とが、前記第1のダイヤモンド半導体領域と同一平面上に配置され、前記絶縁膜の厚さは、前記第2及び第3のダイヤモンド半導体領域の厚さよりも大きいことを特徴とする請求項11乃至15のいずれか1項に記載のダイヤモンド半導体素子。 The second and third diamond semiconductor regions and the insulating film of the stacked body are disposed on the same plane as the first diamond semiconductor region, and the insulating film has a thickness of the second and second diamond semiconductor regions. 3 diamond semiconductor device according to any one of claims 11 to 15, being greater than the thickness of the diamond semiconductor region. チャネル領域となる前記積層体の長さ(幅)が、10nm以上1μm以下であることを特徴とする請求項11乃至16のいずれか1項に記載のダイヤモンド半導体素子。 The length of the laminate serving as a channel region (width), diamond semiconductor device according to any one of claims 11 to 16, wherein the at 10nm or more 1μm or less.
JP2005330888A 2005-11-15 2005-11-15 Diamond semiconductor device and manufacturing method thereof Expired - Fee Related JP4817813B2 (en)

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US8237170B2 (en) * 2007-04-27 2012-08-07 National Institute Of Advanced Industrial Science And Technology Schottky diamond semiconductor device and manufacturing method for a Schottky electrode for diamond semiconductor device
JP5042006B2 (en) * 2007-12-25 2012-10-03 日本電信電話株式会社 Diamond field effect transistor
JP5483168B2 (en) * 2009-07-24 2014-05-07 日本電信電話株式会社 Diamond thin film and diamond field effect transistor
JP2021145003A (en) * 2020-03-10 2021-09-24 学校法人早稲田大学 Diamond field effect transistor and method for producing same

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JPS61224363A (en) * 1985-03-28 1986-10-06 Fuji Xerox Co Ltd Thin film transistor and manufacture thereof
JPS6467970A (en) * 1987-09-08 1989-03-14 Fujitsu Ltd Thin film transistor
JP3364119B2 (en) * 1996-09-02 2003-01-08 東京瓦斯株式会社 Hydrogen-terminated diamond MISFET and method for manufacturing the same
JP3714803B2 (en) * 1998-10-09 2005-11-09 株式会社神戸製鋼所 Method for manufacturing diamond field effect transistor
FR2868209B1 (en) * 2004-03-25 2006-06-16 Commissariat Energie Atomique FIELD-FIELD FIELD EFFECT TRANSISTOR DIAMOND CARBON

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