JP2007123339A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for reducing the occurrence of crystal defects, or the like occurring from an element separation region. <P>SOLUTION: The manufacturing method of a semiconductor device comprises a process (a) for forming a first recognition mark 210 at a recess on a semiconductor layer 10, a process (b) for forming a well 20 on the semiconductor layer 10 by the first recognition mark 210, a process (c) for forming an element separation insulating layer 22 on the semiconductor layer 10, a process (d) for forming an insulating layer 214 for covering the inner surface of the recess 210 in the first recognition mark 210, a process (e) for forming an insulating layer 216 for embedding the recess 210 on the insulating layer 214 and forming a second recognition mark 200, and a process (f) for forming a transistor 100 on the semiconductor layer 10 by the second recognition mark 200. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In a method of manufacturing a semiconductor device having an element isolation region, particularly a high voltage transistor, an impurity is introduced into an element formation region other than the element isolation region after the element isolation region is formed in the semiconductor substrate as in Patent Document 1, for example. The well is formed by uniformly diffusing impurities into a desired region in the semiconductor substrate by heat treatment at a high temperature for a long time.
JP 2004-260073 A

  However, in the manufacturing method described above, heat is also applied to the element isolation region due to the heat treatment when forming the well in the semiconductor substrate on which the element isolation region is formed. As a result, for example, since the thermal expansion coefficient of the material forming the element isolation region is different from that of the semiconductor substrate, there is a possibility that a crystal defect is formed due to the stress and a current leakage due to this defect occurs. is there.

An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device for reducing the occurrence of crystal defects and the like generated from an element isolation region.

(1) A manufacturing method of a semiconductor device according to the present invention includes:
(A) forming a first recognition mark of a recess in the semiconductor layer;
(B) forming a well in the semiconductor layer using the first recognition mark;
(C) forming an element isolation insulating layer on the semiconductor layer;
(D) forming a first insulating layer covering an inner surface of the first recognition mark;
(E) forming a second insulating layer for embedding the first recognition mark on the first insulating layer, and forming a second recognition mark;
(F) forming a transistor in the semiconductor layer using the second recognition mark.

  According to the semiconductor device manufacturing method of the present invention, the well is formed before the element isolation insulating layer is formed. In the formation of the well, heat treatment at a high temperature may be performed for a long time in order to diffuse impurities. Such a heat treatment process gives thermal stress to the element isolation insulating layer in the semiconductor layer, and current leakage due to crystal defects may occur. However, according to the method for manufacturing a semiconductor device according to the present invention, since the well is formed before the element isolation insulating layer is formed, the above problem can be suppressed. As a result, a semiconductor device with improved reliability can be provided.

  In addition, the manufacturing method of the semiconductor device concerning this invention can take the following aspect further.

(2) In the method for manufacturing a semiconductor device according to the present invention,
The first recognition mark may be formed in a scribe area.

(3) In the method for manufacturing a semiconductor device according to the present invention,
The step (c) includes forming a groove in the semiconductor layer;
Embedding an insulating layer in the groove,
The step of embedding the insulating layer includes
This may be performed simultaneously with the formation of the second insulating layer in the step (e).

(4) In the method for manufacturing a semiconductor device according to the present invention,
The first insulating layer may be a nitride film, and the second insulating layer may be an oxide film.

(5) A semiconductor device according to the present invention includes:
A semiconductor layer having a chip region and a scribe region;
A transistor provided in the chip region;
A recognition mark provided in the scribe area,
The recognition mark is
A recess provided in the semiconductor layer;
A first insulating layer provided to cover the inner surface of the recess;
And a second insulating layer which is on the first insulating layer and fills the recess.

  The semiconductor device according to the present invention can further take the following aspects.

(6) In the semiconductor device according to the present invention,
The exposed surface of the first insulating layer is the same as the upper surface of the semiconductor layer or at a position lower than the upper surface of the semiconductor layer,
The top surface of the second insulating layer may be the same as the top surface of the semiconductor layer or higher than the top surface of the semiconductor layer.

(7) In the semiconductor device according to the present invention,
The upper surface of the second insulating layer may be at the same height as the upper surface of the element isolation insulating layer provided in the semiconductor layer.

(8) In the semiconductor device according to the present invention,
When viewed in a plan view, the element isolation insulating layer may not be provided in a region having a predetermined distance from the end of the recognition mark.

(9) In the semiconductor device according to the present invention,
The transistor is
A well provided in the semiconductor layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A channel region formed in the semiconductor layer;
A source region and a drain region provided in the semiconductor layer;
The channel region may include an offset insulating layer provided between the source region and the drain region.

  Next, an example of an embodiment of the present invention will be described with reference to the drawings.

1. Semiconductor Device First, a semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment.

  The semiconductor device according to the present embodiment includes a semiconductor layer 10 as shown in FIG. The semiconductor layer 10 has a chip region 10C and a scribe region 10S. The chip region 10C is a region where various semiconductor devices constituting the IC chip are formed. The scribe region 10S is provided around one semiconductor chip and includes a dicing area for dicing the semiconductor chip. Further, the chip region 10 </ b> C and the scribe region 10 </ b> S are each surrounded by the element isolation insulating layer 22.

  As shown in FIG. 1, the transistor 100 is formed in the chip region 10C. The transistor 100 is a transistor for high drive voltage operation. The transistor 100 includes a gate insulating layer 110, a gate electrode 112, a sidewall insulating layer 114, and a source region 116 and a drain region 116 (hereinafter referred to as a source region / drain region) which are high-concentration impurity layers. ”, An offset insulating layer 24, a low-concentration impurity layer 118, and a well 20.

  The gate insulating layer 110 is provided on the semiconductor layer 10 and on the channel region in the well 20. The gate electrode 112 is formed on the gate insulating layer 110. The sidewall insulating layer 114 is formed on the side of the gate electrode 112.

  The source / drain region 116 is formed in the upper part in the low concentration impurity layer 118. In the source region / drain region 116, the impurity concentration can be made higher than that in the low concentration impurity layer 118. The offset insulating layer 24 is formed to be embedded in the upper surface side of the semiconductor layer 10. The offset insulating layer 24 is formed between the source region 116 and the channel region under the gate insulating layer 110 and between the drain region 116 and the channel region under the gate insulating layer 110. The offset insulating layer 24 is included in the low concentration impurity layer 118.

  The low concentration impurity layer 118 is formed in the upper portion of the well 20. The low concentration impurity layer 118 overlaps with all of the source region / drain region 116 and is formed deeper than the source region / drain region 116. That is, the low concentration impurity layer 118 includes the source region / drain region 116. The well 20 is formed in the upper part of the semiconductor layer 10 and includes a low concentration impurity layer 118.

  In the semiconductor device according to the present embodiment, the case where only the transistor 100 for high drive voltage operation is provided in the chip region 10C is illustrated, but a plurality of transistors having different drive voltages are provided in this chip region. It goes without saying that it may be done.

  Next, the scribe area 10S will be described. A recognition mark 200 is formed in the scribe area 10S. The recognition mark 200 is used for aligning the semiconductor layer 10 and the mask layer, for example, in the process of forming the transistor 100 or the like. The recognition mark 200 can have various plane patterns (cross pattern, L-shaped pattern, line pattern, etc.) according to a recommended mark by an exposure apparatus vendor and an alignment method.

  The recognition mark 200 included in the semiconductor device according to the present embodiment corresponds to a recess 210 provided in the semiconductor layer 10 and an insulating layer 214 (“first insulating layer”) formed along the inner surface of the recess 210. ) And an insulating layer 216 (corresponding to a “second insulating layer”) in which the recess 210 is embedded. In the present embodiment, an insulating layer 212 is provided between the insulating layer 214 and the inner surface of the recess 210 (see the description of the manufacturing method described later). A nitride film such as a silicon nitride film can be formed as the insulating layer 214, and an oxide film such as a silicon oxide film can be formed as the insulating layer 216. The insulating layers 214 and 216 are preferably formed using insulating layers having different light refractive indexes. For example, a silicon nitride film and a silicon nitride film have optically different colors because the silicon nitride film has a refractive index different from that of the silicon oxide film. Usually, alignment of the device is often performed by an optical method (color difference or contrast difference). In the semiconductor device according to the present embodiment, a silicon nitride film (insulating layer 214) is formed on the inner surface of the recess 210. Therefore, even when the concave portion 210 is embedded with an insulating material, the concave portion can be easily detected. As a result, a semiconductor device having the recognition mark 200 with high recognizability even after a plurality of steps can be provided.

  In the scribe region 10S, the element isolation insulating layer 22 is not formed in a range having a predetermined distance X from the end of the recess 210. Here, the predetermined distance X is a distance that needs to be secured in order to prevent other grooves (steps) from being generated in a range where an alignment error may occur, and varies depending on the accuracy of the alignment apparatus and the like. It is. Thereby, the improvement of the further recognition property can be aimed at.

(Modification)
Next, a modification of the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view schematically showing a semiconductor device according to this modification. The semiconductor device according to this modification is an example in which the recognition mark 200 is different from the semiconductor device according to the above-described embodiment. In the following description, only differences from the semiconductor device shown in FIG.

  As shown in FIG. 2, the semiconductor device according to the present modification includes a chip region 10C and a scribe region 10S. A transistor 100 is provided in the chip region 10C. A recognition mark 200 is provided in the scribe area 10S. In the semiconductor device according to this modification, in the recognition mark 200, the exposed surface 215 of the insulating layer 214 and the upper surface 217 of the insulating layer 216 are different in height. Specifically, the exposed surface 215 is at a lower position than the upper surface 217. That is, a step is formed between the exposed surface 215 and the upper surface 217.

  According to this modification, as described in the above embodiment, in addition to the fact that materials having different reflectivities such as a silicon nitride film and a silicon oxide film are embedded in the recesses 210, Since there are also irregularities, the reflectance can be further varied. As a result, a semiconductor device having the recognition mark 200 with improved recognition can be provided.

2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 3 to 9 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the present embodiment.

  (1) First, as shown in FIG. 3, a semiconductor layer 10 having a chip region 10C and a scribe region 10S is prepared. A known material such as a single crystal silicon substrate can be used for the semiconductor layer 10. Next, a recess 210 serving as a first recognition mark for forming a well to be formed in a later step is formed in the scribe region 10S. In forming the recess 210, a mask layer (not shown) having an opening in the region where the recess 210 is formed is formed on the semiconductor layer 10. Next, the recess 210 can be formed by etching the semiconductor layer 10 using the mask layer.

  (2) Next, as shown in FIG. 4, the well 20 is formed in the chip region 10 </ b> C using the recess (first recognition mark) 210. First, after forming a mask layer (not shown) having an opening in a predetermined region, an impurity of a predetermined conductivity type is introduced into the semiconductor layer 10. In the step of forming the mask layer, for example, the recess 210 is used for alignment between the semiconductor layer 10 and the reticle. Subsequently, the well 20 is formed by performing heat treatment for diffusing the impurities. This heat treatment can be performed, for example, at a temperature of 900 ° C. or higher.

  (3) Next, the element isolation insulating layer 22 and the offset insulating layer 24 (see FIG. 1) are formed in the semiconductor layer 10. As an example of forming the element isolation insulating layer 22 and the offset insulating layer 24, a case where the element isolation insulating layer 22 and the offset insulating layer 24 are formed by the STI method will be described below. First, as shown in FIG. 5, an oxide film 12 and a nitride film 14 are formed on the entire surface of the semiconductor layer 10. When the semiconductor layer 10 is a silicon substrate, a silicon oxide film can be formed as the oxide film 12 and a silicon nitride film can be formed as the nitride film 14.

  Next, as shown in FIG. 5, a mask layer M1 having an opening 40 is formed in a region where the element isolation insulating layer 22 and the offset insulating layer 24 are to be formed. At this time, the opening 40 does not have an opening above a region where the recess 210 is formed and above a region having a predetermined distance X from the end of the recess 210. Here, the distance X from the end of the recess 210 is a distance that needs to be secured in order to prevent other grooves (steps) from being generated in a range where an alignment error may occur. The distance X varies depending on the accuracy of the alignment apparatus. Further, in the cross section shown in the present embodiment, the case where the trench 16 for the element isolation insulating layer 22 is formed at a position separated from the end of the concave portion 210 which is a recognition mark by a predetermined distance X or more is illustrated. .

  (4) Next, the oxide film 12, the nitride film 14, and the semiconductor layer 10 are etched using the mask layer M1 (see FIG. 5). By this step, a trench 16 is formed as shown in FIG. On the other hand, since the upper part of the recess 210 is covered with the mask layer M <b> 1, the inner surface of the recess 210 remains covered with the oxide film 12 and the nitride film 14. The nitride film 14 becomes an insulating layer 214 that covers the inner surface of the recess 210 in a later step.

  (5) Next, an insulating layer (not shown) is formed above the semiconductor layer 10 so as to fill the trench 16 and the recess 210. Next, as shown in FIG. 7, the insulating layer is etched by, for example, CMP until the nitride film 14 is exposed. Thereby, the insulating layers 22a, 24a, and 206a216a are formed. At this time, the insulating layer may be a film in which a plurality of insulating layers are stacked. For example, when a laminated film of a silicon nitride film and a silicon oxide film (a laminated film made of materials having different reflectivities) is used as the insulating layer, a silicon nitride film is formed on the inner surface of the recess 210, and the second recognition mark 200 Recognizability can be improved.

  (6) Next, as shown in FIG. 8, the nitride film 14 serving as a stopper is selectively removed. The removal of the nitride film 14 can be performed by, for example, wet etching using hot phosphoric acid. Then, if necessary, the insulating layer that protrudes by the thickness of the nitride film 14 is removed by a known etching method, so that the in-plane height of the semiconductor layer 10 can be made uniform. Through the above steps, as shown in FIG. 8, the element isolation insulating layer 22 and the offset insulating layer 24, and the insulating layer 214 and the insulating layer 216 embedded in the recess 210 are formed. That is, by this step, the second recognition mark 200 including the recess 210 and the insulating layer 214 embedded therein is formed.

  (7) Next, the transistor 100 (see FIG. 1) is formed in the chip region 10C. In forming the transistor 100, the second recognition mark 200 can be used in the step of forming at least one mask layer. Thus, the 1st recognition mark (recessed part 210) used at the previous process is applicable also at a subsequent process. Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, it is not necessary to increase the number of steps for forming the recognition mark. As a result, the number of processes can be reduced, and the manufacturing cost can be reduced. An example of a method for forming the transistor 100 is described below.

  First, as shown in FIG. 9, a low concentration impurity layer 118 is formed. This step is performed by forming a mask layer (not shown) having an opening above at least the low-concentration impurity layer 118 and then introducing an impurity of a predetermined conductivity type into the semiconductor layer 10. Moreover, you may perform the heat processing for diffusing an impurity as needed. This heat treatment is performed under conditions where the temperature is lowered or the treatment time is shortened as compared with the heat treatment performed in the step (2).

  Next, the gate insulating layer 110 is formed. In forming the gate insulating layer 110, an opening is formed in a region where the gate insulating layer 110 is to be formed, and a mask layer (not shown) for heat-resistant oxidation is formed. As the mask layer, for example, a silicon nitride film can be used. Then, the gate insulating layer 110 can be formed by performing thermal oxidation. Thereafter, the mask layer is removed by a known removal method corresponding to the material.

  (8) Next, as shown in FIG. 1, a gate electrode 112 is formed. In this step, first, a conductive layer (not shown) is formed above the entire surface of the semiconductor layer 10. As the conductive layer, for example, a polycrystalline silicon layer can be formed. Thereafter, this conductive layer is patterned to form the gate electrode 112. Next, a sidewall insulating layer 114 is formed on the side of the gate electrode 112. The sidewall insulating layer 114 is formed by forming an insulating layer (not shown) on the entire upper surface of the semiconductor layer 10 and performing anisotropic etching on the insulating layer. Next, source / drain regions 116 are formed. The source region / drain region 116 is formed by introducing an impurity after covering a region where the impurity is not desired to be introduced with a mask layer (not shown).

  Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

  According to the method for manufacturing a semiconductor device according to the present embodiment, the well 20 is formed before the element isolation insulating layer 22 is formed. In the formation of the well 20, heat treatment at a high temperature may be performed for a long time in order to diffuse impurities. Such a heat treatment process gives thermal stress to the element isolation insulating layer 22 in the semiconductor layer 10, which may cause current leakage due to crystal defects. In particular, as exemplified by the semiconductor device according to the present embodiment, in the case of a transistor for high voltage driving, it is necessary to form a deep well 20 in order to ensure a withstand voltage. In order to form the deep well 20, it is necessary to perform high-temperature heat treatment for a long time, and crystal defects are likely to occur due to thermal stress. However, according to the manufacturing method of the semiconductor device according to the present embodiment, the well 20 is formed before the element isolation insulating layer 22 is formed, so that the above problem can be suppressed. As a result, a semiconductor device with improved reliability can be provided.

  Further, when manufacturing the semiconductor device according to the present modification, the etching time may be set to the overetching condition in the step of removing the nitride film 14 described in the above step (6).

  In the semiconductor device manufacturing method according to the present embodiment, the case where the element isolation insulating layer 22 is formed by the STI method has been described, but the present invention is not limited to this. It may be formed by the LOCOS method or the semi-recessed LOCOS method.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment. Sectional drawing which shows typically the semiconductor device concerning this modification. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment.

Explanation of symbols

  10C ... Chip region, 10S ... Scribe region, 10 ... Semiconductor layer, 12 ... Oxide film, 14 ... Nitride film, 16 ... Trench, 20 ... Well, 22 ... Element isolation insulating layer, 24 ... Offset insulating layer, 40 ... Opening, DESCRIPTION OF SYMBOLS 100 ... Transistor, 110 ... Gate insulating layer, 112 ... Gate electrode, 114 ... Side wall insulating layer, 116 ... Source region / drain region, 118 ... Low concentration impurity layer, 200 ... Recognition mark (second recognition mark), 210 ... Recesses (first recognition marks), 212, 214, 216 ... insulating layer, 215 ... exposed surface, 217 ... upper surface

Claims (9)

(A) forming a first recognition mark of a recess in the semiconductor layer;
(B) forming a well in the semiconductor layer using the first recognition mark;
(C) forming an element isolation insulating layer on the semiconductor layer;
(D) forming a first insulating layer covering an inner surface of the first recognition mark;
(E) forming a second insulating layer for embedding the first recognition mark on the first insulating layer, and forming a second recognition mark;
(F) forming a transistor in the semiconductor layer by using the second recognition mark. A method for manufacturing a semiconductor device. In claim 1,
The method of manufacturing a semiconductor device, wherein the first recognition mark is formed in a scribe region. In claim 1 or 2,
The step (c) includes forming a groove in the semiconductor layer;
Embedding an insulating layer in the groove,
The step of embedding the insulating layer includes
A method for manufacturing a semiconductor device, which is performed simultaneously with the formation of the second insulating layer in the step (e). In any of claims 1 to 3,
The method for manufacturing a semiconductor device, wherein the first insulating layer is a nitride film, and the second insulating layer is an oxide film. A semiconductor layer having a chip region and a scribe region;
A transistor provided in the chip region;
A recognition mark provided in the scribe area,
The recognition mark is
A recess provided in the semiconductor layer;
A first insulating layer provided to cover the inner surface of the recess;
A semiconductor device comprising: a second insulating layer which is on the first insulating layer and fills the recess. In claim 5,
The exposed surface of the first insulating layer is the same as the upper surface of the semiconductor layer or at a position lower than the upper surface of the semiconductor layer,
The semiconductor device, wherein the upper surface of the second insulating layer is the same as or higher than the upper surface of the semiconductor layer. In claim 5 or 6,
The upper surface of the second insulating layer is a semiconductor device having the same height as the upper surface of the element isolation insulating layer provided in the semiconductor layer. In claim 7,
A semiconductor device in which the element isolation insulating layer is not provided in a region having a predetermined distance from an end of the recognition mark when seen in a plan view. In any one of claims 5 to 8,
The transistor is
A well provided in the semiconductor layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A channel region formed in the semiconductor layer;
A source region and a drain region provided in the semiconductor layer;
A semiconductor device comprising: the channel region; and an offset insulating layer provided between the source region and the drain region.

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