JP2006114772A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an alignment mark for realizing overlay excellent in accuracy in a photoengraving process or the like, and to provide its manufacturing method. <P>SOLUTION: The method comprises a process of forming a first layer and a second layer on a substrate; a process of forming a first trench in a component forming region and an alignment mark forming region; a process of forming a second trench by further etching the first trench of the alignment mark forming region among the first trenches, and of reducing the thickness of the second layer of the alignment mark forming region simultaneously; a process of depositing an insulating film on the second layer so that it may embed the first trench and the second trench; a process of planarizing the insulating film into a state in which the insulating film is left on the second layer of the alignment mark forming region; a process of removing the second layer of the component forming region by etching using the insulating film left on the second layer of the alignment mark forming region as an etching mask; and an insulating film removing process of removing the insulating film of the alignment mark forming region by etching. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including an alignment mark that can be accurately superimposed between a plurality of photoengraving steps, and a method for manufacturing the same.

  Generally, a semiconductor device is formed on a silicon substrate by repeating a film forming process, a photolithography process, and a processing / ion implantation process. And since such a semiconductor device has a structure in which a plurality of patterns formed in the photolithography process are laminated, it is important to perform overlaying between the photolithography processes performed multiple times with high accuracy. Become.

  Here, since many semiconductor devices first form an element isolation structure, the alignment mark formed by the element isolation structure serves as a reference for superposition of photolithography. And in order to perform superposition | superposition with a sufficient precision in a next process, it is necessary to form so that an alignment mark can be identified clearly at each process.

  An example of a case where superposition of photolithography is a problem is a process in which the underlying structure is difficult to see. Specifically, when forming a gate electrode of a transistor, metal or metal silicide may be used as an electrode material. When the metal layer is formed on the entire surface of the silicon substrate, it is difficult to optically detect the alignment mark because the metal layer reflects light. In particular, when the level difference from the silicon substrate of the base separation structure is small, the difficulty of superposition becomes greater.

  As one method of avoiding this, there is a method of providing a step by etching an insulating film used for an element isolation structure. LOCOS method (Local Oxidation of Silicon) that forms an element isolation structure by selectively oxidizing with masking a part of the substrate, or a trench is formed by etching the substrate, and an insulating film is formed in this trench After patterning the alignment mark with an STI (Shallow Trench Isolation) structure that embeds and forms element isolation, the insulating film is etched using a photoresist having an opening only in the alignment mark as a mask. It is formed. In particular, in an STI structure that can form a vertical step on a substrate, a mark with a clear step can be formed.

  As an alignment mark used in the element isolation structure as described above, an alignment mark formed in the same manner as normal element isolation (hereinafter referred to as an isolation mark) or an insulating film of the element isolation structure is etched to recess the substrate. Marks (hereinafter referred to as substrate marks). When the film laminated on these marks is an optically transparent film, superposition can be performed. On the other hand, when the film laminated on the substrate mark is an optically opaque reflective film, it is difficult to detect with a separation mark having a small step, and a structure like a substrate mark that can form a relatively large step is required. It becomes.

  The formation of the substrate mark is performed by a step of selectively removing the insulating film on the wide active region by etching (hereinafter referred to as pre-etching) when forming the STI structure. The process of forming the STI structure is roughly divided into three steps: a process of forming a trench in the substrate, a process of depositing an insulating film, and a planarization process by a CMP (Chemical Mechanical Polishing) method. When it is desired to polish the deposited insulating film as it is by CMP, a wide isolation structure region may fall into a mortar shape (hereinafter referred to as dishing). This is because, due to the influence of the CMP polishing cloth, the wide separation, particularly the central portion, is removed when the insulating film on the active region is removed.

  In order to avoid the occurrence of dishing, pre-etching is performed, the amount of polishing on the active region is reduced to suppress the occurrence of dishing, and the in-plane uniformity of the separation structure film thickness is improved. In the pre-etching, photolithography is performed using a photoresist mask having a wide active region portion, and the insulating film is etched. At this time, by opening the alignment mark part, the substrate mark structure can be formed without increasing the number of steps.

  In addition, a technique is proposed in which after a thermal oxide film and a nitride film are formed on a substrate, a groove is formed at a predetermined position of the thermal oxide film and the nitride film using a resist, and this groove is used as an alignment mark. (For example, refer to Patent Document 1). However, the alignment mark formed in this technique is a mark specialized for a photoengraving process when ion implantation is performed through a nitride film / oxide film stack, and there is a disadvantage that it cannot be used in an arbitrary process.

JP-A-7-235478

  By the way, due to the demand for CMOS circuits operating at higher speeds, increasing the driving current of MOS transistors has become an important issue. As a technique for achieving both of this large drive current and a low power supply voltage due to the demand for low power consumption, a technique for increasing carrier mobility using a special substrate is known. As an example of such a method, there is a method using a SiGe substrate in which a germanium atomic layer having a lattice spacing larger than that of a silicon crystal is arranged in a bulk portion of a silicon substrate. According to this method, the effect of widening the lattice spacing of the surface Si layer due to the presence of the SiGe layer is obtained, and as a result, the electron mobility is increased and the driving current can be increased.

  However, according to the above conventional technique, the alignment mark formed by removing the element isolation oxide film has the advantage that the alignment mark can be detected regardless of the optical characteristics of the film deposited in the subsequent process. On the other hand, when a SiGe substrate is used, the problem is that the SiGe layer is exposed on the side wall and bottom surface of the trench. That is, when the gate insulating film is formed, since the layer containing Ge is exposed, there is a possibility that the formed gate insulating film may be contaminated and the electrical characteristics of the element may be affected. In order to achieve both current drive characteristics, low power supply voltage, and high device reliability, countermeasures against germanium contamination have become a problem.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a semiconductor device provided with an alignment mark that realizes a highly accurate overlay in a photoengraving process or the like and a method for manufacturing the same.

  In order to solve the above-described problems and achieve the object, according to the semiconductor device manufacturing method of the present invention, groove-shaped element isolation is formed in the element formation region on the substrate and the alignment mark formation region on the substrate is formed. A method of manufacturing a semiconductor device, wherein a first layer forming step of forming a first layer on a substrate, a second layer forming step of forming a second layer on the first layer, A first trench forming step of etching the two layers, the first layer, and the substrate to form a first trench in the element formation region and the alignment mark formation region; and a first trench in the alignment mark formation region of the first trench Etching to form a second trench deeper than the first trench and to reduce the thickness of the second layer in the alignment mark formation region; An insulating film deposition step for depositing an insulating film on the second layer so as to fill the trench and the second trench, and a flattening process for flattening the insulating film in a state in which the insulating film remains on the second layer in the alignment mark formation region And removing the second layer of the element forming region by etching using the insulating film remaining on the second layer of the alignment mark forming region as an etching mask, and the insulating film removing the insulating film of the alignment mark forming region by etching And a removing step.

  According to the present invention, the bulk portion of the substrate is not exposed after the trench is filled with the insulating film. For this reason, when another layer such as a gate insulating film is formed thereafter, the constituent elements of the substrate do not diffuse into the gate insulating film or the like to contaminate the gate insulating film or the like. Further, according to the present invention, since the alignment mark has a physically large step, even after the formation of the alignment mark, even when an optically opaque film is formed on the upper portion, photolithography is performed a plurality of times. Overlaying between processes is performed reliably and accurately. According to the present invention, the alignment mark can be used in any photolithography process after the alignment mark is formed.

  According to the present invention, after the trench is filled with the insulating film, the bulk portion of the substrate is not exposed. Therefore, when forming another layer such as the gate insulating film, the constituent elements of the substrate become the gate insulating film or the like. The alignment mark can be formed by preventing the diffusion and contamination of the gate insulating film and the like, and effectively preventing the influence of electrical characteristics due to the contamination.

  Further, according to the present invention, since the alignment mark has a physically large step, even when an optically opaque film is formed on the alignment mark, the alignment mark is overlapped between a plurality of photolithography processes. A high-quality semiconductor device that can be reliably and accurately performed and has excellent positional accuracy can be manufactured.

  According to the present invention, the alignment mark can be used in any photolithography process after the alignment mark is formed. Therefore, according to the present invention, there is an effect that it is possible to obtain a semiconductor device provided with an alignment mark that realizes superposition with good accuracy in a photolithography process or the like and a manufacturing method thereof.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention. This semiconductor device has a circuit element region 26A and an alignment mark region 26B of a silicon germanium (SiGe) substrate 2 (hereinafter referred to as SiGe substrate 2). The circuit element region 26A is provided with a MOS transistor 10 that is a semiconductor element including the source / drain region 8, a grooved element isolation 4 that separates the MOS transistor 10 from other MOS transistors, and a wiring 14. Yes. Further, the MOS transistor 10 and the wiring 14 are separated by an interlayer insulating film 12, and the source / drain region 8 and the wiring 14 are electrically connected by a contact 16. The trench type element isolation 4 has an STI (Shallow Trench Isolation) structure, and is an element isolation formed by forming a protective film 6 on the inner wall of a trench provided in the SiGe substrate 2 and further embedding an insulating material. is there.

  In the alignment mark region 26 </ b> B, the underlying oxide film (silicon oxide film) 22 and the silicon nitride film 24 used at the time of forming the above STI structure are left without being removed, and these protrude from the surface of the SiGe substrate 2. The alignment mark 20 is formed by stacking. A protective film 6 is formed between the adjacent alignment marks 20 on the inner wall of the groove, and an insulating film 18 is embedded. Also in the alignment mark region 26 </ b> B, the interlayer insulating film 12 is formed so as to cover the alignment mark 20.

  In the semiconductor device according to the present embodiment as described above, the SiGe substrate 2 in which the germanium atomic layer having a larger lattice spacing than the silicon crystal is disposed in the bulk portion of the silicon substrate as the semiconductor substrate. As a result, the effect of widening the lattice spacing of the surface Si layer due to the presence of the SiGe layer is obtained, and as a result, the electron mobility is increased and the driving current can be increased. Therefore, a high quality semiconductor device having high current driving characteristics, low power supply voltage and high element reliability has been realized.

  Further, in the semiconductor device according to the present embodiment as described above, the bulk portion of the SiGe substrate 2 is not exposed and is buried with the insulating film 18. Thus, when forming another layer such as a gate insulating film, the other layer such as the gate insulating film is not contaminated by Ge due to the exposure of the layer containing Ge, and the function is not deteriorated. Therefore, even when the SiGe substrate 2 is used as the substrate, it is reliably prevented that the electrical characteristics of the element are affected due to Ge contamination, and both high current driving characteristics and high element reliability are achieved. A semiconductor device is realized.

  Furthermore, since the alignment mark 20 physically has a large step with respect to the surface of the SiGe substrate 2, after the alignment mark 20 is formed, an optically transparent film is naturally formed on the upper portion. Even when an opaque film is formed on the upper portion, it is possible to accurately perform overlaying between a plurality of photoengraving processes, and a high-quality semiconductor device with excellent positional accuracy is realized. .

  Next, a method for manufacturing the semiconductor device according to the present embodiment as described above will be described with reference to the drawings.

  First, as shown in FIG. 2, the SiGe substrate 2 is thermally oxidized to form an underlying oxide film 22 having a thickness of 5 nm to 50 nm, for example. Next, as shown in FIG. 3, a silicon nitride film 24 is formed on the underlying oxide film 22 to a thickness of, for example, 50 nm to 200 nm. Then, using a photoengraving technique and a dry etching technique, as shown in FIG. 4, the photoresist 30 having an opening at a portion where a trench is to be formed is patterned. Thereafter, using the photoresist 30 as a mask, the silicon nitride film 24, the underlying oxide film 22 and the SiGe substrate 2 are anisotropically etched as shown in FIG.

  After the formation of the trench 32, only the circuit element region 26A is covered with a photoresist 34 by photolithography as shown in FIG. In this state, the SiGe substrate 2 is additionally anisotropically etched to remove the photoresist 34. As a result, a trench 32 ′ deeper than the trench 32 is formed in the alignment mark region 26 B as shown in FIG. This additional anisotropic etching is performed with a recess amount of the SiGe substrate 2, for example, about 50 nm to 150 nm.

  As described above, the trench 32 ′ in the alignment mark region 26 </ b> B formed by performing additional anisotropic etching of the SiGe substrate 2 is deeper than the trench 32 formed in the circuit element region 26 </ b> A. On the other hand, the silicon nitride film 24 in the alignment mark region 26B is thinner than the silicon nitride film 24 in the circuit element region 26A by the amount reduced by the additional anisotropic etching. The amount of loss due to this additional anisotropic etching is determined by the selection ratio of the silicon nitride film 24 to the SiGe substrate 2 in the additional anisotropic etching, and thus varies depending on the film quality of the film to be used, but is about 20 nm to 200 nm as an example.

  After the formation of the trench 32 and the trench 32 ′, thermal oxidation is performed to remove the inner wall of the trench 32 and the trench 32 ′, that is, the damaged portion on the inner side surface and the bottom surface, and as shown in FIG. A protective film 36 is formed on the inner wall. The protective film 36 is formed by using, for example, a high-density plasma CVD (chemical vapor deposition) method (hereinafter referred to as HDP CVD method) when an oxide film embedding process, which is a subsequent process, is performed. Is provided to protect the SiGe substrate 2 so that the SiGe substrate 2 is not damaged by directly hitting the SiGe substrate 2 when plasma is buried. Such a protective film 36 is formed with a thickness of about 5 nm to 50 nm, for example.

  Next, using a CVD method, a silicon oxide film 38 is deposited so as to fill the trench 32 and the trench 32 'as shown in FIG. As the CVD method, for example, the HDP CVD method can be used. The film thickness A of the silicon oxide film 38 deposited here is from the surface of the protective film 36 formed on the bottom surface of the trench 32 'in the alignment mark region 26B, as shown in FIG. 9, from the silicon nitride film in the alignment mark region 26B. The film thickness is obtained by adding a slight additional amount C to the distance B to the surface of 24. However, this additional amount C needs to be at least equal to or thicker than the reduced amount of the silicon nitride film 24 in the alignment mark region 26B reduced by the additional anisotropic etching of the SiGe substrate 2 described above. This additional amount C can be set to 20 nm to 100 nm as an example.

  After the silicon oxide film 38 is deposited, the entire surface of the silicon oxide film 38 is polished using a CMP (Chemical Mechanical Polishing) method to planarize the silicon oxide film 38 as shown in FIG. In this polishing using the CMP method, the pre-etching of the silicon oxide film 38 is not performed, and when the unevenness of the silicon oxide film 38 is eliminated, the polishing is automatically stopped and a slurry that can obtain high flatness (hereinafter referred to as high planarization). It is preferable to use a slurry. By performing polishing by CMP using such a highly planarized slurry, the polishing proceeds until the surface level of the silicon oxide film 38 is aligned with the flat surface having the lowest height, and after the surface is completely flat, Polishing will not progress. As a result, it is possible to prevent the occurrence of problems such as excessive polishing of the silicon oxide film 38. The silicon oxide film 38 can be polished without using the above-described highly planarized slurry.

  The flat surface having the lowest height in the silicon oxide film 38 is an isolation region, that is, a region on the trench 32 'as shown in FIG. For this reason, when polishing by the CMP method using the highly planarized slurry, the polishing is performed with the silicon oxide film 38 having a slight film thickness C ′ remaining on the silicon nitride film 24 as shown in FIG. Stops. Here, the slight film thickness C ′ is equivalent to the additional amount C in FIG. 9 described above or slightly smaller (˜a few nm) than this.

  Next, if necessary, the silicon oxide film 38 is etched as shown in FIG. 11 to form a silicon oxide film 38 'in which the amount of protrusion from the surface of the SiGe substrate 2 is adjusted. This silicon oxide film 38 'becomes the groove type element isolation 4 in the final circuit element region 26A (see FIG. 1). Therefore, this etching is performed in order to adjust the protrusion amount of the groove type element isolation 4 from the surface of the SiGe substrate 2. The etching amount D of the silicon oxide film 38 at this time is set to an amount slightly smaller than the slight film thickness C ′ in FIG. 10 described above, so that the silicon oxide film 38 having a thickness C ″ thinner than at least the film thickness C ′ remains. To.

  Thereafter, the silicon nitride film 24 is removed by etching using the silicon oxide film 38 in the alignment mark region 26B as an etching mask as shown in FIG. At this time, since the silicon nitride film 24 in the circuit element region 26A is exposed on the surface, it is removed by etching. However, the silicon nitride film 24 in the alignment mark region 26B is not exposed on the surface and is removed by etching. Instead, it remains as shown in FIG.

  Then, after removing the silicon nitride film 24, the underlying oxide film 22 removal process, the screen oxide film formation process for ion implantation, the screen oxide film removal process after ion implantation, and the like in accordance with a conventionally known MOS transistor formation process A gate insulating film forming step is performed. As a result, as shown in FIG. 13, the silicon nitride film 24 in the alignment mark region 26B protrudes on the surface, and the alignment mark 20 having a step with the surface of the SiGe substrate 2 is formed.

  Here, the protruding amount E of the alignment mark 20 from the surface of the SiGe substrate 2 is the initial deposited film thickness of the silicon nitride film 24, the additional anisotropic etching amount of the SiGe substrate 2, and the underlying oxide film 22 and the screen oxide film. It can be controlled by setting the film thickness and the etching amount for removing them. As an example of such a protrusion amount E, it can be set to 20 nm to 100 nm, for example.

  Thereafter, according to a conventionally known MOS transistor forming process, the MOS transistor 10, the interlayer insulating film 12, the contact 16 and the wiring 14 can be formed to form the semiconductor device as shown in FIG.

  According to the semiconductor device manufacturing method according to the present embodiment as described above, after the trenches 32 and 32 ′ are filled with the silicon oxide film 38, the bulk portion of the SiGe substrate 2 (the Ge of the SiGe substrate 2 is included). Part) is not exposed. For this reason, Ge is not diffused into the gate insulating film or the like when the other layers such as the gate insulating film are formed thereafter, thereby contaminating the gate insulating film or the like. That is, even when the SiGe substrate 2 is used as the semiconductor substrate, it is possible to effectively prevent the electrical characteristics of the semiconductor element (MOS transistor 10) from being affected by Ge diffused in other layers such as a gate insulating film. Thus, the alignment mark 20 can be formed. As a result, it is possible to manufacture a high-quality semiconductor device using the SiGe substrate 2 as a semiconductor substrate and having high current drive characteristics, low power supply voltage, and high element reliability.

  In addition, since the alignment mark 20 has a physically large step, after the alignment mark 20 is formed, even when an optically opaque film is formed on the upper portion, the alignment mark 20 may be subjected to a plurality of photolithography processes. Superposition can be performed with high accuracy, and a high-quality semiconductor device with excellent positional accuracy can be manufactured.

  The alignment mark 20 formed by the semiconductor device manufacturing method according to the present embodiment has an advantage that it can be used in any photolithography process. In the conventional technology, for example, alignment marks and gate electrode materials that can be used exclusively for the photoengraving process when performing ion implantation through a nitride film / oxide film stack and the photoengraving process when forming contact holes are used. There are also alignment marks that have been removed and alignment marks that are removed during the manufacturing process. However, these alignment marks have a restriction that they can be used only in a specific photoengraving process or cannot be used in a specific photoengraving process, and have a low degree of freedom in use. However, the alignment mark according to the present embodiment exists until the manufacturing process is completed, and has an effect that it can be used in any arbitrary photoengraving process after the formation of the alignment mark. is there.

  In the present invention, after the silicon nitride film 24 is removed, the underlying oxide film 22 removal process, the screen oxide film formation process for ion implantation, and the screen after ion implantation are performed in accordance with a conventionally known CMOS transistor formation process. Subsequent to the oxide film removing step, a step of forming a thin gate insulating film / thick gate insulating film on the SiGe substrate 2 (hereinafter referred to as a dual oxide step) can also be performed.

  In the dual oxide process, a thick gate insulating film is first formed by thick gate oxidation. Subsequently, the photoresist having an opening in the thin film gate insulating film forming region is patterned, and the thick gate insulating film in the thin film gate insulating film forming region is removed using the photoresist as a mask. Then, after removing the photoresist, a thin film gate insulating film is formed by thin film gate oxidation, whereby two types of gate insulating films can be formed on the same substrate. Thereby, a semiconductor device including a plurality of semiconductor elements having different electrical characteristics can be formed.

  Here, the protruding amount E of the alignment mark 20 from the surface of the SiGe substrate 2 is the initial deposited film thickness of the silicon nitride film 24, the additional anisotropic etching amount of the SiGe substrate 2, the thickness of the underlying oxide film 22 and the screen oxide film. It can be controlled by setting the film thickness with the film gate insulating film and the etching amount when removing these. As an example of such a protrusion amount E, it can be set to 20 nm to 100 nm, for example, as described above.

  In the above description, the SiGe substrate is used as the substrate. However, the present invention is not limited to this, and the present invention can be widely applied to the case where a silicon substrate or the like is used as the substrate. .

Embodiment 2. FIG.
FIG. 14 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. This semiconductor device has a circuit element region 26C and an alignment mark region 26D of a silicon germanium (SiGe) substrate 2 (hereinafter referred to as SiGe substrate 2). The circuit element region 26C is provided with a MOS transistor 10 which is a semiconductor element including the source / drain region 8, a grooved element isolation 4 ′ for separating the MOS transistor 10 from other MOS transistors, and a wiring 14. ing. Further, the MOS transistor 10 and the wiring 14 are separated by an interlayer insulating film 12, and the source / drain region 8 and the wiring 14 are electrically connected by a contact 16. The trench type element isolation 4 ′ has an STI (Shallow Trench Isolation) structure and is formed by forming a protective film 6 on the inner wall of a trench provided in the SiGe substrate 2 and further embedding an insulating material. It is.

  In the alignment mark region 26D, the underlying oxide film (silicon oxide film) 52, the polysilicon film 54, and the silicon nitride film 56 used at the time of forming the above STI structure are left without being removed, and these remain on the SiGe substrate 2. The alignment mark 50 is formed by being stacked so as to protrude from the surface. Further, in this alignment mark 50, a bird's beak 53 formed by oxidizing the end portion of the polysilicon film 54 is formed. In the circuit element region 26C, the bird's beak is finally removed. However, the bird's beak is also present in the circuit element region 26C during the manufacturing process, and the bird's beak is separated from the groove type element isolation 4 ′. In order to prevent the end 5 from falling, the groove-type element isolation 4 ′ is formed between the SiGe substrate 2 with no gap therebetween via the protective film 6. Thereby, in this semiconductor device, the electric field concentration at the end of the active region is relaxed, and the device characteristics are excellent.

  A protective film 6 is formed between the adjacent alignment marks 20 on the inner wall of the groove, and an insulating film 18 is embedded. In the alignment mark region 26 </ b> D, the interlayer insulating film 12 is formed so as to cover the alignment mark 20. In FIG. 14 and subsequent drawings, the same reference numerals are assigned to the same members as those in FIG. 1 shown in the first embodiment for easy understanding.

  In the semiconductor device according to the present embodiment as described above, the SiGe substrate 2 in which the germanium atomic layer having a larger lattice spacing than the silicon crystal is disposed in the bulk portion of the silicon substrate as the semiconductor substrate. As a result, the effect of widening the lattice spacing of the surface Si layer due to the presence of the SiGe layer is obtained, and as a result, the electron mobility is increased and the driving current can be increased. Therefore, a high quality semiconductor device having high current driving characteristics, low power supply voltage and high element reliability has been realized.

  Further, in the semiconductor device according to the present embodiment as described above, the bulk portion of the SiGe substrate 2 is not exposed and is buried with the insulating film 18. Thus, when forming another layer such as a gate insulating film, the other layer such as the gate insulating film is not contaminated by Ge due to the exposure of the layer containing Ge, and the function is not deteriorated. Therefore, even when the SiGe substrate 2 is used as the substrate, it is reliably prevented that the electrical characteristics of the element are affected due to Ge contamination, and both high current driving characteristics and high element reliability are achieved. A semiconductor device is realized.

  Furthermore, since the alignment mark 20 physically has a large step with respect to the surface of the SiGe substrate 2, after the alignment mark 20 is formed, an optically transparent film is naturally formed on the upper portion. Even when an opaque film is formed on the upper portion, it is possible to accurately perform overlaying between a plurality of photoengraving processes, and a high-quality semiconductor device with excellent positional accuracy is realized. .

  Furthermore, in the method of manufacturing a semiconductor device according to the present embodiment, the alignment mark 50 is formed as a three-layer structure in which an underlying oxide film 52 and a silicon nitride film 56 and a polysilicon film 54 having different optical coefficients are laminated. Forming. As a result, when a semiconductor device is manufactured using the alignment mark 50, the contour of the alignment mark 50 can be detected more clearly by adjusting the wavelength, and the overlap between the photoengraving steps can be performed with higher accuracy. A high-quality semiconductor device having excellent positional accuracy can be manufactured.

  Next, a method for manufacturing the semiconductor device according to the present embodiment as described above will be described with reference to the drawings.

  First, as shown in FIG. 15, the SiGe substrate 2 is thermally oxidized to form an underlying oxide film 52 having a thickness of 5 nm to 50 nm, for example. Next, as shown in FIG. 16, a polysilicon film 54 is formed on the underlying oxide film 52 with a film thickness of 20 nm to 100 nm, for example. Further, as shown in FIG. 17, a silicon nitride film 56 is formed on the polysilicon film 54 to a thickness of, for example, 50 nm to 200 nm. Then, using a photoengraving technique and a dry etching technique, as shown in FIG. 18, the photoresist 30 having an opening at a portion where a trench is to be formed is patterned. Thereafter, using the photoresist 30 as a mask, anisotropic etching is performed on the silicon nitride film 56, the polysilicon film 54, the underlying oxide film 52 and the SiGe substrate 2 as shown in FIG.

  After the formation of the trench 58, only the circuit element region 26C is covered with the photoresist 34 by photolithography as shown in FIG. In this state, the SiGe substrate 2 is additionally anisotropically etched to remove the photoresist 34. As a result, a trench 58 ′ deeper than the trench 58 is formed in the alignment mark region 26 D as shown in FIG. This additional anisotropic etching is performed with a recess amount of the SiGe substrate 2, for example, about 50 nm to 150 nm.

  As described above, the trench 58 ′ of the alignment mark region 26D formed by performing additional anisotropic etching of the SiGe substrate 2 has a deeper trench depth than the trench 58 formed in the circuit element region 26C. On the other hand, the silicon nitride film 24 in the alignment mark region 26D is thinner than the silicon nitride film 24 in the circuit element region 26C by the amount reduced by the additional anisotropic etching. The amount of loss due to this additional anisotropic etching is determined by the selectivity of the silicon nitride film 56 with respect to the SiGe substrate 2 in the additional anisotropic etching, and therefore varies depending on the film quality of the film used, but is about 20 nm to 200 nm as an example.

  After the formation of the trench 58 and the trench 58 ', thermal oxidation is performed to remove the inner walls of the trench 58 and the trench 58', that is, the damaged portions on the inner side surface and the bottom surface, and as shown in FIG. A protective film 36 is formed on the inner wall. The protective film 36 is formed by using, for example, a high-density plasma CVD (chemical vapor deposition) method (hereinafter referred to as HDP CVD method) when an oxide film embedding process, which is a subsequent process, is performed. Is provided to protect the SiGe substrate 2 so that the SiGe substrate 2 is not damaged by directly hitting the SiGe substrate 2 when plasma is buried. Such a protective film 36 is formed with a thickness of about 5 nm to 50 nm, for example. Further, by this thermal oxidation, bird's beaks 53 are formed at the ends of the polysilicon film 54 as shown in FIG.

  Next, using a CVD method, a silicon oxide film 38 is deposited so as to fill the trench 58 and the trench 58 'as shown in FIG. As the CVD method, for example, the HDP CVD method can be used. The film thickness A of the silicon oxide film 38 deposited here is from the surface of the protective film 36 formed on the bottom surface of the trench 58 'in the alignment mark region 26D, as shown in FIG. 23, to the silicon nitride film in the alignment mark region 26D. The film thickness is obtained by adding a slight additional amount C to the distance B to the surface of 56. However, this additional amount C needs to be at least equal to or thicker than the reduced amount of the silicon nitride film 56 in the alignment mark region 26D reduced by the additional anisotropic etching of the SiGe substrate 2 described above. This additional amount C can be set to 20 nm to 100 nm as an example.

  After the silicon oxide film 38 is deposited, the entire surface of the silicon oxide film 38 is polished by CMP to planarize the silicon oxide film 38 as shown in FIG. In the polishing using this CMP method, the pre-etching of the silicon oxide film 38 is not performed as in the case of the above-described embodiment, and when the unevenness of the silicon oxide film 38 is eliminated, the polishing is auto-stopped and has high flatness. It is preferable to use a slurry that can be obtained (hereinafter referred to as a highly planarized slurry). By performing polishing by CMP using such a highly planarized slurry, the polishing proceeds until the surface level of the silicon oxide film 38 is aligned with the flat surface having the lowest height, and after the surface is completely flat, Polishing will not progress. As a result, it is possible to prevent the occurrence of problems such as excessive polishing of the silicon oxide film 38. The silicon oxide film 38 can be polished without using the above-described highly planarized slurry.

  The flat surface having the lowest height in the silicon oxide film 38 is an isolation region, that is, a region on the trench 58 'as shown in FIG. For this reason, when polishing by the CMP method using the highly planarized slurry, the polishing is performed with the silicon oxide film 38 having a slight film thickness C ′ remaining on the silicon nitride film 56 as shown in FIG. Stops. Here, the slight film thickness C ′ is equivalent to the additional amount C in FIG. 23 described above or slightly smaller (˜a few nm) than this.

  Next, if necessary, the silicon oxide film 38 is etched as shown in FIG. 25 to form a silicon oxide film 38 'in which the amount of protrusion from the surface of the SiGe substrate 2 is adjusted. This silicon oxide film 38 'becomes the trench type element isolation 4' in the final circuit element region 26C. Therefore, this etching is performed in order to adjust the protrusion amount of the groove type element isolation 4 from the surface of the SiGe substrate 2. At this time, the etching amount D of the silicon oxide film 38 is set to be smaller than the film thickness C ′ in FIG. 24 described above so that the silicon oxide film 38 having a thickness C ″ thinner than the film thickness C ′ remains. .

  Thereafter, as shown in FIG. 26, the silicon nitride film 56 and the polysilicon film 54 are removed by etching using the silicon oxide film 38 in the alignment mark region 26D as an etching mask. As a result, the silicon oxide film 38 ″ is exposed. At this time, since the silicon nitride film 56 in the circuit element region 26C is exposed on the surface, the silicon nitride film 56 in the alignment mark region 26D is removed by etching. Therefore, it remains as it is as shown in FIG. 26 without being removed by etching.

  Then, after removing the silicon nitride film 56, the underlying oxide film 52 removal process, the screen oxide film formation process for ion implantation, the screen oxide film removal process after ion implantation, and the like in accordance with a conventionally known MOS transistor formation process, A gate insulating film forming step is performed. As a result, as shown in FIG. 27, the silicon nitride film 56 in the alignment mark region 26D protrudes on the surface, and the alignment mark 50 having a step with the surface of the SiGe substrate 2 is formed.

  Here, the protrusion amount E of the alignment mark 50 from the surface of the SiGe substrate 2 is the initial deposited film thickness of the silicon nitride film 56, the additional anisotropic etching amount of the SiGe substrate 2, and the underlying oxide film 52 and the screen oxide film. It can be controlled by setting the film thickness and the etching amount for removing them. As an example of such a protrusion amount E, it can be set to 20 nm to 100 nm, for example.

  Further, as shown in FIG. 27, at the separation end 5 of the groove type element isolation 4 ′, the groove type element isolation 4 ′ is formed between the SiGe substrate 2 via the protective film 6 without a gap. In the manufacturing method according to the first embodiment described above, there is a gap between the groove type element isolation 4 and the SiGe substrate 2 at the separation end 7 of the groove type element isolation 4 as shown in FIG. . However, in the present embodiment, there is a bird's beak 53 in the circuit element region 26C, and this bird's beak prevents the separation end 5 of the groove-type element isolation 4 'from falling, so that the groove-type as shown in FIG. The groove-type element isolation 4 ′ can be formed without leaving a gap between the groove-type element isolation 4 ′ and the SiGe substrate 2 at the separation end 5 of the element isolation 4 ′. Thereby, the electric field concentration at the edge of the active region is relaxed, and a semiconductor device having good element characteristics can be manufactured.

  Thereafter, according to a conventionally known MOS transistor forming process, the MOS transistor 10, the interlayer insulating film 12, the contact 16 and the wiring 14 can be formed to form a semiconductor device as shown in FIG.

  According to the semiconductor device manufacturing method according to the present embodiment as described above, after the trenches 32 and 32 ′ are filled with the silicon oxide film 38, the bulk portion of the SiGe substrate 2 (the Ge of the SiGe substrate 2 is included). Part) is not exposed. For this reason, Ge is not diffused into the gate insulating film or the like when the other layers such as the gate insulating film are formed thereafter, thereby contaminating the gate insulating film or the like. That is, even when the SiGe substrate 2 is used as the semiconductor substrate, it is possible to effectively prevent the electrical characteristics of the semiconductor element (MOS transistor 10) from being affected by Ge diffused in other layers such as a gate insulating film. Thus, the alignment mark 20 can be formed. As a result, it is possible to manufacture a high-quality semiconductor device using the SiGe substrate 2 as a semiconductor substrate and having high current drive characteristics, low power supply voltage, and high element reliability.

  In addition, since the alignment mark 20 has a physically large step, after the alignment mark 20 is formed, even when an optically opaque film is formed on the upper portion, the alignment mark 20 may be subjected to a plurality of photolithography processes. Superposition can be performed with high accuracy, and a high-quality semiconductor device with excellent positional accuracy can be manufactured.

  The alignment mark 20 formed by the semiconductor device manufacturing method according to the present embodiment has an advantage that it can be used in any photolithography process. In the conventional technology, for example, alignment marks and gate electrode materials that can be used exclusively for the photoengraving process when performing ion implantation through a nitride film / oxide film stack and the photoengraving process when forming contact holes are used. There are also alignment marks that have been removed and alignment marks that are removed during the manufacturing process. However, these alignment marks have a restriction that they can be used only in a specific photoengraving process or cannot be used in a specific photoengraving process, and have a low degree of freedom in use. However, the alignment mark according to the present embodiment exists until the manufacturing process is completed, and has an effect that it can be used in any arbitrary photoengraving process after the formation of the alignment mark. is there.

  Furthermore, in the method of manufacturing a semiconductor device according to the present embodiment, the alignment mark 50 is formed as a three-layer structure in which an underlying oxide film 52 and a silicon nitride film 56 and a polysilicon film 54 having different optical coefficients are laminated. Forming. As a result, when a semiconductor device is manufactured using the alignment mark 50, the contour of the alignment mark 50 can be detected more clearly by adjusting the wavelength, and the overlap between the photoengraving steps can be performed with higher accuracy. A high-quality semiconductor device having excellent positional accuracy can be manufactured.

  In the present invention, after the silicon nitride film 56 is removed, the polysilicon film 54 and the underlying oxide film 52 are removed in accordance with a conventionally known MOS transistor forming process, a screen oxide film forming process for ion implantation, Subsequent to the screen oxide film removing step after ion implantation, a step of forming a thin gate insulating film / thick gate insulating film on the SiGe substrate 2 (hereinafter referred to as a dual oxide step) may be performed.

  In the dual oxide process, a thick gate insulating film is first formed by thick gate oxidation. Subsequently, the photoresist having an opening in the thin film gate insulating film forming region is patterned, and the thick gate insulating film in the thin film gate insulating film forming region is removed using the photoresist as a mask. Then, after removing the photoresist, a thin film gate insulating film is formed by thin film gate oxidation, whereby two types of gate insulating films can be formed on the same substrate. Thereby, a semiconductor device including a plurality of semiconductor elements having different electrical characteristics can be formed.

  Here, the protrusion amount E of the alignment mark 50 from the surface of the SiGe substrate 2 is the initial deposited film thickness of the silicon nitride film 56, the additional anisotropic etching amount of the SiGe substrate 2, the thickness of the underlying oxide film 52, the screen oxide film, and the like. It can be controlled by setting the film thickness with the film gate insulating film and the etching amount when removing these. As an example of such a protrusion amount E, it can be set to 20 nm to 100 nm, for example, as described above.

  In the above description, the SiGe substrate is used as the substrate. However, the present invention is not limited to this, and the present invention can be widely applied to the case where a silicon substrate or the like is used as the substrate. .

Embodiment 3 FIG.
In the third embodiment, a modified example of the semiconductor device described in the first embodiment will be described. FIG. 29 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the third embodiment of the present invention.

  This semiconductor device has a circuit element region 26C, an alignment mark region 26D, and an alignment mark region 26C of a silicon germanium (SiGe) substrate 2 (hereinafter referred to as SiGe substrate 2). The configurations of the circuit element region 26C and the alignment mark region 26D are the same as those shown in FIG. 1 in the first embodiment.

  The semiconductor device shown in FIG. 29 is different from the semiconductor device shown in FIG. 1 in that an alignment mark region 26C having an alignment mark 70 having an STI structure is provided. The alignment mark 70 having this STI structure can be formed simultaneously with the groove type element isolation 4 by the same process as the groove type element isolation 4 in the circuit element region 26A. Therefore, it can be formed without increasing the number of steps.

  By adopting such a configuration, this semiconductor device has the effects described in the first embodiment. Further, in this semiconductor device, the alignment mark 20 and the alignment mark 70 having the STI structure can be used properly in the photolithography process after the optically transparent film is formed. Since the alignment mark 70 has a simple configuration that does not use a laminated film, a situation such as a blurred outline of the alignment mark does not occur and can be detected with high accuracy. Therefore, the alignment between the photoengraving process can be performed with higher accuracy by using the alignment mark 20 and the alignment mark 70 properly for each photoengraving process, such as using an alignment mark with high detection accuracy according to the work process. It is possible to manufacture a high-quality semiconductor device with excellent positional accuracy.

Embodiment 4 FIG.
In the third embodiment, a modification of the semiconductor device described in the second embodiment will be described. FIG. 30 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the fourth embodiment of the present invention.

  This semiconductor device has a circuit element region 26C, an alignment mark region 26D, and an alignment mark region 26E of a silicon germanium (SiGe) substrate 2 (hereinafter referred to as SiGe substrate 2). The configurations of the circuit element region 26C and the alignment mark region 26D are the same as those shown in FIG. 14 in the second embodiment.

  The semiconductor device shown in FIG. 30 is different from the semiconductor device shown in FIG. 14 in that an alignment mark region 26E having an STI structure alignment mark 80 is provided. The alignment mark 80 having the STI structure can be formed simultaneously with the groove type element isolation 4 ′ by the same process as the groove type element isolation 4 ′ in the circuit element region 26C. Therefore, it can be formed without increasing the number of steps.

  By adopting such a configuration, this semiconductor device has the effects described in the second embodiment. Further, in this semiconductor device, the alignment mark 20 and the STI structure alignment mark 80 can be used properly in the photolithography process after the optically transparent film is formed. Since the alignment mark 80 has a simple configuration that does not use a laminated film, the alignment mark 80 can be accurately detected without causing a situation such as a blurred outline of the alignment mark. Therefore, by using the alignment mark 20 and the alignment mark 80 separately for each photoengraving process, such as using an alignment mark with high detection accuracy according to the work process, superimposing between the photoengraving processes with higher accuracy. It is possible to manufacture a high-quality semiconductor device with excellent positional accuracy.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device having a photolithography process, and in particular, includes a plurality of semiconductor elements having different electrical characteristics on the same substrate, and photolithography. It is suitable for manufacturing a semiconductor device that uses many processes.

It is sectional drawing which shows schematic structure of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows schematic structure of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows schematic structure of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing which shows schematic structure of the semiconductor device concerning Embodiment 4 of this invention.

Explanation of symbols

2 Silicon substrate 4 Groove type element isolation 4 'Groove type element isolation 5 Separation end of groove type element isolation 4' 6 Protective film 7 Separation end of groove type element isolation 4 8 Source / drain region 10 Semiconductor element 12 Interlayer insulating film 14 Wiring 16 Contact 18 Insulating film 20 Alignment mark 22 Underlay oxide film 24 Silicon nitride film 26A Circuit element region 26B Alignment mark area 30 Photoresist 32 Trench 32 'Trench 34 Photoresist 36 Protective film 38 Silicon oxide film 50 Alignment mark 52 Underlay oxide film 53 Bird's beak 54 Polysilicon film 56 Silicon nitride film 58 Trench 58 'Trench 70 STI structure alignment mark 80 STI structure alignment mark

Claims (17)

A method for manufacturing a semiconductor device, wherein groove-shaped element isolation is formed in an element formation region on a substrate and an alignment mark is formed in the alignment mark formation region on the substrate,
A first layer forming step of forming a first layer on the substrate;
A second layer forming step of forming a second layer on the first layer;
A first trench formation step of etching the second layer, the first layer, and the substrate to form a first trench in the element formation region and the alignment mark formation region;
The first trench in the alignment mark formation region of the first trench is further etched to form a second trench deeper than the first trench, and the thickness of the second layer in the alignment mark formation region is reduced. A second trench forming step;
An insulating film deposition step of depositing an insulating film on the second layer so as to fill the first trench and the second trench;
A planarization step of planarizing the insulating film in a state in which the insulating film remains on the second layer in the alignment mark formation region;
A removal step of etching and removing the second layer in the element formation region using the insulating film remaining on the second layer in the alignment mark formation region as an etching mask;
An insulating film removing step of etching away the insulating film in the alignment mark forming region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first layer is an oxide film, and the second layer is a nitride film. 2. The semiconductor device according to claim 1, further comprising a thermal oxidation step of thermally oxidizing inner walls of the first trench and the second trench between the second trench formation step and the insulating film deposition step. Production method. The adjusting step of adjusting the height of the insulating film by etching the insulating film in the element formation region is included between the planarizing step and the second layer removing step. The manufacturing method of the semiconductor device of description. A method for manufacturing a semiconductor device, wherein groove-shaped element isolation is formed in an element formation region on a substrate and an alignment mark is formed in the alignment mark formation region on the substrate,
A first layer forming step of forming a first layer on the substrate;
A second layer forming step of forming a second layer on the first layer;
A third layer forming step of forming a third layer on the second layer;
A first trench formation step of etching the third layer, the second layer, the first layer, and the substrate to form a first trench in the element formation region and the alignment mark formation region;
The first trench in the alignment mark formation region of the first trench is further etched to form a second trench deeper than the first trench, and the thickness of the second layer in the alignment mark formation region is reduced. A second trench forming step;
An insulating film deposition step of depositing an insulating film on the third layer so as to fill the first trench and the second trench;
A planarization step of planarizing the insulating film in a state where the insulating film remains on the third layer in the alignment mark formation region;
A removal step of etching and removing the third layer and the second layer in the element formation region using the insulating film remaining on the third layer in the alignment mark formation region as an etching mask;
An insulating film removing step of etching away the insulating film in the alignment mark forming region;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the first layer is an oxide film, the second layer is a polysilicon film, and the third layer is a nitride film. The semiconductor device according to claim 5, further comprising a thermal oxidation step of thermally oxidizing inner walls of the first trench and the second trench between the second trench formation step and the insulating film deposition step. Production method. The semiconductor according to claim 5, further comprising an adjusting step of adjusting the height of the insulating film by etching the insulating film in the element formation region between the planarizing step and the removing step. Device manufacturing method. Groove-type element isolation is formed in the element formation region on the substrate, and alignment marks having the same structure as the groove-type element isolation are formed in the first alignment mark formation region and the second alignment mark formation region on the substrate. A method for manufacturing a semiconductor device, comprising:
A first layer forming step of forming a first layer on the substrate;
A second layer forming step of forming a second layer on the first layer;
Etching the second layer, the first layer, and the substrate to form a first trench in the element formation region, the first alignment mark formation region, and the second alignment mark formation region;
The first trench in the first alignment mark formation region of the first trench is further etched to form a second trench deeper than the first trench, and the second layer in the first alignment mark formation region is formed. A second trench forming step for reducing the thickness;
An insulating film deposition step of depositing an insulating film on the second layer so as to fill the first trench and the second trench;
A planarization step of planarizing the insulating film in a state in which the insulating film remains on the second layer in the first alignment mark formation region;
A removal step of etching and removing the element formation region and the second layer of the second alignment mark formation region using the insulating film remaining on the second layer of the first alignment mark formation region as an etching mask;
An insulating film removing step of etching away the insulating film in the alignment mark forming region;
A method for manufacturing a semiconductor device, comprising: Groove-type element isolation is formed in the element formation region on the substrate, and alignment marks having the same structure as the groove-type element isolation are formed in the first alignment mark formation region and the second alignment mark formation region on the substrate. A method for manufacturing a semiconductor device, comprising:
A first layer forming step of forming a first layer on the substrate;
A second layer forming step of forming a second layer on the first layer;
A third layer forming step of forming a third layer on the second layer;
Forming a first trench by etching the third layer, the second layer, the first layer, and the substrate to form a first trench in the element formation region, the first alignment mark formation region, and the second alignment mark formation region Process,
The first trench in the alignment mark formation region of the first trench is further etched to form a second trench deeper than the first trench, and the thickness of the second layer in the alignment mark formation region is reduced. A second trench forming step;
An insulating film deposition step of depositing an insulating film on the third layer so as to fill the first trench and the second trench;
A planarization step of planarizing the insulating film in a state where the insulating film remains on the third layer in the alignment mark formation region;
A removal step of etching and removing the element formation region and the third layer and the second layer of the second alignment mark formation region using the insulating film remaining on the third layer of the alignment mark formation region as an etching mask;
An insulating film removing step of etching away the insulating film in the alignment mark forming region;
A method for manufacturing a semiconductor device, comprising: A semiconductor device in which a semiconductor element is separated by groove-type element separation,
A substrate,
A semiconductor element provided on the substrate;
Trench-type element isolation for element isolation of the semiconductor element;
A plurality of layers are laminated on the substrate, and an alignment mark provided in a state protruding from the substrate surface;
A semiconductor device comprising:   The semiconductor device according to claim 11, wherein the alignment mark is an alignment mark used in a photolithography process.   The semiconductor device according to claim 12, wherein the substrate is a silicon germanium substrate.   13. The semiconductor device according to claim 12, wherein the alignment mark is formed by stacking an oxide film and a nitride film on the substrate in this order. The semiconductor device according to claim 14, further comprising another alignment mark in which an insulating film is embedded in a trench provided in the substrate.   The semiconductor device according to claim 12, wherein the alignment mark is formed by stacking an oxide film, a polysilicon film, and a nitride film on the substrate in this order. The semiconductor device according to claim 16, further comprising another alignment mark in which an insulating film is embedded in a trench provided in the substrate.

Images