KR20060105894A - Method for fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein an alignment key is formed in a key region during a hard mask film and a pad nitride film etching process for defining a field region in a cell region, and the alignment key A trench active layer is formed at the same depth as the peri region in the key region except for to form a trench depth of the key region and the cell region differently, and then a reverse active mask for reducing the CMP target thickness of the cell region. The key region is opened together during the process to expose the alignment key of the key region during the process to recess the insulating film of the cell region. Therefore, the key open mask process and the etching process for exposing the alignment key can be omitted, thereby simplifying the process and improving the productivity of the semiconductor device.

Key area, reverse active mask, key open mask

Description

Method for fabricating semiconductor device {Method for fabricating semiconductor device}

1A to 1G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11 pad nitride film

12: hard mask film 13: alignment key

14: first trench 15: second trench

16: third trench 17: gap fill insulating film

18: mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for simplifying a process and improving productivity by merging a reverse active mask and a key open mask. .

In general, semiconductor devices include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices are highly integrated and miniaturized, research on not only the size of each individual device but also the size of the device isolation region has been actively conducted. The reason for this is that the formation of device isolation regions is an initial stage of manufacturing all semiconductor devices, and depends on the size of the active region and the process margin of the post-processing stage.

Until recently, the LOCOS device isolation method, which is widely used in the manufacture of semiconductor devices, forms a device isolation region having a relatively large area, and thus has reached its limit as semiconductor devices are highly integrated. Accordingly, a technique suitable for device isolation of highly integrated semiconductor devices is to form a trench by etching a portion of the substrate, fill the trench, and then planarize the top surface by using a chemical mechanical polishing (CMP) method. A trench device isolation method has been proposed to separate the.

On the other hand, semiconductor devices that require high voltage, such as flash memory devices, include a cell region in which data is stored and a peri region in which a high voltage circuit is to be formed, and the peripheral region is a cell region. In addition, the device isolation film in the peripheral area should be larger in width and depth than the device isolation film in the cell area. In order to satisfy these characteristics, a dual trench isolation structure in which a device isolation film in a peripheral region is formed deeper than a device isolation film in a cell region is introduced.

In the dual trench isolation structure, since the cell region has a thicker target thickness of the CMP process after the trench filling than the peripheral region, the uniformity of the CMP process is reduced. Accordingly, a method of reducing the thickness of the CMP target of the cell region is used by using a reverse active mask that opens the cell region.

On the other hand, the trench isolation technology has a problem that the semiconductor device is highly integrated, so that the shallow trench isolation and perfect planarization during the STI process cannot read the alignment key of the scribe lane in the gate mask process. . In order to solve this problem, in the related art, an etching process is further performed by using a key open mask that opens a key region in which an alignment key is separately formed.

Therefore, there is a problem in that the process is increased by using two masks, a reverse active mask and a key open mask, thereby increasing the process steps and lowering the productivity of the semiconductor device.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the number of mask processes and etching processes, which are devised to solve the above-described problems of the prior art.

Another object of the present invention is to simplify the process and improve productivity.

A method of manufacturing a semiconductor device according to the present invention includes the steps of (a) forming a pad nitride film and a hard mask film on a semiconductor substrate having a cell region, a peripheral region and a key region, and (b) selecting the hard mask film and the pad nitride film. Etching to expose the semiconductor substrate of the field portion in the cell region and forming an alignment key in the key region; and (c) forming a first mask covering the active portion of the peripheral region, the cell region, and the alignment key. (D) etching the hard mask layer, the pad nitride layer, and the semiconductor substrate using the first mask to form a first trench, and removing the first mask; and (e) removing the hard mask. Etching a semiconductor substrate with a mask to form a second trench in the cell region, and a third trench having a depth deeper than the second trench in the peripheral region and the key region Forming a tooth; (f) forming a gap fill insulating film filling the second and third trenches on the front surface; and (g) recessing the gap fill insulating film between the cell region and the key region to form the alignment key. Exposing and (h) planarizing the entire surface.

Preferably, the step (g) includes forming a second mask exposing the cell region and the key region, and using the second mask to form a surface height of the insulating layer formed in the cell region in the peripheral region. And recessing the insulating films of the cell region and the key region to be equal to the surface height of the substrate, and removing the second mask.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1G are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, a pad nitride film 11 and a hard mask film 12 are formed on a semiconductor substrate 10 including a cell region, a peri region, and a key region.

Then, the hard mask layer 12 and the pad nitride layer 11 are selectively etched by a photolithography process to divide the cell region into a field portion and an active portion, and the pad nitride layer 11 and the hard mask layer in the key region. An alignment key 13 made of the laminated film of (12) is formed.

In this case, a portion where the pad nitride layer 11 and the hard mask layer 12 remain in the cell region is an active portion, and a portion where the pad nitride layer 11 and the hard mask layer 12 is removed is a field portion.

Then, a photoresist PR is applied to the entire surface as shown in FIG. 1B, and an exposure and development process is carried out so as to remain on the active portion of the cell region and the peripheral region, the alignment key 13 and the adjacent key region. The photoresist PR is patterned.

Next, as shown in FIG. 1C, the hard mask layer 12, the pad nitride layer 11, and the semiconductor substrate 10 are etched using the photoresist PR as a mask to form first portions in the peripheral region and the key region. After the trench 14 is formed, the photoresist PR is removed.

At this time, the depth of the first trench 14 is a value corresponding to the difference between the depth of the trench to be formed in the peripheral region and the depth of the trench to be formed in the cell region, and is preferably about 1700 Å.

Subsequently, as shown in FIG. 1D, the semiconductor substrate 10 is etched with a predetermined depth using the hard mask layer 12 as a mask to form a second trench 15 in the cell region, and the second region in the peripheral region and the key region. A third trench 16 having a depth deeper than the second trenches 15 by the first trenches 14 is formed. The predetermined depth is a depth corresponding to the depth of the second trenches 15 formed in the cell region.

Then, as shown in FIG. 1E, the gap fill insulating film 17 is deposited on the entire surface so that the second and third trenches 15 and 16 are completely filled.

The gap fill insulating layer 17 may include HDP (High Density Plasma), HARP (High Aspect Ratio planarization), O3-TEOS (Tetra Ethyl Ortho Silicate), SOG, Sipn On Glass Chemical Vapor Deposition (CVD) oxide, APCVD (Atmospheric Pressure) CVD) oxide film is used.

At this time, due to the difference in depth between the second trench 15 and the third trench 16, a thick gap fill insulating film 17 is formed on the surface of the semiconductor substrate 10 in the cell region, while surroundings are formed. On the surface of the semiconductor substrate 10 in the region and the key region, a relatively thin gap fill insulating film 17 is formed. Such a difference in thickness of the gap fill insulating layer 17 between the cell region and the peripheral region causes a nonuniformity of the CMP process to be performed later.

The mask 18 for opening the cell region and the key region is formed to solve the non-uniformity problem of the CMP process and to reveal the alignment key of the key region. The mask 18 is a combination of a reverse active mask for planarization of a CMP process and a key open mask for opening an alignment key, and are formed on a peripheral area.

Then, as shown in FIG. 1F, the gap fill insulating layer 17 of the cell region and the key region is etched using the mask 18 so that the CMP target thickness of the cell region is equal to the CMP target thickness of the peripheral region. Recess

In this case, since the thickness of the gap fill insulating layer 17 of the key region is thinner than the thickness of the gap fill insulating layer 17 of the cell region, the alignment key 13 is exposed.

Thereafter, the mask 18 is removed, and the gap fill insulating layer 17 is etched by the CMP process of targeting the hard mask layer 12, as shown in FIG. 1G, to form the second and third trenches 15. A device isolation film 17a is formed in the () 16.

This completes the manufacture of the semiconductor device according to the embodiment of the present invention.

Therefore, the present invention has the following effects.

First, the mask process can be reduced by merging a reverse active mask and a key open mask.

Second, since the alignment key is opened during the etching process for matching the CMP target thickness of the cell region and the surrounding region, the separate etching process for opening the alignment key does not have to be performed, thereby reducing the number of etching processes.

Third, since the mask process and the etching process can be reduced, TAT (Turn Around Time) can be improved and production cost can be reduced.

Claims (2)

(a) forming a pad nitride film and a hard mask film on a semiconductor substrate having a cell region, a peripheral region, and a key region; (b) selectively etching the hard mask layer and the pad nitride layer to expose a semiconductor substrate in a field portion in the cell region and to form an alignment key in the key region; (c) forming a first mask covering an active portion of the peripheral area, the cell area, and the alignment key; (d) etching the hard mask layer, the pad nitride layer, and the semiconductor substrate using the first mask to form a first trench and to remove the first mask; (e) etching the semiconductor substrate using the hard mask as a mask to form a second trench in the cell region, and forming a third trench having a depth deeper than the second trench in the peripheral region and the key region; (f) forming a gap fill insulating film filling the second and third trenches on the entire surface; (g) recessing a gapfill insulating film between the cell region and the key region to expose the alignment key; And (h) planarizing the entire surface. The method of claim 1, Step (g) may include forming a second mask exposing the cell region and the key region; Recessing the insulating films of the cell region and the key region using the second mask such that the surface height of the insulating film formed in the cell region is the same as the surface height of the insulating film formed in the peripheral region; And removing the second mask.

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