JP2007123338A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for reducing the occurrence of crystal defects, or the like occurring from an element separation region. <P>SOLUTION: The semiconductor device comprises a process (a) for forming a first recognition mark comprising a first groove 210 on a semiconductor layer 10; a process (b) for forming a well 20 on the semiconductor layer by the first recognition mark 210; a process (c) for forming a mask layer M1 that contains at least the first recognition mark, and has a first opening 42 in a plane shape that is larger than the plane shape of the first recognition mark on the semiconductor layer; a process (d) for forming a second recognition mark comprising a second groove by etching the semiconductor layer by the mask layer M1; a process (e) for forming an element separation insulating layer 22 on the semiconductor layer; and a process (f) for forming a transistor 100 on the semiconductor layer by the second recognition mark. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In a method of manufacturing a semiconductor device having an element isolation region, particularly a high voltage transistor, an impurity is introduced into an element formation region other than the element isolation region after the element isolation region is formed in a semiconductor substrate as in Patent Document 1, for example. By performing heat treatment for a long time at high temperature, the well is formed by uniformly diffusing impurities into a desired region in the semiconductor substrate.
JP 2004-260073 A

However, in the above manufacturing method, thermal stress may be applied to the element isolation region due to the heat treatment when forming the well in the semiconductor substrate in which the element isolation region is formed. As a result, for example, since the thermal expansion coefficient of the material forming the element isolation region is different from that of the semiconductor substrate, a crystal defect is formed due to the stress, and there is a possibility that a current leakage due to the defect occurs. is there.

An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device for reducing the occurrence of crystal defects and the like generated from an element isolation region.

(1) A manufacturing method of a semiconductor device according to the present invention includes:
(A) forming a first recognition mark comprising a first groove in the semiconductor layer;
(B) forming a well in the semiconductor layer using the first recognition mark;
(C) forming a mask layer including at least a first recognition mark on the semiconductor layer and having a first opening having a planar shape larger than the planar shape of the first recognition mark;
(D) forming a second recognition mark comprising a second groove by etching the semiconductor layer using the mask layer;
(E) forming an element isolation insulating layer on the semiconductor layer;
(F) forming a transistor in the semiconductor layer using the second recognition mark.

  According to the method for manufacturing a semiconductor device of the present invention, the well is formed using the first recognition mark formed in the semiconductor layer, and then the element isolation insulating layer is formed. In the formation of the well, thermal stress may be applied to the semiconductor layer in a heat treatment process for diffusing impurities into the semiconductor substrate. According to the method for manufacturing a semiconductor device according to the present invention, since the element isolation insulating layer is not formed before the well is formed, it is possible to suppress the occurrence of crystal defects or the like due to thermal stress in the element isolation insulating layer. . As a result, defects due to current leakage caused by crystal defects and the like can be reduced, and a semiconductor device with improved reliability can be manufactured.

  In addition, the manufacturing method of the semiconductor device concerning this invention can take the following aspect further.

(2) In the method for manufacturing a semiconductor device according to the present invention,
The first recognition mark may be formed in a scribe area.

(3) In the method for manufacturing a semiconductor device according to the present invention,
In the step (c), the mask layer has a second opening above a region where the element isolation insulating layer is formed,
In the step (d), a third groove can be further formed.

(4) In the method for manufacturing a semiconductor device according to the present invention,
The step (e) may include embedding an insulating layer in the third groove.

(5) A semiconductor device according to the present invention includes:
A semiconductor layer having a chip region and a recognition mark region;
A transistor provided in the chip region;
A recognition mark provided in the recognition mark area,
The recognition mark is
A groove provided in the semiconductor layer has a first bottom surface and a second bottom surface having a different depth from the first bottom surface.

  The semiconductor device according to the present invention can further take the following aspects.

(6) In the semiconductor device according to the present invention,
An insulating layer may be formed in the groove.

(7) In the semiconductor device according to the present invention,
The bottom surface of the element isolation insulating layer provided in the chip region and the second bottom surface may have the same depth.

(8) In the semiconductor device according to the present invention,
The transistor is
A well provided in the semiconductor layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A channel region formed in the semiconductor layer;
A source region and a drain region provided in the semiconductor layer;
The channel region may include an offset insulating layer provided between the source region and the drain region.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

1. Semiconductor Device First, a semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment.

  The semiconductor device according to the present embodiment includes a semiconductor layer 10 as shown in FIG. The semiconductor layer 10 has a chip region 10C and a recognition mark region 10S. The chip region 10C is a region where various semiconductor devices constituting the IC chip are formed. The chip region 10 </ b> C and the recognition mark region 10 </ b> S can each be surrounded by the element isolation insulating layer 22. Further, the recognition mark area 10S may be included in the scribe area. In this case, the scribe region is provided around one semiconductor chip and includes a dicing area for dicing the semiconductor chip.

  As shown in FIG. 1, the transistor 100 is formed in the chip region 10C. The transistor 100 is a transistor for high drive voltage operation. The transistor 100 includes a gate insulating layer 110, a gate electrode 112, a sidewall insulating layer 114, and a source region 116 and a drain region 116 (hereinafter referred to as a source region / drain region) which are high-concentration impurity layers. ”, An offset insulating layer 24, a low-concentration impurity layer 118, and a well 20.

  The gate insulating layer 110 is provided on the semiconductor layer 10 and on the channel region in the well 20. The gate electrode 112 is formed on the gate insulating layer 110. The sidewall insulating layer 114 is formed on the side of the gate electrode 112.

  The source / drain region 116 is formed in the upper part in the low concentration impurity layer 118. In the source region / drain region 116, the impurity concentration can be made higher than that in the low concentration impurity layer 118. The offset insulating layer 24 is formed to be embedded in the upper surface side of the semiconductor layer 10. The offset insulating layer 24 is formed between the source region 116 and the channel region under the gate insulating layer 110 and between the drain region 116 and the channel region under the gate insulating layer 110. The offset insulating layer 24 is included in the low concentration impurity layer 118.

  The low concentration impurity layer 118 is formed in the upper portion of the well 20. The low concentration impurity layer 118 overlaps with all of the source region / drain region 116 and is formed deeper than the source region / drain region 116. That is, the low concentration impurity layer 118 includes the source region / drain region 116. The well 20 is formed in the upper part in the semiconductor layer 10.

  In the semiconductor device according to the present embodiment, the case where only the high drive voltage transistor 100 is provided in the chip region 10C is illustrated. However, a plurality of transistors having different drive voltages are provided in the chip region. Needless to say, it may be.

  A recognition mark 200 is formed in the recognition mark area 10S. The recognition mark 200 is used, for example, for aligning the semiconductor layer 10 and the mask in the process of forming the transistor 100 or the like. The recognition mark 200 can have various plane patterns depending on the alignment method.

  The recognition mark 200 included in the semiconductor device according to the present embodiment is a groove including a first bottom surface 202 and a second bottom surface 204 that is shallower than the first bottom surface 202. That is, the first bottom surface 202 and the second bottom surface 204 form a step. This step serves as a recognition mark. The second bottom surface 204 can be at the same position as the bottom surface of the element isolation insulating layer 22. An insulating layer 206 is provided in the recognition mark 200.

  According to the semiconductor device according to the present embodiment, once the recognition mark 200 is formed, the shape is maintained even after a plurality of steps performed after the formation of the recognition mark 200. Become. Therefore, the recognition mark 200 included in the semiconductor device according to the present embodiment can be suitably used as a recognition mark even in a process after the formation of the element isolation insulating layer 22. In addition, an insulating layer 206 made of one kind of material is formed in the recognition mark 200. A plurality of types of materials such as a silicon nitride film and a silicon oxide layer may be embedded in the groove formed in the semiconductor layer. In that case, heat treatment is performed due to the difference in thermal expansion coefficient of each material. And may cause crystal defects due to stress. However, in this embodiment, by using only the silicon oxide layer as the insulating layer 206, it is possible to provide a semiconductor device in which stress can be reduced and generation of crystal defects at the interface of the semiconductor layer 10 due to heat treatment is reduced. .

2. Method for Manufacturing Semiconductor Device Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 2 to 7 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the present embodiment.

  (1) First, as shown in FIG. 2, a semiconductor layer 10 having a chip region 10C and a recognition mark region 10S is prepared. A known material such as a single crystal silicon substrate can be used for the semiconductor layer 10. Next, a first groove 210 that is a first recognition mark for forming a well formed in a later process is formed in the recognition mark region 10S. In the formation of the first groove 210, a mask layer (not shown) having an opening in a region where the first groove 210 is formed is formed on the semiconductor layer 10. Next, the first groove 210 can be formed by etching the semiconductor layer 10 using the mask layer.

  (2) Next, as shown in FIG. 3, the well 20 is formed in the chip region 10 </ b> C using the first groove 210. First, after forming a mask layer (not shown) having an opening in a predetermined region, an impurity of a predetermined conductivity type is introduced into the semiconductor layer 10. In the step of forming the mask layer, for example, the first groove 210 is used for alignment between the semiconductor layer 10 and the reticle. Subsequently, the well 20 is formed by performing heat treatment for diffusing the impurities. This heat treatment can be performed, for example, at a temperature of 800 ° C. or higher.

  (3) Next, the element isolation insulating layer 22 and the offset insulating layer 24 (see FIG. 1) are formed in the semiconductor layer 10. As an example of forming the element isolation insulating layer 22 and the offset insulating layer 24, a case where the element isolation insulating layer 22 and the offset insulating layer 24 are formed by the STI method will be described below. First, as shown in FIG. 4, an oxide film 12 and a nitride film 14 are formed on the entire surface of the semiconductor layer 10. When the semiconductor layer 10 is a silicon substrate, for example, a silicon oxide film can be formed as the oxide film 12 and a silicon nitride film can be formed as the nitride film 14. Next, the chip region 10C has an opening 40 in a region where the element isolation insulating layer 22 and the offset insulating layer 24 are formed, and the recognition mark region 10S includes the first groove 210. A mask layer M1 having an opening 42 larger than the planar shape is formed.

  (4) Next, the oxide film 12, the nitride film 14, and the semiconductor layer 10 are etched using the mask layer M1. By this step, a trench 16 is formed as shown in FIG. In the recognition mark region 10S, a second groove 200 as a second recognition mark is formed in a region where the opening 42 (see FIG. 4) is located. The second groove 200 has a first bottom surface 202 and a second bottom surface 204 that is shallower than the first bottom surface 202. The first bottom surface 202 is located at the same depth as the bottom surface of the trench 16. That is, the first bottom surface 202 and the second bottom surface 204 form a step. This is because the first groove 210 formed in the previous step is provided in the region of the opening 42, so that the portion becomes a deeper groove. A step portion formed on the bottom surface of the second groove 200 formed by this process can be used as a second recognition mark in a subsequent transistor formation process.

  (5) Next, an insulating layer (not shown) is formed above the semiconductor layer 10 so as to fill the trench 16 and the second groove 200. Thereafter, the insulating layer is etched by, for example, a CMP method until the nitride film 14 is exposed. Next, the nitride film 14 is selectively removed by wet etching using hot phosphoric acid, for example. Next, if necessary, the insulating layer that protrudes by the thickness of the nitride film 14 when the height of the upper surface of the oxide film 12 is used as a reference is removed by a known etching method. Through the above steps, the element isolation insulating layer 22 and the offset insulating layer 24 can be formed as shown in FIG. In this step, the insulating layer 206 is formed in the second groove 200 at the same time. This insulating layer 206 can also be used for element isolation.

  (6) Next, the transistor 100 (see FIG. 1) is formed in the chip region 10C. In forming the transistor 100, the second groove 200 can be used as a recognition mark in the step of forming at least one mask layer. Thus, the 1st recognition mark (recessed part 210) used in the previous process can be applied as a recognition mark in the subsequent process. Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, it is not necessary to increase the number of steps for forming the recognition mark. As a result, the number of processes can be reduced, and the manufacturing cost can be reduced. An example of a method for forming the transistor 100 is described below.

  First, as shown in FIG. 7, a low concentration impurity layer 118 is formed. This step is performed by forming a mask layer (not shown) having an opening above at least the low-concentration impurity layer 118 and then introducing an impurity of a predetermined conductivity type into the semiconductor layer 10. Moreover, you may perform the heat processing for diffusing an impurity as needed. This heat treatment is performed under the condition that the temperature is lowered or the treatment time is shortened compared to the heat treatment performed in the step (2) (the condition that the total amount of heat is smaller than the heat treatment of the step (2)). .

  Next, the gate insulating layer 110 is formed. In forming the gate insulating layer 110, an opening is formed in a region where the gate insulating layer 110 is to be formed, and a mask layer (not shown) for heat-resistant oxidation is formed. As the mask layer, for example, a silicon nitride film can be used. Then, the gate insulating layer 110 can be formed by performing thermal oxidation. Thereafter, the mask layer is removed by a known removal method corresponding to the material.

  (7) Next, as shown in FIG. 1, a gate electrode 112 is formed. In this step, first, a conductive layer (not shown) is formed above the entire surface of the semiconductor layer 10. As the conductive layer, for example, a polycrystalline silicon layer can be formed. Thereafter, the conductive layer is formed by patterning. Next, a sidewall insulating layer 114 is formed on the side of the gate electrode 112. The sidewall insulating layer 114 is formed by forming an insulating layer (not shown) on the entire upper surface of the semiconductor layer 10 and performing anisotropic etching on the insulating layer. Next, source / drain regions 116 are formed. The source region / drain region 116 is formed by introducing an impurity after covering a region where the impurity is not desired to be introduced with a mask layer (not shown).

  Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

  According to the manufacturing method of the semiconductor device according to the present embodiment, the well 20 is formed using the first recognition mark 210 formed in the semiconductor layer 10 and then the element isolation insulating layer 22 is formed. In the formation of the well 20, thermal stress may be applied to the semiconductor layer in a heat treatment process for diffusing impurities into the semiconductor layer 10. In particular, as exemplified by the semiconductor device according to the present embodiment, in the case of a transistor for high voltage driving, it is necessary to form a deep well 20 in order to ensure a withstand voltage. In order to form the deep well 20, it is necessary to perform high-temperature heat treatment for a long time, and crystal defects are likely to occur due to thermal stress. However, according to the manufacturing method of the semiconductor device according to the present embodiment, since the element isolation insulating layer is not formed before the well is formed, crystal defects or the like due to thermal stress occur in the element isolation insulating layer 22. Can be suppressed. As a result, defects due to current leakage caused by crystal defects and the like can be reduced, and a semiconductor device with improved reliability can be manufactured.

  In the semiconductor device manufacturing method according to the present embodiment, the case where the element isolation insulating layer 22 is formed by the STI method has been described, but the present invention is not limited to this. It may be formed by the LOCOS method or the semi-recessed LOCOS method.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 10C ... Chip area | region, 10S ... Recognition mark area | region, 12 ... Oxide film, 14 ... Nitride film, 16 ... Trench, 20 ... Well, 22 ... Element isolation insulating layer, 24 ... Offset insulating layer, 40, 42 DESCRIPTION OF SYMBOLS ... Opening, 100 ... Transistor, 110 ... Gate insulating layer, 112 ... Gate electrode, 114 ... Side wall insulating layer, 116 ... Source region / drain region, 118 ... Low concentration impurity layer, 200 ... Second groove (second recognition) Mark), 202 ... first bottom surface, 204 ... second bottom surface, 206 ... insulating layer, 210 ... first groove (first recognition mark), M1 ... mask layer

Claims (8)

(A) forming a first recognition mark comprising a first groove in the semiconductor layer;
(B) forming a well in the semiconductor layer using the first recognition mark;
(C) forming a mask layer including at least a first recognition mark on the semiconductor layer and having a first opening having a planar shape larger than the planar shape of the first recognition mark;
(D) forming a second recognition mark comprising a second groove by etching the semiconductor layer using the mask layer;
(E) forming an element isolation insulating layer on the semiconductor layer;
(F) forming a transistor in the semiconductor layer by using the second recognition mark. A method for manufacturing a semiconductor device. In claim 1,
The method of manufacturing a semiconductor device, wherein the first recognition mark is formed in a scribe region. In claim 1 or 2,
In the step (c), the mask layer has a second opening above a region where the element isolation insulating layer is formed,
In the step (d), a third groove is further formed. In claim 3,
The step (e) is a method for manufacturing a semiconductor device, comprising embedding an insulating layer in the third groove. A semiconductor layer having a chip region and a recognition mark region;
A transistor provided in the chip region;
A recognition mark provided in the recognition mark area,
The recognition mark is
The semiconductor device which is a groove | channel which has the 1st bottom face provided in the said semiconductor layer, and the 2nd bottom face from which this 1st bottom face differs in depth. In claim 5,
A semiconductor device, wherein an insulating layer is formed in the groove. In claim 5 or 6,
A semiconductor device in which a bottom surface of an element isolation insulating layer provided in the chip region and the second bottom surface have the same depth. In any of claims 5 to 7,
The transistor is
A well provided in the semiconductor layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A channel region formed in the semiconductor layer;
A source region and a drain region provided in the semiconductor layer;
A semiconductor device comprising: the channel region; and an offset insulating layer provided between the source region and the drain region.

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