JP2007104353A - Logical setting circuit - Google Patents

Logical setting circuit Download PDF

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JP2007104353A
JP2007104353A JP2005291910A JP2005291910A JP2007104353A JP 2007104353 A JP2007104353 A JP 2007104353A JP 2005291910 A JP2005291910 A JP 2005291910A JP 2005291910 A JP2005291910 A JP 2005291910A JP 2007104353 A JP2007104353 A JP 2007104353A
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logic setting
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JP4770376B2 (en
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Hideo Matsukawa
英男 松川
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Yokogawa Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a logical setting circuit for detecting an failure in insulation without adding a special diagnostic circuit. <P>SOLUTION: In the logical setting circuit, each voltage at a connection point of two or more logical setting switching means connected to different pull-up resistors or pull-down resistors, is entered in a logical circuit unit. In this case, the pull-up resistors or the pull-down resistors have different resistance values from each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、別々のプルアップ抵抗又はプルダウン抵抗にそれぞれ接続された複数の論理設定用スイッチ手段の接続点の電圧を論理回路部に入力する論理設定回路の絶縁不良対策に関するものである。   The present invention relates to an insulation failure countermeasure for a logic setting circuit that inputs voltages at connection points of a plurality of logic setting switch means connected to different pull-up resistors or pull-down resistors to a logic circuit section.

絶縁不良対策に関する先行技術としては、特許文献1がある。図3は、従来の論理設定回路の構成例を示す機能ブロック図である。1は論理設定部であり、複数の論理設定用のスイッチ手段11,12,13,…1nよりなる。これらスイッチ手段の一方の端子は共通接続されてグランド電位Eに接続されている。これらスイッチ手段の他方の端子は、夫々プルアップ抵抗部2のプルアップ抵抗(抵抗値R)21,22,23,…2nを介して適当な直流電位+Vに接続されている。   As a prior art regarding measures against insulation failure, there is Patent Document 1. FIG. 3 is a functional block diagram showing a configuration example of a conventional logic setting circuit. Reference numeral 1 denotes a logic setting unit, which comprises a plurality of logic setting switch means 11, 12, 13,. One terminal of these switch means is connected in common and connected to the ground potential E. The other terminals of these switch means are connected to an appropriate DC potential + V through pull-up resistors (resistance values R) 21, 22, 23,.

前記各スイッチ手段と各プルアップ抵抗との接続点電圧の信号、V1,V2,V3,…Vnは、論理回路部3に入力され、設定読取回路31により所定のスレッシュホールド電位と比較されてデジタル信号化される。   Signals of connection points V1, V2, V3,... Vn between the switch means and the pull-up resistors are input to the logic circuit unit 3 and compared with a predetermined threshold potential by the setting reading circuit 31 to be digital. Signaled.

電子回路が実装されるプリント基板では、外気環境(腐食性ガス、結露等)による腐食や、半田工程でのフラックス残渣に発生するクラックが原因となるマイグレーションによる腐食に起因して、端子間の絶縁不良が発生する場合がある。   In printed circuit boards on which electronic circuits are mounted, insulation between terminals is caused by corrosion caused by migration due to corrosion caused by the outside air environment (corrosive gas, condensation, etc.) or cracks generated in the flux residue in the soldering process. Defects may occur.

信頼性を要求される電子機器路では、この絶縁不良に起因する論理誤動作に対して対策する必要がある。電子機器のマイグレーション等の腐食に対する一般的対策としては、
(a)耐腐食性の優れた基板材料、マイグレーションの発生を抑止したフラックスの使用。
(b)密閉構造とし、腐食性ガスの進入及び結露を防止する。
の手法が採用されている。
In an electronic device path that requires reliability, it is necessary to take measures against a logic malfunction caused by this insulation failure. As a general countermeasure against corrosion such as migration of electronic equipment,
(A) Use of a substrate material having excellent corrosion resistance and a flux that suppresses the occurrence of migration.
(B) Use a sealed structure to prevent the entry and condensation of corrosive gases.
The method is adopted.

特許文献1には、プルアップ抵抗を有する接点入力回路が記載されている。   Patent Document 1 describes a contact input circuit having a pull-up resistor.

特許第2863775号公報Japanese Patent No. 2863775

従来の論理設定回路では、次のような問題点がある。
(1)前記一般的な対策では、特別な材料の使用、気密性の高い筐体を必要とし、機器の大幅なコストアップの要因となる。
The conventional logic setting circuit has the following problems.
(1) The above-mentioned general measures require the use of special materials and a highly airtight casing, which causes a significant cost increase of the equipment.

(2)このような一般的な対策に代えて、腐食診断回路を設け、絶縁不良による影響が出る前に故障検出して基板を交換する手法もある。しかしながら、従来の論理設定回路は自身に腐食診断機能を備えていないので、新たに高価な診断回路を付加する必要があり、これも大幅なコストアップの要因となる。 (2) In place of such a general countermeasure, there is also a technique in which a corrosion diagnosis circuit is provided to detect a failure and replace the substrate before being affected by an insulation failure. However, since the conventional logic setting circuit itself does not have a corrosion diagnosis function, it is necessary to add a new expensive diagnosis circuit, which also causes a significant cost increase.

本発明は上述した問題点を解決するためになされたものであり、特別の診断回路を付加することなく、絶縁不良を検出することが可能な論理設定回路を実現することを目的としている。   The present invention has been made to solve the above-described problems, and an object thereof is to realize a logic setting circuit capable of detecting an insulation failure without adding a special diagnostic circuit.

このような課題を達成するために、本発明は次の通りの構成になっている。
(1)別々のプルアップ抵抗又はプルダウン抵抗にそれぞれ接続された複数の論理設定用スイッチ手段の接続点の電圧を論理回路部に入力する論理設定回路において、
前記プルアップ抵抗又はプルダウン抵抗を、互いに異なる抵抗値としたことを特徴とする論理設定回路。
In order to achieve such a subject, the present invention has the following configuration.
(1) In a logic setting circuit for inputting voltages at connection points of a plurality of logic setting switch means connected to separate pull-up resistors or pull-down resistors to a logic circuit unit,
A logic setting circuit, wherein the pull-up resistor or the pull-down resistor has different resistance values.

(2)前記論理設定用スイッチ手段の隣り合う前記接続点間に同一条件で絶縁不良が発生した場合、前記論理回路部において設定される所定のスレッシュホールド電圧を基準とする前記論理設定用スイッチ手段の論理入力値が1ビット変化するように、前記プルアップ抵抗又はプルダウン抵抗を互いに異なる抵抗値としたことを特徴とする(1)に記載の論理設定回路。 (2) The logic setting switch means based on a predetermined threshold voltage set in the logic circuit section when an insulation failure occurs between adjacent connection points of the logic setting switch means under the same condition. The logic setting circuit according to (1), wherein the pull-up resistor or the pull-down resistor has a different resistance value so that the logic input value of 1 changes by 1 bit.

(3)前記論理回路部は、前記1ビットの変化をパリティーエラーとして検出する故障検出回路を備えることを特徴とする(2)に記載の論理設定回路。 (3) The logic setting circuit according to (2), wherein the logic circuit section includes a failure detection circuit that detects the change of the 1 bit as a parity error.

(4)前記プルアップ又はプルダウン抵抗は、前記論理回路部内に形成されていることを特徴とする(1)乃至(3)のいずれかに記載の論理設定回路。 (4) The logic setting circuit according to any one of (1) to (3), wherein the pull-up or pull-down resistor is formed in the logic circuit section.

(5)前記プルアップ又はプルダウン抵抗は、同一抵抗値の抵抗を組み合わせて形成されていることを特徴とする(1)乃至(4)のいずれかに記載の論理設定回路。 (5) The logic setting circuit according to any one of (1) to (4), wherein the pull-up or pull-down resistors are formed by combining resistors having the same resistance value.

以上説明したことから明らかなように、本発明によれば次のような効果がある。
(1)腐食による絶縁不良の影響を事前に警報できるので、特別な材料の使用、気密性の高い筐体等の、機器の大幅なコストアップの要因となる一般的な腐食対策を必要としない。
As is apparent from the above description, the present invention has the following effects.
(1) Since the effect of insulation failure due to corrosion can be warned in advance, the use of special materials and a highly airtight casing, etc. do not require general countermeasures against corrosion that cause significant cost increase of equipment. .

(2)論理設定回路自身が備えるプルアップ抵抗又はプルダウン抵抗の抵抗値を工夫することで、コストアップの要因となる高価な診断回路を付加することなく、絶縁不良の診断機能を実現できる。 (2) By devising the resistance value of the pull-up resistor or pull-down resistor included in the logic setting circuit itself, it is possible to realize a diagnosis function for insulation failure without adding an expensive diagnostic circuit that causes an increase in cost.

以下、本発明を図面により詳細に説明する。図1は、本発明を適用した論理設定回路の実施形態を示す機能ブロック図である。図3で説明した従来回路と同一要素には同一符号を付して説明を省略する。以下、本発明の特徴部につき説明する。   Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of a logic setting circuit to which the present invention is applied. The same elements as those of the conventional circuit described with reference to FIG. Hereinafter, the characteristic part of the present invention will be described.

図1において、200は本発明が適用されたプルアップ抵抗部である。201,202,203,…20nは、夫々スイッチ手段11,12,13,…1nに接続されるプルアップ抵抗である。本発明の特徴は、これらプルアップ抵抗の抵抗値R1,R2,R3,…Rnを、R1≠R2≠R3≠…Rnと、互いに異なる値に選定した点にある。   In FIG. 1, reference numeral 200 denotes a pull-up resistor unit to which the present invention is applied. 201n, 202, 203,... 20n are pull-up resistors connected to the switching means 11, 12, 13,. The feature of the present invention is that the resistance values R1, R2, R3,... Rn of these pull-up resistors are selected to be different from each other such that R1 ≠ R2 ≠ R3 ≠ ... Rn.

各プルアップ抵抗の抵抗値をこのように選定することにより、プルアップ抵抗と接続される設定用スイッチ手段の隣り合う接続点間に同一条件で絶縁不良が発生した場合、論理回路部において設定される所定のスレッシュホールド電圧を基準とする論理入力値が1ビット変化することを利用する。   By selecting the resistance value of each pull-up resistor in this way, if an insulation failure occurs under the same conditions between adjacent connection points of the setting switch means connected to the pull-up resistor, it is set in the logic circuit section. The fact that the logical input value with reference to a predetermined threshold voltage changes by 1 bit is used.

300は本発明が適用された論理回路部であり、従来回路部と同じ設定読取回路301に追加して、故障検出回路302を備える。この故障検出回路302は、前記1ビットの変化をパリティーエラーとして絶縁不良を故障検出する。   A logic circuit unit 300 to which the present invention is applied includes a failure detection circuit 302 in addition to the same setting reading circuit 301 as the conventional circuit unit. The failure detection circuit 302 detects an insulation failure by using the change of 1 bit as a parity error.

図2は、絶縁不良による故障検出の具体的例を説明する実施形態を示す機能ブロック図である。この例では、簡単のためにスイッチ手段は11,12,13で3ビットの設定をし、プルアップ抵抗はR1,R2,R3の3個の場合を示している。これらプルアップ抵抗は、R1≠R2≠R3に選定されている。   FIG. 2 is a functional block diagram showing an embodiment for explaining a specific example of failure detection due to insulation failure. In this example, for simplification, the switch means is set to 3 bits at 11, 12, and 13 and the pull-up resistors are three cases of R1, R2, and R3. These pull-up resistors are selected such that R1 ≠ R2 ≠ R3.

401及び402は、絶縁不良を表す等価抵抗であり、401は信号V1と信号V2間に、402は信号V2と信号V3間に接続され、同一条件で絶縁不良が発生していることを想定してその抵抗値をRxで示している。   401 and 402 are equivalent resistances representing insulation failure, 401 is connected between signal V1 and signal V2, 402 is connected between signal V2 and signal V3, and it is assumed that insulation failure has occurred under the same conditions. The resistance value is indicated by Rx.

ここで、論理設定部1のスイッチ手段による設定状態を、1:0:1に、直流電位+Vを3.3Vにした場合を想定する。従来は、プルアップ抵抗は同じ抵抗値であり、例えばR1=R2=R3=2kΩであったとする。マイグレーション等による絶縁不良により、信号V1−信号V2間および信号V2−信号V3間のインピーダンスが低下し、等価抵抗Rx=1kΩで短絡されたとする。   Here, it is assumed that the setting state by the switch means of the logic setting unit 1 is 1: 0: 1 and the DC potential + V is 3.3V. Conventionally, it is assumed that the pull-up resistors have the same resistance value, for example, R1 = R2 = R3 = 2 kΩ. It is assumed that the impedance between the signal V1 and the signal V2 and between the signal V2 and the signal V3 is lowered due to an insulation failure due to migration or the like, and is short-circuited with an equivalent resistance Rx = 1 kΩ.

信号V2の電位は、0Vである。従来回路では、信号V1の電位は、R1(2kΩ)及びRx(1kΩ)により分圧されるため、1.1Vとなる。同様に、信号V3の電位もR3(2kΩ)及びRx(1kΩ)により分圧されるため、1.1Vとなる。   The potential of the signal V2 is 0V. In the conventional circuit, the potential of the signal V1 is 1.1 V because it is divided by R1 (2 kΩ) and Rx (1 kΩ). Similarly, the potential of the signal V3 is 1.1 V because it is divided by R3 (2 kΩ) and Rx (1 kΩ).

論理回路部300内において設定されるスレッシュホールド電圧を1.5Vとすると、論理回路部は、正しい論理値V1:V2:V3=1:0:1に対して、V1:V2:V3=0:0:0と読み取る。   When the threshold voltage set in the logic circuit unit 300 is 1.5 V, the logic circuit unit has a correct logic value V1: V2: V3 = 1: 0: 1, whereas V1: V2: V3 = 0: Read as 0: 0.

この論理値変化を、広く使用されているパリティチェック手法による故障検出回路302により検出する場合、パリティチェックでは、1ビット故障は検出できるが、2ビット故障は検出できない。即ち、プルアップ抵抗を全て同じ抵抗値とする従来回路では、パリティチェック手法による故障検出はできない。   When this logical value change is detected by the failure detection circuit 302 using a widely used parity check technique, the parity check can detect a 1-bit failure but cannot detect a 2-bit failure. That is, in the conventional circuit in which all the pull-up resistors have the same resistance value, failure detection by the parity check method cannot be performed.

そこで、本発明では、隣接するプルアップ抵抗の抵抗値を変え、例えばR1=1kΩ、R2=2kΩ、R3=3kΩとする。マイグレーション等による絶縁不良により、信号V1−信号V2間および信号V2−信号V3間のインピーダンスが低下し、Rx=1kΩで接続されたとする。   Therefore, in the present invention, the resistance values of adjacent pull-up resistors are changed, for example, R1 = 1 kΩ, R2 = 2 kΩ, and R3 = 3 kΩ. It is assumed that the impedance between the signal V1 and the signal V2 and between the signal V2 and the signal V3 is lowered due to insulation failure due to migration or the like, and the connection is made at Rx = 1 kΩ.

信号V1の電位は、R1(1kΩ)及びRx(1kΩ)により分圧されるため、1.65Vとなる。同様に、信号V3の電位もR3(3kΩ)及びRx(1kΩ)により分圧されるため、0.825Vとなる。   The potential of the signal V1 is 1.65 V because it is divided by R1 (1 kΩ) and Rx (1 kΩ). Similarly, since the potential of the signal V3 is also divided by R3 (3 kΩ) and Rx (1 kΩ), it becomes 0.825 V.

論理回路部300内において設定されるスレッシュホールド電圧を1.5Vとすると、論理回路部は、正しい論理値V1:V2:V3=1:0:1に対して、V1:V2:V3=1:0:0と読み取る。   Assuming that the threshold voltage set in the logic circuit unit 300 is 1.5 V, the logic circuit unit has a correct logic value V1: V2: V3 = 1: 0: 1, whereas V1: V2: V3 = 1: Read as 0: 0.

この論理値変化を、パリティチェック手法を用いた故障検出回路302により検出する場合、正しい論理値に対して1ビット変化しているので、パリティーエラーとして故障検出することが可能となる。   When this logical value change is detected by the failure detection circuit 302 using the parity check method, since 1 bit is changed with respect to the correct logical value, it is possible to detect a failure as a parity error.

以上説明した実施形態では、プルアップ抵抗を論理部回路部300の外部回路に記述したが、ASICのような論理回路部の中に値の異なるプルアップ抵抗群を具備した形態でも良い。値の異なる抵抗を実現する場合、同じ値の複数の抵抗を並列または直列に接続した形態であってもよい。   In the embodiment described above, the pull-up resistor is described in the external circuit of the logic unit circuit unit 300. However, the logic circuit unit such as an ASIC may include a group of pull-up resistors having different values. When realizing resistors having different values, a plurality of resistors having the same value may be connected in parallel or in series.

実施形態では、設定スイッチ手段の共通接続点をグランド電位Eに接続とし、抵抗群を直流電位+Vに接続するプルアップの形態を示したが、設定スイッチ手段の共通接続点を直流電位+Vに接続し、抵抗群をグランド電位Eに接続するプルダウンの形態であってもよい。   In the embodiment, the pull-up form is shown in which the common connection point of the setting switch means is connected to the ground potential E, and the resistor group is connected to the DC potential + V. However, the common connection point of the setting switch means is connected to the DC potential + V. However, a pull-down configuration in which the resistor group is connected to the ground potential E may be used.

実施形態では、論理設定を行う設定スイッチ手段を機械的な接点の形態で示しているが、半導体で実現される電子的なスイッチ手段であってもよい。   In the embodiment, the setting switch means for performing the logic setting is shown in the form of a mechanical contact, but it may be an electronic switch means realized by a semiconductor.

本発明を適用した論理設定回路の実施形態を示す機能ブロック図である。It is a functional block diagram showing an embodiment of a logic setting circuit to which the present invention is applied. 絶縁不良による故障検出の具体的例を説明する実施形態を示す機能ブロック図である。It is a functional block diagram which shows embodiment which demonstrates the specific example of the failure detection by an insulation failure. 従来の論理設定回路の構成例を示す機能ブロック図である。It is a functional block diagram which shows the structural example of the conventional logic setting circuit.

符号の説明Explanation of symbols

1 論理設定部
11,12,13,…1n スイッチ手段
200 プルアップ抵抗部
201,202,203,…20n プルアップ抵抗
300 論理回路部
301 設定読取回路
302 故障検出回路

DESCRIPTION OF SYMBOLS 1 Logic setting part 11, 12, 13, ... 1n Switch means 200 Pull-up resistance part 201,202,203, ... 20n Pull-up resistance 300 Logic circuit part 301 Setting reading circuit 302 Failure detection circuit

Claims (5)

別々のプルアップ抵抗又はプルダウン抵抗にそれぞれ接続された複数の論理設定用スイッチ手段の接続点の電圧を論理回路部に入力する論理設定回路において、
前記プルアップ抵抗又はプルダウン抵抗を、互いに異なる抵抗値としたことを特徴とする論理設定回路。
In the logic setting circuit for inputting the voltages at the connection points of a plurality of logic setting switch means connected to different pull-up resistors or pull-down resistors to the logic circuit section,
A logic setting circuit, wherein the pull-up resistor or the pull-down resistor has different resistance values.
前記論理設定用スイッチ手段の隣り合う前記接続点間に同一条件で絶縁不良が発生した場合、前記論理回路部において設定される所定のスレッシュホールド電圧を基準とする前記論理設定用スイッチ手段の論理入力値が1ビット変化するように、前記プルアップ抵抗又はプルダウン抵抗を互いに異なる抵抗値としたことを特徴とする請求項1に記載の論理設定回路。   When an insulation failure occurs under the same conditions between the adjacent connection points of the logic setting switch means, the logic input of the logic setting switch means with reference to a predetermined threshold voltage set in the logic circuit section 2. The logic setting circuit according to claim 1, wherein the pull-up resistor or the pull-down resistor has a different resistance value so that the value changes by 1 bit. 前記論理回路部は、前記1ビットの変化をパリティーエラーとして検出する故障検出回路を備えることを特徴とする請求項2に記載の論理設定回路。   The logic setting circuit according to claim 2, wherein the logic circuit unit includes a failure detection circuit that detects a change in the 1 bit as a parity error. 前記プルアップ又はプルダウン抵抗は、前記論理回路部内に形成されていることを特徴とする請求項1乃至3のいずれかに記載の論理設定回路。   4. The logic setting circuit according to claim 1, wherein the pull-up or pull-down resistor is formed in the logic circuit unit. 前記プルアップ又はプルダウン抵抗は、同一抵抗値の抵抗を組み合わせて形成されていることを特徴とする請求項1乃至4のいずれかに記載の論理設定回路。
5. The logic setting circuit according to claim 1, wherein the pull-up or pull-down resistor is formed by combining resistors having the same resistance value.
JP2005291910A 2005-10-05 2005-10-05 Logic setting circuit Expired - Fee Related JP4770376B2 (en)

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CN105301476A (en) * 2015-10-14 2016-02-03 京东方科技集团股份有限公司 Signal testing device for printed circuit board
JP2018088627A (en) * 2016-11-29 2018-06-07 株式会社ユーシン Input device

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JP2009238424A (en) * 2008-03-26 2009-10-15 Sanden Corp Migration preventing circuit
JP2012208067A (en) * 2011-03-30 2012-10-25 Keihin Corp Battery voltage detection device
CN105301476A (en) * 2015-10-14 2016-02-03 京东方科技集团股份有限公司 Signal testing device for printed circuit board
WO2017063395A1 (en) * 2015-10-14 2017-04-20 京东方科技集团股份有限公司 Signal testing device for printed circuit board
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