JP2007096279A5 - - Google Patents

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Publication number
JP2007096279A5
JP2007096279A5 JP2006225479A JP2006225479A JP2007096279A5 JP 2007096279 A5 JP2007096279 A5 JP 2007096279A5 JP 2006225479 A JP2006225479 A JP 2006225479A JP 2006225479 A JP2006225479 A JP 2006225479A JP 2007096279 A5 JP2007096279 A5 JP 2007096279A5
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JP
Japan
Prior art keywords
integrated circuit
substrate
circuit device
recess
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006225479A
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Japanese (ja)
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JP2007096279A (en
JP5137356B2 (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2006225479A priority Critical patent/JP5137356B2/en
Priority claimed from JP2006225479A external-priority patent/JP5137356B2/en
Publication of JP2007096279A publication Critical patent/JP2007096279A/en
Publication of JP2007096279A5 publication Critical patent/JP2007096279A5/ja
Application granted granted Critical
Publication of JP5137356B2 publication Critical patent/JP5137356B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (12)

一方の面に集積回路が設けられ、他方の面に凹部を有する基板を有し
記凹部には放熱性材料が充填されていることを特徴とする集積回路装置。
On one surface an integrated circuit is provided, comprising a substrate having a recess on the other side,
The front Symbol recess, the integrated circuit device heat dissipation material is characterized in that it is filled.
積層された複数の基板を有し、
前記複数の基板のうち少なくとも1つの基板は、一方の面に集積回路が設けられ、他方の面に凹部を有し、
記凹部には放熱性材料が充填されていることを特徴とする集積回路装置。
Having a plurality of stacked substrates,
At least one substrate of the plurality of substrates, integrated circuits are provided on one surface, has a recess on the other side,
The front Symbol recess, the integrated circuit device heat dissipation material is characterized in that it is filled.
一方の面に集積回路が設けられ、他方の面に凹部を有する基板を有し
なくとも前記凹部の表面には、放熱性材料を含む膜が設けられていることを特徴とする
集積回路装置。
On one surface an integrated circuit is provided, comprising a substrate having a recess on the other side,
On the surface of the recess even without low, integrated circuit device, wherein a film containing a heat dissipation material is provided.
積層された複数の基板を有し、
前記複数の基板のうち少なくとも1つの基板は、一方の面に集積回路が設けられ、他方の面に凹部を有し、
なくとも前記凹部の表面には、放熱性材料を含む膜が設けられていることを特徴とする集積回路装置。
Having a plurality of stacked substrates,
At least one substrate of the plurality of substrates, integrated circuits are provided on one surface, has a recess on the other side,
On the surface of the recess even without low, integrated circuit device, wherein a film containing a heat dissipation material is provided.
請求項1乃至請求項4のいずれか一項において、In any one of Claims 1 thru | or 4,
前記他方の面は、前記一方の面よりも表面積が大きいことを特徴とする集積回路装置。The integrated circuit device, wherein the other surface has a surface area larger than that of the one surface.
請求項2または請求項4において、
前記複数の基板のうち少なくとも1つの基板には、放熱部が設けられていることを特徴とする集積回路装置。
In claim 2 or claim 4,
An integrated circuit device, wherein a heat radiating portion is provided on at least one of the plurality of substrates.
請求項6において、In claim 6,
前記放熱部は、前記基板の端部に設けられていることを特徴とする集積回路装置。The integrated circuit device, wherein the heat radiating portion is provided at an end portion of the substrate.
請求項6または請求項7において、In claim 6 or claim 7,
前記放熱部に凹部が設けられていることを特徴とする集積回路装置。An integrated circuit device, wherein the heat radiating portion is provided with a recess.
請求項1乃至請求項8のいずれか一項において、
前記放熱性材料は、前記基板を構成する材料よりも熱伝導率が高い材料であることを特徴
とする集積回路装置。
In any one of claims 1 to 8,
The integrated circuit device, wherein the heat dissipating material is a material having a higher thermal conductivity than a material constituting the substrate.
請求項1乃至請求項9のいずれか一項において、
前記基板はガラス基板または石英基板であり、
前記放熱性材料は、20℃における熱伝導率が2W/(m・K)以上の材料であることを
特徴とする集積回路装置。
In any one of Claims 1 thru | or 9 ,
The substrate is a glass substrate or a quartz substrate;
The integrated circuit device, wherein the heat dissipating material is a material having a thermal conductivity of 2 W / (m · K) or more at 20 ° C.
請求項1乃至請求項9のいずれか一項において、In any one of Claims 1 thru | or 9,
前記基板は、ガラス基板または石英基板であり、The substrate is a glass substrate or a quartz substrate;
前記放熱性材料は、Si、金属、合金、窒化アルミニウム、グラファイト、窒化珪素、またはこれらをポリマー中に混合した材料であることを特徴とする集積回路装置。The integrated circuit device is characterized in that the heat dissipation material is Si, metal, alloy, aluminum nitride, graphite, silicon nitride, or a material obtained by mixing these in a polymer.
請求項1乃至請求項11のいずれか一項において、
前記基板の厚さは100μm以下であることを特徴とする集積回路装置。
In any one of Claims 1 to 11 ,
An integrated circuit device, wherein the substrate has a thickness of 100 μm or less.
JP2006225479A 2005-09-02 2006-08-22 Integrated circuit device Expired - Fee Related JP5137356B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006225479A JP5137356B2 (en) 2005-09-02 2006-08-22 Integrated circuit device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005254481 2005-09-02
JP2005254481 2005-09-02
JP2006225479A JP5137356B2 (en) 2005-09-02 2006-08-22 Integrated circuit device

Publications (3)

Publication Number Publication Date
JP2007096279A JP2007096279A (en) 2007-04-12
JP2007096279A5 true JP2007096279A5 (en) 2009-09-10
JP5137356B2 JP5137356B2 (en) 2013-02-06

Family

ID=37981542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006225479A Expired - Fee Related JP5137356B2 (en) 2005-09-02 2006-08-22 Integrated circuit device

Country Status (1)

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JP (1) JP5137356B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4973328B2 (en) * 2007-06-14 2012-07-11 株式会社デンソー Semiconductor device
CN102576735B (en) 2009-09-30 2016-01-20 大日本印刷株式会社 The manufacture method of flexible device substrate, flexible device thin film transistor base plate, flexible device, thin-film component substrate, thin-film component, thin-film transistor, the manufacture method of thin-film component substrate, the manufacture method of thin-film component and thin-film transistor
US20110186899A1 (en) * 2010-02-03 2011-08-04 Polymer Vision Limited Semiconductor device with a variable integrated circuit chip bump pitch
JP2011233858A (en) * 2010-04-09 2011-11-17 Dainippon Printing Co Ltd Method for manufacturing substrate for thin film element, method for manufacturing thin film element, method for manufacturing thin film transistor, thin film element and thin film transistor
JP2014082253A (en) * 2012-10-15 2014-05-08 Nippon Hoso Kyokai <Nhk> Lamination type semiconductor device, semiconductor chip, and method of manufacturing lamination type semiconductor device
US20220037778A1 (en) * 2018-12-25 2022-02-03 Toray Industries, Inc. Method for manufacturing wireless communication device, wireless communication device, and assembly of wireless communication devices
KR20220096469A (en) 2020-12-31 2022-07-07 엘지디스플레이 주식회사 Display apparatus comprising overlapped pixel driving circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3506054B2 (en) * 1999-07-23 2004-03-15 日本電気株式会社 Semiconductor device and method of manufacturing semiconductor device
JP2002246514A (en) * 2001-02-14 2002-08-30 Fuji Electric Co Ltd Semiconductor device
JP4483123B2 (en) * 2001-05-07 2010-06-16 ソニー株式会社 Three-dimensional semiconductor chip and manufacturing method thereof
JP3791459B2 (en) * 2002-05-27 2006-06-28 株式会社デンソー Semiconductor device and manufacturing method thereof
JP4238998B2 (en) * 2004-03-18 2009-03-18 セイコーエプソン株式会社 Electrical device

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