JP2007081108A - Laminated structure of semiconductor chip and semiconductor device using same - Google Patents

Laminated structure of semiconductor chip and semiconductor device using same Download PDF

Info

Publication number
JP2007081108A
JP2007081108A JP2005266760A JP2005266760A JP2007081108A JP 2007081108 A JP2007081108 A JP 2007081108A JP 2005266760 A JP2005266760 A JP 2005266760A JP 2005266760 A JP2005266760 A JP 2005266760A JP 2007081108 A JP2007081108 A JP 2007081108A
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring
base substrate
mounting
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005266760A
Other languages
Japanese (ja)
Inventor
Kunihiro Takenaka
国浩 竹中
Toshio Nagao
敏男 長尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Corp filed Critical Yaskawa Electric Corp
Priority to JP2005266760A priority Critical patent/JP2007081108A/en
Publication of JP2007081108A publication Critical patent/JP2007081108A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the size of two semiconductor chips three-dimensionally mounted down to a chip size and also to electrically connect the chips with the shortest wiring line length. <P>SOLUTION: A laminated structure of a semiconductor chip comprises two semiconductor chips of a large semiconductor chip 111a and a small semiconductor chip 111b, a wiring board 120 for mounting these chips thereon, and a base substrate 114 for mounting the semiconductor chips and the wiring board 120 thereon. The large semiconductor chip is mounted on the base substrate through the wiring board. The small semiconductor chip is mounted at such a position as to be sandwiched by the large semiconductor chip and the base substrate. The wiring board has a space for being capable of accommodating the small semiconductor chip, a thickness larger than the mounted height of the small semiconductor chip, electrodes and wiring lines necessary for mounting the large semiconductor chip. External electrodes 122 for connection with the base substrate are provided on the side of the wiring board opposed to the mount surface of the large semiconductor chip. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体チップを高密度に実装する手段として、半導体チップを積層して実装する際に用いる実装構造に関するものであり、特にその実装構造を用いた半導体装置に関する。   The present invention relates to a mounting structure used when stacking and mounting semiconductor chips as means for mounting semiconductor chips at high density, and more particularly to a semiconductor device using the mounting structure.

従来の半導体チップの積層構造として、半導体チップを配線基板へ実装し、その配線基板を積層するものと、半導体チップ同士を直接積層するものの二つがある。前者は第１の従来例を示すもので、配線基板が可撓性であり、半導体チップと実装するための電極や配線を有しており、その配線基板上に半導体チップを実装したのち、半導体チップが実装された配線基板を積層するものである。電気的な接続は、配線基板の端部に設けられた外部電極を介して行う（例えば、特許文献１参照）。また、後者は第２の従来例を示すもので、異なる大きさの半導体チップで、大きさの大きな半導体チップを下にしその上に大きさの小さな半導体チップを積層し、電気的な接続は、ワイヤボンディングによる配線やフリップチップ実装法により達成している（例えば、非特許文献１参照）。
第１の従来例の構造を図４に示す。図４は、従来の半導体チップの積層構造を示す概略断面図である。図において、１１１は半導体チップ、１１２は可撓性を有し、半導体チップの内部電極と電気的に接続される配線パターンとを有している配線基板、１１３は配線基板１１２の端部に設けられた外部電極、１１４はベース基板、１１５はベース基板上に設けられたベース電極である。半導体チップの積層構造は、半導体チップが実装され、可撓性を有した配線基板を積層することで達成される。まず、配線基板１１２に半導体チップ１１１がフリップチップ実装法により実装される。半導体チップ１１１と配線基板１１２の電気的な接続は、図示しないバンプを介して達成される。積層構造は、半導体チップがフリップチップ実装された配線基板を複数段重ね、配線基板１１２の端部に設けられた外部電極１１３がはんだ付されることにより、電気的、機械的に接合される。はんだ付は、ヒータツールなどにより、外部電極１１３を局所的に加熱、加圧することで、一括で積層される。
第２の従来例の構造を図５に示す。図５は、従来の半導体チップ積層構造を示す概略断面図である。図５に示す非特許文献１の構成要素が特許文献１と同じものについては、同一符号を付してその説明を省略し、異なる点のみ説明する。図において、１１６はワイヤ配線、１１７ははんだボール、１１８はパッケージ樹脂、１１９はバンプである。特に、２つの異なる大きさの半導体チップを、大きさの大きい半導体チップを大半導体チップ１１１ａ、大きさの小さい半導体チップを小半導体チップ１１１ｂとする。半導体チップの積層構造は、大半導体チップ１１１ａ上に直接小半導体１１１ｂチップを実装することで達成される。まず、ベース基板１１４に大半導体チップ１１１ａをダイボンディングした後、その大半導体チップ上に小半導体チップ１１１ｂをダイボンディングする。２つの半導体チップおよび大半導体チップ１１１ａとベース基板１１４の電気的な接続は、ワイヤボンディングにより行われ、ワイヤ１１６を介して達成される（図５（ａ））。また、ベース基板１１４に大半導体チップ１１１ａをダイボンディングした後、その大半導体チップ１１１ａ上に小半導体チップ１１１ｂをフリップチップ実装法により実装する場合もある。２つの半導体チップの電気的な接続は、フリップチップ実装法により行われ、バンプ１１９を介して達成され、大半導体チップ１１１ａとベース基板１１４の電気的な接続は、ワイヤボンディングにより行われ、ワイヤ配線１１６を介して達成される（図５（ｂ））。この場合、大半導体チップ１１１ａの裏面には、小半導体チップ１１１ｂを実装するために、何らかの電極および配線が必要になる。また、ベース基板１１４に大半導体チップ１１１ａをフリップチップ実装法により実装した後、その大半導体チップ１１１ａ上に小半導体チップ１１１ｂをダイボンディングする場合もある。２つの半導体チップの電気的な接続は、ワイヤボンディングにより行われ、ワイヤ配線１１６とベース基板１１４を介して達成され、大半導体チップ１１１ａとベース基板１１４の電気的な接続は、フリップチップ実装法によりバンプ１１９を介して達成される（図５（ｃ））。
このように、従来の半導体チップの積層構造は、半導体チップをフリップチップ実装法により実装した可撓性を有した配線基板を積層する構造で、電気的な接続は配線基板の端部に設けられた外部電極を介して行うものや、異なる大きさの半導体チップで、大きさが大きな半導体チップを下にし、その上に大きさが小さな半導体チップを直接積層する構造で、電気的な接続はワイヤボンディングによるワイヤ配線やフリップチップ実装法によるバンプを介して行うものである。
特開２００２−５７２７９号公報（第５−７頁、図３） 小澤 要、合葉 和之ら「SiP(System in Package)の電気特性評価」エレクトロニクス実装学会誌、Ｖｏｌ．６、Ｎｏ．４、ｐ．３２６−３３１、２００３年 There are two conventional stacked structures of semiconductor chips: a semiconductor chip mounted on a wiring board and the wiring board stacked, and a semiconductor chip stacked directly. The former shows a first conventional example. The wiring board is flexible and has electrodes and wiring for mounting on a semiconductor chip. After mounting the semiconductor chip on the wiring board, the semiconductor A wiring board on which chips are mounted is laminated. The electrical connection is made via an external electrode provided at the end of the wiring board (see, for example, Patent Document 1). The latter shows a second conventional example. A semiconductor chip having a different size, a semiconductor chip having a large size on the bottom, and a semiconductor chip having a small size stacked on the semiconductor chip are electrically connected. This is achieved by wiring by wire bonding or a flip chip mounting method (for example, see Non-Patent Document 1).
The structure of the first conventional example is shown in FIG. FIG. 4 is a schematic cross-sectional view showing a conventional laminated structure of semiconductor chips. In the figure, 111 is a semiconductor chip, 112 is a flexible wiring board having a wiring pattern electrically connected to internal electrodes of the semiconductor chip, and 113 is provided at an end of the wiring board 112. The external electrode 114, a base substrate 114, and a base electrode 115 provided on the base substrate. The stacked structure of semiconductor chips is achieved by stacking a flexible wiring board on which the semiconductor chips are mounted. First, the semiconductor chip 111 is mounted on the wiring board 112 by a flip chip mounting method. The electrical connection between the semiconductor chip 111 and the wiring substrate 112 is achieved through bumps (not shown). The stacked structure is electrically and mechanically bonded by stacking a plurality of wiring substrates on which semiconductor chips are flip-chip mounted and soldering the external electrodes 113 provided at the ends of the wiring substrate 112. In soldering, the external electrodes 113 are locally heated and pressurized with a heater tool or the like to be stacked in a lump.
The structure of the second conventional example is shown in FIG. FIG. 5 is a schematic cross-sectional view showing a conventional semiconductor chip laminated structure. Components that are the same as those of Non-Patent Document 1 shown in FIG. 5 are denoted by the same reference numerals, description thereof is omitted, and only different points will be described. In the figure, 116 is a wire wiring, 117 is a solder ball, 118 is a package resin, and 119 is a bump. In particular, two different sized semiconductor chips are referred to as a large semiconductor chip 111a and a small semiconductor chip 111b. A stacked structure of semiconductor chips is achieved by mounting a small semiconductor 111b chip directly on a large semiconductor chip 111a. First, after the large semiconductor chip 111a is die-bonded to the base substrate 114, the small semiconductor chip 111b is die-bonded on the large semiconductor chip. Electrical connection between the two semiconductor chips and the large semiconductor chip 111a and the base substrate 114 is performed by wire bonding and is achieved through the wires 116 (FIG. 5A). In some cases, after the large semiconductor chip 111a is die-bonded to the base substrate 114, the small semiconductor chip 111b is mounted on the large semiconductor chip 111a by a flip chip mounting method. The electrical connection between the two semiconductor chips is performed by a flip chip mounting method and is achieved via the bumps 119, and the electrical connection between the large semiconductor chip 111a and the base substrate 114 is performed by wire bonding, and wire wiring 116 (FIG. 5B). In this case, some electrodes and wiring are necessary on the back surface of the large semiconductor chip 111a in order to mount the small semiconductor chip 111b. In some cases, after the large semiconductor chip 111a is mounted on the base substrate 114 by the flip chip mounting method, the small semiconductor chip 111b is die-bonded on the large semiconductor chip 111a. The electrical connection between the two semiconductor chips is performed by wire bonding and is achieved via the wire wiring 116 and the base substrate 114, and the electrical connection between the large semiconductor chip 111a and the base substrate 114 is performed by a flip chip mounting method. This is achieved through the bump 119 (FIG. 5C).
Thus, the conventional laminated structure of semiconductor chips is a structure in which a flexible wiring board in which semiconductor chips are mounted by a flip chip mounting method is laminated, and electrical connection is provided at the end of the wiring board. This is done by using external electrodes or semiconductor chips of different sizes, with a large semiconductor chip facing down, and a small semiconductor chip stacked directly on top of it. This is performed through wire wiring by bonding or bumps by flip chip mounting.
JP 2002-57279 A (Page 5-7, FIG. 3) Kaname Ozawa, Kazuyuki Aiba et al. “Electrical characteristics evaluation of SiP (System in Package)”, Journal of Japan Institute of Electronics Packaging, Vol. 6, no. 4, p. 326-331, 2003

ところが、第１の従来例の半導体チップの積層構造では、可撓性を有した配線基板を用いる場合、配線基板を積層するための外部電極が配線基板の端部に設けられ、その外部電極は、半導体チップ周囲の２辺、または、４辺に必要となり、チップサイズまで小形化できないという問題があった。
また、第２の従来例の半導体チップの積層構造では、半導体チップを直接積層する場合、ワイヤボンディングによるワイヤ配線が必要となっており、ワイヤ配線長が短くできないので、その配線長が高速信号の伝播に悪影響をおよぼすという問題があった。また、ワイヤボンディングによるワイヤ配線は、ワイヤループ高さや、ワイヤボンディングするためのスペースが必要となっていて、チップサイズまで小形化できないというような問題もあった。
本発明はこのような問題点に鑑みてなされたものであり、チップサイズまで小形化するとともに、最短の配線長で電気的な接続をすることができる半導体チップの積層構造とそれを用いた半導体装置を提供することを目的とする。 However, in the first conventional semiconductor chip stacking structure, when a flexible wiring board is used, an external electrode for stacking the wiring board is provided at the end of the wiring board, and the external electrode is However, it is necessary for two or four sides around the semiconductor chip, and there is a problem that the chip size cannot be reduced.
In the second conventional semiconductor chip laminated structure, when semiconductor chips are directly laminated, wire wiring by wire bonding is required, and the wire wiring length cannot be shortened. There was a problem of adversely affecting the propagation. In addition, wire wiring by wire bonding has a problem that the wire loop height and a space for wire bonding are required, and the chip size cannot be reduced.
SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and a semiconductor chip stacked structure that can be miniaturized to a chip size and can be electrically connected with the shortest wiring length and a semiconductor using the same An object is to provide an apparatus.

上記問題を解決するため、本発明は、次のように構成したものである。
請求項１に記載の発明は、形状の大きい大半導体チップと形状の小さい小半導体チップからなる２つの半導体チップと、前記２つの半導体チップを実装するための電極と配線とを有した配線基板と、前記半導体チップおよび前記配線基板を実装するための電極や配線を有したベース基板とを備え、半導体チップを立体的に実装する半導体チップの積層構造において、前記大半導体チップは前記配線基板を介してベース基板へ実装され、前記小半導体チップは前記大半導体チップと前記ベース基板にはさまれる位置に実装され、前記配線基板は、前記小半導体チップが収納できるための空間と、前記小半導体チップの実装高さよりも大きな厚みと、前記大半導体チップを実装するための電極および配線を有し、前記ベース基板と接続するための外部電極は前記大半導体チップを実装する面と反対側の面に有しているものである。
また、請求項２に記載の発明は、請求項１記載の半導体チップの積層構造を用いて、前記ベース基板の半導体チップが実装された面と反対側の面に、外部と接続するはんだボールを設けたものである。 In order to solve the above problems, the present invention is configured as follows.
According to a first aspect of the present invention, there is provided a wiring board having two semiconductor chips comprising a large semiconductor chip having a large shape and a small semiconductor chip having a small shape, an electrode for mounting the two semiconductor chips, and a wiring. And a base substrate having electrodes and wiring for mounting the semiconductor chip and the wiring board, and a semiconductor chip stacked structure for mounting the semiconductor chip in three dimensions, wherein the large semiconductor chip is interposed through the wiring board. Mounted on a base substrate, the small semiconductor chip is mounted at a position sandwiched between the large semiconductor chip and the base substrate, the wiring substrate includes a space for accommodating the small semiconductor chip, and the small semiconductor chip Having a thickness larger than the mounting height of the electrode, and an electrode and wiring for mounting the large semiconductor chip, for connecting to the base substrate Parts electrodes are those having the surface opposite to the surface mounting the large semiconductor chip.
According to a second aspect of the present invention, a solder ball connected to the outside is provided on the surface of the base substrate opposite to the surface on which the semiconductor chip is mounted using the laminated structure of the semiconductor chips according to the first aspect. It is provided.

請求項１に記載の発明によると、外部電極が半導体チップの投影面積内に形成可能なため、チップサイズまで小形化ができる。２つの異なる大きさの半導体チップは、ともにフリップチップ実装法により実装することができるため配線長を短くすることができ、同時に、高速信号の伝播におよぼす悪影響を低減することができる。また、用いる半導体チップは特殊な加工が必要なく、汎用的な半導体チップを使用できる。
また、請求項２に記載の発明によると、ベース基板に直接はんだボールを実装することができるため、２つのチップを積層した半導体装置をチップサイズまで小形化することができる。 According to the first aspect of the invention, since the external electrode can be formed within the projected area of the semiconductor chip, the chip size can be reduced. Since two different sized semiconductor chips can be mounted by the flip chip mounting method, the wiring length can be shortened, and at the same time, the adverse effect on high-speed signal propagation can be reduced. Moreover, the semiconductor chip to be used does not require special processing, and a general-purpose semiconductor chip can be used.
According to the second aspect of the present invention, since the solder ball can be directly mounted on the base substrate, the semiconductor device in which two chips are stacked can be downsized to the chip size.

以下、本発明の実施の形態について図を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施例１の半導体チップの積層構造を示す図であり、（ａ）は側断面図、（ｂ）は（ａ）のＡ−Ａ’面で切断した上断面図である。本発明の構成要素が従来技術と同じものについては、同一符号を付してその説明を省略し、異なる点のみ説明する。図において、１２０は配線基板、１２１はアンダーフィル、１２２は配線基板の大半導体チップ実装面と反対側の面に設けられた外部電極である。
本実施例は、ベース基板１１４上に実装された小半導体チップ１１１ｂが、配線基板１２０を介して電気的に接続される大半導体チップ１１１ａと、ベース基板１１４にはさまれる構造となっており、その空隙には、熱疲労に対する信頼性を向上するためにアンダーフィル１２１が充填されている。 1A and 1B are views showing a stacked structure of a semiconductor chip according to a first embodiment of the present invention. FIG. 1A is a side sectional view, and FIG. 1B is an upper sectional view taken along the line AA ′ in FIG. is there. Constituent elements of the present invention that are the same as those of the prior art will be denoted by the same reference numerals, description thereof will be omitted, and only differences will be described. In the figure, 120 is a wiring substrate, 121 is an underfill, and 122 is an external electrode provided on the surface of the wiring substrate opposite to the large semiconductor chip mounting surface.
In this embodiment, the small semiconductor chip 111b mounted on the base substrate 114 is sandwiched between the large semiconductor chip 111a electrically connected via the wiring substrate 120 and the base substrate 114. The void is filled with an underfill 121 in order to improve reliability against thermal fatigue.

つぎに、本実施例の半導体チップの積層構造の製造方法を図２のチャートを用いて説明する。
（1） 先ず、小半導体チップ１１１ｂをベース基板１１４へフリップチップ実装法により実装する。ここで用いるフリップチップ実装法は、接合材に導電性接着剤を用いるものやはんだを用いるものが考えられるが特に限定はない。
(2) 小半導体チップ１１１ｂを実装後、ベース基板１１４へ配線基板１２０を実装する。配線基板１２０の外部電極１２２とベース基板のベース電極１１５が接合される。ここで用いられる接合材は、接合材に導電性接着剤を用いるものやはんだを用いるが特に限定はない。ベース基板１１４へ配線基板１２０を実装後、大半導体チップ１１１ａを配線基板１２０上に実装する。ここで用いるフリップチップ実装法も、小半導体チップ１１１ｂ実装時と同様に実装される。
(3) アンダーフィル１２１は、ベース基板１１４に小半導体チップ１１１ｂと配線基板１２０を実装後、充填し、その後、大半導体チップ１１１ａを実装後、再度、充填する２回充填でも良いし、大半導体チップ１１１ａが実装された後に一度に充填する１回充填でも良い。
このようにして、製造した半導体チップの積層構造は、外部電極が半導体チップの投影面積内に形成可能なため、チップサイズまで小形化することができる。２つの異なる大きさの半導体チップは、ともにフリップチップ実装法により実装することができるため配線長を短くすることができ、同時に、高速信号の伝播およぼす悪影響を低減することができる。また、用いる半導体チップは特殊な加工が必要なく、汎用的な半導体チップを使用できる。
本発明が特許文献１と異なる部分は、可撓性を有しない配線基板１２０を備え、前記配線板１２０は大半導体チップ１１１ａを実装する面と反対側の面に外部電極１２２と、小半導体チップ１１１ｂが収納できるための空間と、小半導体チップ１１１ｂの実装高さよりも大きな厚みと、大半導体チップ１１１ａを実装するための電極および配線とを有し、小半導体チップ１１１ｂを大半導体チップ１１１ａとベース基板１１４にはさまれる位置に実装されている部分である。また、非特許文献１と異なる部分は、配線基板１２０に大半導体チップ１１１ａを実装するため、２つの異なる大きさの半導体チップをフリップチップ実装法で実装できる部分である。 Next, a manufacturing method of the laminated structure of the semiconductor chip of this example will be described with reference to the chart of FIG.
(1) First, the small semiconductor chip 111b is mounted on the base substrate 114 by a flip chip mounting method. The flip chip mounting method used here may be a bonding material using a conductive adhesive or a soldering material, but is not particularly limited.
(2) After mounting the small semiconductor chip 111b, the wiring substrate 120 is mounted on the base substrate 114. The external electrode 122 of the wiring board 120 and the base electrode 115 of the base board are joined. The bonding material used here is not particularly limited, although a conductive adhesive or solder is used for the bonding material. After mounting the wiring substrate 120 on the base substrate 114, the large semiconductor chip 111 a is mounted on the wiring substrate 120. The flip chip mounting method used here is also mounted in the same manner as when the small semiconductor chip 111b is mounted.
(3) The underfill 121 may be filled twice after the small semiconductor chip 111b and the wiring substrate 120 are mounted on the base substrate 114, and then filled again after the large semiconductor chip 111a is mounted. It is also possible to fill the chip 111a once after the chip 111a is mounted.
In this way, the manufactured semiconductor chip laminated structure can be downsized to the chip size because the external electrode can be formed within the projected area of the semiconductor chip. Since two different sized semiconductor chips can be mounted by the flip chip mounting method, the wiring length can be shortened, and at the same time, the adverse effect of high-speed signal propagation can be reduced. Moreover, the semiconductor chip to be used does not require special processing, and a general-purpose semiconductor chip can be used.
The portion where the present invention is different from Patent Document 1 is provided with a wiring board 120 having no flexibility. The wiring board 120 has an external electrode 122 and a small semiconductor chip on the surface opposite to the surface on which the large semiconductor chip 111a is mounted. A space for accommodating 111b, a thickness larger than the mounting height of the small semiconductor chip 111b, and an electrode and wiring for mounting the large semiconductor chip 111a, and the small semiconductor chip 111b and the large semiconductor chip 111a as a base It is a portion that is mounted on a position sandwiched between the substrates 114. Further, the portion different from Non-Patent Document 1 is a portion where two large semiconductor chips can be mounted by the flip chip mounting method because the large semiconductor chip 111a is mounted on the wiring board 120.

図３は、本発明の実施例２を示す半導体チップの積層構造を用いた半導体装置の側断面図である。
半導体装置は、ベース基板１１４の半導体チップを実装した面と反対側の面にはんだボール１１７を有しているため、外部と接続することができる。 FIG. 3 is a side sectional view of a semiconductor device using a laminated structure of semiconductor chips showing Embodiment 2 of the present invention.
Since the semiconductor device has the solder balls 117 on the surface of the base substrate 114 opposite to the surface on which the semiconductor chip is mounted, the semiconductor device can be connected to the outside.

本発明の実施例１を示す半導体積層構造の図で、（ａ）は側断面図、（ｂ）は上断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure of the semiconductor laminated structure which shows Example 1 of this invention, (a) is a sectional side view, (b) is an upper sectional view. 本発明の製造工程を示すチャート図である。It is a chart figure which shows the manufacturing process of this invention. 本発明の実施例２を示す半導体積層構造を用いた半導体装置の側断面図である。It is a sectional side view of the semiconductor device using the semiconductor laminated structure which shows Example 2 of this invention. 第１の従来例を示す半導体積層構造の側断面図である。It is a sectional side view of the semiconductor laminated structure which shows a 1st prior art example. 第２の従来例を示す半導体積層構造の側断面図である。It is a sectional side view of the semiconductor laminated structure which shows a 2nd prior art example.

符号の説明Explanation of symbols

１１１ 半導体チップ
１１１ａ 大半導体チップ
１１１ｂ 小半導体チップ
１１２ 可撓性を有した配線基板
１１３、１２２ 外部電極
１１４ ベース基板
１１５ ベース電極
１１６ ワイヤ配線
１１７ はんだボール
１１８ パッケージ樹脂
１１９ バンプ
１２０ 配線基板
１２１ アンダーフィル 111 Semiconductor chip 111a Large semiconductor chip 111b Small semiconductor chip 112 Flexible wiring board 113, 122 External electrode 114 Base board 115 Base electrode 116 Wire wiring 117 Solder ball 118 Package resin 119 Bump 120 Wiring board 121 Underfill

Claims (2)

形状の大きい大半導体チップと形状の小さい小半導体チップからなる２つの半導体チップと、前記２つの半導体チップを実装するための電極と配線とを有した配線基板と、前記半導体チップおよび前記配線基板を実装するための電極や配線を有したベース基板とを備え、半導体チップを立体的に実装する半導体チップの積層構造において、
前記大半導体チップは前記配線基板を介してベース基板へ実装され、前記小半導体チップは前記大半導体チップと前記ベース基板にはさまれる位置に実装され、
前記配線基板は、前記小半導体チップを収納する空間と、前記小半導体チップの実装高さよりも大きな厚みと、前記大半導体チップを実装するための電極および配線を有し、前記ベース基板と接続するための外部電極を前記大半導体チップの実装面と反対側の面に備えていることを特徴とする半導体チップの積層構造。 A wiring board having two semiconductor chips each having a large semiconductor chip having a large shape and a small semiconductor chip having a small shape; an electrode and wiring for mounting the two semiconductor chips; and the semiconductor chip and the wiring board. In a laminated structure of a semiconductor chip that includes a base substrate having electrodes and wiring for mounting, and three-dimensionally mounting the semiconductor chip,
The large semiconductor chip is mounted on a base substrate through the wiring substrate, and the small semiconductor chip is mounted at a position sandwiched between the large semiconductor chip and the base substrate,
The wiring board has a space for housing the small semiconductor chip, a thickness larger than a mounting height of the small semiconductor chip, and an electrode and wiring for mounting the large semiconductor chip, and is connected to the base substrate. An external electrode for the semiconductor chip is provided on a surface opposite to the mounting surface of the large semiconductor chip. 請求項１記載の半導体チップの積層構造を用いて、前記ベース基板の半導体チップが実装された面と反対側の面に、外部と接続するはんだボールを設けたことを特徴とする半導体装置。   2. A semiconductor device, wherein a solder ball connected to the outside is provided on a surface of the base substrate opposite to the surface on which the semiconductor chip is mounted, using the laminated structure of semiconductor chips according to claim 1.
JP2005266760A 2005-09-14 2005-09-14 Laminated structure of semiconductor chip and semiconductor device using same Pending JP2007081108A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005266760A JP2007081108A (en) 2005-09-14 2005-09-14 Laminated structure of semiconductor chip and semiconductor device using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005266760A JP2007081108A (en) 2005-09-14 2005-09-14 Laminated structure of semiconductor chip and semiconductor device using same

Publications (1)

Publication Number Publication Date
JP2007081108A true JP2007081108A (en) 2007-03-29

Family

ID=37941090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005266760A Pending JP2007081108A (en) 2005-09-14 2005-09-14 Laminated structure of semiconductor chip and semiconductor device using same

Country Status (1)

Country Link
JP (1) JP2007081108A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03104739U (en) * 1990-02-13 1991-10-30
JPH1084076A (en) * 1996-09-05 1998-03-31 Hitachi Ltd Semiconductor device and method for manufacturing the same
JP2001077293A (en) * 1999-09-02 2001-03-23 Nec Corp Semiconductor device
JP2001156251A (en) * 1999-11-25 2001-06-08 Mitsubishi Electric Corp Semiconductor device
JP2002270760A (en) * 2001-03-07 2002-09-20 Sony Corp Electronic component, assembly thereof and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03104739U (en) * 1990-02-13 1991-10-30
JPH1084076A (en) * 1996-09-05 1998-03-31 Hitachi Ltd Semiconductor device and method for manufacturing the same
JP2001077293A (en) * 1999-09-02 2001-03-23 Nec Corp Semiconductor device
JP2001156251A (en) * 1999-11-25 2001-06-08 Mitsubishi Electric Corp Semiconductor device
JP2002270760A (en) * 2001-03-07 2002-09-20 Sony Corp Electronic component, assembly thereof and its manufacturing method

Similar Documents

Publication Publication Date Title
JP2008166439A (en) Semiconductor device and manufacturing method thereof
JP2007123595A (en) Semiconductor device and its mounting structure
US10510720B2 (en) Electronic package and method for fabricating the same
JP2005175423A (en) Semiconductor package
JP2007123520A (en) Laminated semiconductor module
JP2009506571A (en) MICROELECTRONIC DEVICE HAVING INTERMEDIATE CONTACTS FOR CONNECTING TO INTERPOSER SUBSTRATE AND METHOD OF PACKAGING MICROELECTRONIC DEVICE WITH INTERMEDIATE CONTACTS RELATED TO THE SAME
KR20090039411A (en) Semiconductor package, module, system having a solder ball being coupled to a chip pad and manufacturing method thereof
WO2011086613A1 (en) Semiconductor device and method for fabricating same
KR20110124063A (en) Stack type semiconductor package
JP2005093551A (en) Package structure of semiconductor device, and packaging method
JP5012612B2 (en) Semiconductor device mounting structure and electronic device using the mounting structure
US7217995B2 (en) Apparatus for stacking electrical components using insulated and interconnecting via
JP2006295183A (en) Multi-package module provided with stacked packages having asymmetrically disposed die and molding
US7462925B2 (en) Method and apparatus for stacking electrical components using via to provide interconnection
JP2004281820A (en) Semiconductor device, electronic device, electronic apparatus, method for manufacturing semiconductor device, and method for manufacturing electronic device
JP2001077294A (en) Semiconductor device
JP2006253576A (en) Semiconductor device and manufacturing method thereof
JP2007221045A (en) Semiconductor device employing multi-chip structure
JP2005286126A (en) Semiconductor device
KR20120096754A (en) Three-dimensional stack structure of wafer chip using interposer
JP4556671B2 (en) Semiconductor package and flexible circuit board
JP4557757B2 (en) Semiconductor device
KR101374144B1 (en) Semiconductor device for preventing warpage
JP2009238855A (en) Mounting structure of semiconductor device, and electronic apparatus using mounting structure
JP2008270303A (en) Multilayer semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080818

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100701

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20101209