JP2007073752A - Led display - Google Patents

Led display Download PDF

Info

Publication number
JP2007073752A
JP2007073752A JP2005259462A JP2005259462A JP2007073752A JP 2007073752 A JP2007073752 A JP 2007073752A JP 2005259462 A JP2005259462 A JP 2005259462A JP 2005259462 A JP2005259462 A JP 2005259462A JP 2007073752 A JP2007073752 A JP 2007073752A
Authority
JP
Japan
Prior art keywords
led
pad
led display
circuit board
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005259462A
Other languages
Japanese (ja)
Inventor
Toshihiro Moriya
利弘 森谷
Koji Shinpo
浩二 新保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meiko Co Ltd
Original Assignee
Meiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Co Ltd filed Critical Meiko Co Ltd
Priority to JP2005259462A priority Critical patent/JP2007073752A/en
Publication of JP2007073752A publication Critical patent/JP2007073752A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Led Device Packages (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LED display wherein the shape of its image displaying surface is small, and its highly precise and fine image can be realized. <P>SOLUTION: The interlayer continuity structure of the LED display is formed out of column-form conductors 12 wherein conductive materials are filled into laser vias bored in insulating base materials 10. On the top surface 10a of a multilayer circuit substrate A of the LED display, pads 13 each of which comprises two pads 13a, 13b connected with the column-form conductors 12 are arranged in the form of a matrix. The LED display has picture-element dots B each of which comprises an LED element 14 mounted on the one pad 13a of the pad 13, a connective means 15 for connecting electrically the other pad 13b of the pad 13 with the LED element 14, and a resin seal 16 for sealing the pad 13, the connective means 15, and the LED element 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ＬＥＤディスプレーに関し、更に詳しくは、画素ドットそれ自体が従来よりも小さく、また画素ドット間の画素ピッチを狭くすることができるので、大幅に小型化され、かつ高精細映像を実現できる表示面を有するＬＥＤディスプレーに関する。   The present invention relates to an LED display. More specifically, since the pixel dots themselves are smaller than before and the pixel pitch between the pixel dots can be narrowed, the size can be greatly reduced and a high-definition image can be realized. The present invention relates to an LED display having a display surface.

電車の電光掲示板、バスの行先掲示板、また店舗のショーウィンドウ用の表示ボードなどには、ＬＥＤディスプレーが広く用いられている。
このＬＥＤディスプレーは、通常、次のようにして製造されている。すなわち、所定サイズの回路基板の表面に、既にデバイスとして製造されているＬＥＤを、直接、マトリックス状に実装する。したがって、製造されたＬＥＤディスプレーの表示面には、画素ドットであるＬＥＤのドットマトリックスが形成されている。このとき実装されるＬＥＤには、チップタイプ（ＳＭＴタイプ）とリードタイプが考えられる。 LED displays are widely used in electric bulletin boards for trains, bulletin boards for bus destinations, display boards for shop show windows, and the like.
This LED display is usually manufactured as follows. That is, LEDs already manufactured as devices are directly mounted in a matrix on the surface of a circuit board having a predetermined size. Therefore, an LED dot matrix which is pixel dots is formed on the display surface of the manufactured LED display. The LED mounted at this time may be a chip type (SMT type) or a lead type.

ここで、回路基板の表面に実装するチップＬＥＤとしては、次の構造のものが知られている（非特許文献１を参照）。それを模式的に図３に示す。
このチップＬＥＤは、絶縁基材１の上面に２個のパッド２ａ、２ｂが形成され、絶縁基材１の横方向の両側にＬＥＤ駆動用の電極端子３ａ、３ｂが形成されている。
電極端子３ａ、３ｂは、絶縁基材１の両側面を被覆し、その一部は絶縁基材の上面にまわり込んでパッド２ａ、２ｂとそれぞれ電気的に接続し、他の部分は絶縁基材の下面にまでまわり込んでいる。 Here, as a chip LED mounted on the surface of a circuit board, one having the following structure is known (see Non-Patent Document 1). This is schematically shown in FIG.
In this chip LED, two pads 2 a and 2 b are formed on the upper surface of the insulating base 1, and electrode terminals 3 a and 3 b for driving LEDs are formed on both sides of the insulating base 1 in the lateral direction.
The electrode terminals 3a and 3b cover both side surfaces of the insulating base material 1, a part of which goes around the upper surface of the insulating base material and is electrically connected to the pads 2a and 2b, respectively, and the other part is the insulating base material. It wraps around to the lower surface.

そして、パッド２ａの上にＬＥＤ素子４が実装され、このＬＥＤ素子と他方のパッド２ｂの間がＡｕ線５をワイヤボンディングすることにより電気的に接続されている。そして、全体は透明樹脂で樹脂封止されて、絶縁基材１の上面には樹脂封止部６が形成されている。
ＬＥＤディスプレーの製造時にこのチップＬＥＤは、絶縁基材の下面にまわり込んでいる電極端子部分と、回路基板の表面に配線されている導体回路とを接続することにより回路基板に実装される。
なお、このチップＬＥＤは、図４で示したような、大きな両面銅張り板に等間隔でスリット穴を形成し、表出した絶縁基材の側面にサイドめっきを行なったのち、フォトリソグラフィー技術とエッチング処理で２個のパッドを１組とするパッド部をスリット穴の間に位置する細長い部分に複数個形成し、そこにＬＥＤ素子の実装、ワイヤボンディング、樹脂封止を行なって、複数個のチップＬＥＤの前駆体を製作したのち、それを１個１個切断・分離することによって製造されている。
電子材料、１９９７年１０月号、５９〜６３頁 The LED element 4 is mounted on the pad 2a, and the LED element and the other pad 2b are electrically connected by wire bonding of an Au wire 5. And the whole is resin-sealed with transparent resin, and the resin sealing part 6 is formed in the upper surface of the insulating base material 1. FIG.
At the time of manufacturing the LED display, the chip LED is mounted on the circuit board by connecting the electrode terminal portion that wraps around the lower surface of the insulating base and the conductor circuit wired on the surface of the circuit board.
In addition, this chip LED is formed by forming slit holes at equal intervals on a large double-sided copper-clad plate as shown in FIG. 4 and performing side plating on the exposed side surface of the insulating base material. A plurality of pad portions each having two pads as a set are formed in an elongated portion located between the slit holes by etching treatment, and LED elements are mounted, wire bonding, and resin sealing are performed there. Chip LED precursors are manufactured and then cut and separated one by one.
Electronic Materials, October 1997, 59-63

ところで、ＬＥＤディスプレーに対しては、最近、形状の小型化、すなわち映像表示面の小型化が要求されているが、その場合であっても、同時に小型化された表示面での高精細映像の実現ということが必要とされる。
映像の高精細化ということを無視して、形状の小型化という問題だけを考えれば、それは、回路基板に実装するチップＬＥＤの形状を小型化することで対処可能である。 By the way, the LED display has recently been required to have a smaller shape, that is, a smaller image display surface. Even in this case, a high-definition image can be displayed on the smaller display surface at the same time. Realization is required.
If only the problem of miniaturization of the shape is considered ignoring the high definition of the video, it can be dealt with by miniaturizing the shape of the chip LED mounted on the circuit board.

一方、映像の高精細化は、実装するチップＬＥＤの大きさの問題ではなく、マトリックス状に配列されている画素ドットとしてのチップＬＥＤ間の画素ピッチが狭いか広いかという問題に関係し、この画素ピッチを狭くすることにより映像の高精細化を実現することができる。
したがって、形状が小型であり、同時に高精細映像を実現するＬＥＤディスプレーを製造するためには、回路基板の表面に、小型形状のチップＬＥＤを互いのピッチを狭くしてマトリックス状に配列すればよいことになる。 On the other hand, the high definition of the image is not a problem of the size of the chip LED to be mounted, but is related to the problem of whether the pixel pitch between the chip LEDs as pixel dots arranged in a matrix is narrow or wide. By reducing the pixel pitch, it is possible to achieve high definition of the video.
Therefore, in order to manufacture an LED display that has a small shape and at the same time realizes a high-definition image, it is only necessary to arrange small chip LEDs on the surface of the circuit board in a matrix form with a narrow pitch. It will be.

しかしながら、用いるチップＬＥＤが仮に小型化しても、実際問題としては、次の理由でチップＬＥＤ間の画素ピッチを狭くすることは制約を受けるので、ＬＥＤディスプレー映像表示面の形状小型化は困難である。
その理由とは、回路基板の表面にマトリックス状にチップＬＥＤを配列する場合、通常そのチップＬＥＤを適正に駆動させるために、当該チップＬＥＤの近辺に、例えば電流制御用抵抗器やそのための配線回路などの周辺部品を配置するからである。 However, even if the chip LED to be used is downsized, as a practical problem, it is difficult to reduce the shape of the LED display image display surface because the pixel pitch between the chip LEDs is restricted for the following reason. .
The reason for this is that when chip LEDs are arranged in a matrix on the surface of the circuit board, in order to drive the chip LEDs properly, a resistor for current control, for example, and a wiring circuit therefor are usually provided in the vicinity of the chip LED. This is because peripheral parts such as are arranged.

このように、回路基板の表面にはチップＬＥＤと周辺部品が同時に配置されるので、チップＬＥＤの配列態様は、その近辺に平面的に配置されているこれら周辺部品の規制を受けることになり、結局、チップＬＥＤ間のピッチを狭くすることが制約されていることになる。
このように、従来のＬＥＤディスプレーの場合、回路基板の同一表面上に、チップＬＥＤと周辺部品を同時に配置するので、画素ドットであるチップＬＥＤのマトリックス配列における相互の画素ピッチを狭くすることは困難であった。 In this way, since the chip LED and the peripheral component are simultaneously arranged on the surface of the circuit board, the arrangement mode of the chip LED is restricted by these peripheral components arranged in a plane in the vicinity thereof, After all, narrowing the pitch between the chip LEDs is restricted.
As described above, in the case of the conventional LED display, since the chip LED and the peripheral components are simultaneously arranged on the same surface of the circuit board, it is difficult to narrow the mutual pixel pitch in the matrix array of the chip LED which is the pixel dot. Met.

本発明は、従来のＬＥＤディスプレーにおける上記した問題を解決し、回路基板としてビルドアップ工法で製造した回路基板を用い、その回路基板上にＬＥＤ素子を直接マトリックス状に実装し、更に全体を透明樹脂で樹脂封止することで、画素ドットとしてのチップＬＥＤをモジュール化することにより、画素ドットの小型化と狭い画素ドット間ピッチを同時に実現している新規構造のＬＥＤディスプレーの提供を目的とする。   The present invention solves the above-described problems in conventional LED displays, uses a circuit board manufactured by a build-up method as a circuit board, and mounts LED elements directly on the circuit board in a matrix, and further transparent resin as a whole It is an object of the present invention to provide an LED display having a novel structure that simultaneously realizes downsizing of pixel dots and a narrow pitch between pixel dots by modularizing chip LEDs as pixel dots by resin sealing.

上記した目的を達成するために、本発明においては、
絶縁基材に穿設されたレーザビアに導電性材料を充填して成る柱状導体で、各層間の導通構造が形成され、かつ最上面には前記柱状導体と接続する２個のパッドから成るパッド部がマトリックス状に配列されている多層回路基板と、
前記パッド部の一方のパッド部に実装されたＬＥＤ素子と、前記パッド部の他方のパッドと前記ＬＥＤ素子間を電気的に接続する接続手段と、前記パッド部と前記接続手段と前記ＬＥＤ素子を封止する樹脂封止部とから成る画素ドットを備えていることを特徴とするＬＥＤディスプレーが提供される。 In order to achieve the above object, in the present invention,
A columnar conductor formed by filling a conductive material into a laser via drilled in an insulating base material, a conductive structure between each layer is formed, and a pad portion comprising two pads connected to the columnar conductor on the uppermost surface Multilayer circuit boards arranged in a matrix,
An LED element mounted on one pad part of the pad part, a connection means for electrically connecting the other pad of the pad part and the LED element, the pad part, the connection means, and the LED element. There is provided an LED display including a pixel dot including a resin sealing portion to be sealed.

このＬＥＤディスプレーの場合、図３で示した従来のチップＬＥＤの場合とは異なり、画素ドットの駆動信号などは、絶縁基材を上下方向に貫く柱状導体を介してパッド部に送信される。そのため、一対のパッド間の間隔を狭くすることにより画素ドットを小型化することができる。
また、画素ドットの駆動用周辺部品も当該画素ドットの近辺に配置しなくてもよくなるため、画素ドット間の間隔を狭くして映像の高精細化を実現することができる。 In the case of this LED display, unlike the case of the conventional chip LED shown in FIG. 3, a pixel dot drive signal or the like is transmitted to the pad portion via a columnar conductor penetrating the insulating base material in the vertical direction. Therefore, the pixel dot can be reduced in size by narrowing the interval between the pair of pads.
In addition, since the peripheral components for driving the pixel dots do not have to be arranged in the vicinity of the pixel dots, the interval between the pixel dots can be narrowed to achieve high definition of the image.

本発明のＬＥＤディスプレーの１例を図１に示す。また図１のII−II線に沿う断面図を図２に示す。
このＬＥＤディスプレーは、従来のＬＥＤディスプレーのように回路基板の表面に既に１個の完成デバイスであるチップＬＥＤが実装された構造ではなく、ビルドアップ工法で製造された多層回路基板の最上面に、チップＬＥＤと同一機能を有する後述の画素ドットが一体的に組付けられた構造になっていることを特徴とする。 An example of the LED display of the present invention is shown in FIG. FIG. 2 is a cross-sectional view taken along line II-II in FIG.
This LED display is not a structure in which a chip LED, which is one completed device, is already mounted on the surface of the circuit board like a conventional LED display, but on the uppermost surface of a multilayer circuit board manufactured by a build-up method, It has a structure in which pixel dots, which will be described later, having the same function as the chip LED are integrally assembled.

すなわち、多層回路基板（図では３層構造の基板）Ａにおける最上層の基板Ａ３の上に、後述する画素ドットＢが複数個組付けられた構造になっている。
そして、この多層回路基板Ａの背面、すなわち、画素ドットＢの組付け面とは反対側の面に形成されている導体回路に、画素ドットＢを適正に駆動するための各種の周辺部品Ｃが実装されている。 In other words, (in the figure the substrate having a three-layer structure) multi-layer circuit board on the top layer of the substrate A 3 in A, has become the pixel dots B to be described later assembled plurality structure.
Various peripheral components C for appropriately driving the pixel dots B are formed on the conductor circuit formed on the back surface of the multilayer circuit board A, that is, the surface opposite to the assembly surface of the pixel dots B. Has been implemented.

多層回路基板Ａにおける各基板Ａ１、Ａ２、Ａ３には、いずれも、それぞれの絶縁基材１０の上面１０ａと下面１０ｂにそれぞれ所定パターンの導体回路１１ａ、１１ｂが形成されている。これら導体回路側の導通構造は、絶縁基材１０に穿設したレーザビアに導電性材料を充填することによって形成した柱状導体１２で形成されている。
最上層の基板Ａ３の上面１０ａには、２個のパッド１３ａ、１３ｂが形成されてパッド部１３を構成している。そして、パッド１３ａとパッド１３ｂは、いずれも、柱状導体１２を介して基板Ａ２の上面に形成されている導体回路１１ａと電気的に接続されている。 In each of the substrates A 1 , A 2 , and A 3 in the multilayer circuit substrate A, conductor circuits 11 a and 11 b having predetermined patterns are formed on the upper surface 10 a and the lower surface 10 b of the insulating base material 10, respectively. These conductive structures on the conductor circuit side are formed of columnar conductors 12 formed by filling a laser via formed in the insulating base material 10 with a conductive material.
Two pads 13 a and 13 b are formed on the upper surface 10 a of the uppermost substrate A 3 to form a pad portion 13. The pads 13a and the pads 13b are both are electrically connected to the conductor circuits 11a formed on the upper surface of the substrate A 2 through a columnar conductor 12.

この多層回路基板Ａはビルドアップ工法で製造される。
まず、両面に所定パターンの導体回路が形成され、導体回路間は柱状導体で電気的に接続されている基板Ａ１をコア基板として製造する。この基板Ａ１の上にＢステージ状態の例えばガラス繊維強化エポキシ樹脂のプリプレグ材と銅箔を順次重ね合わせて熱圧プレスを行ない、プリプレグ材を熱硬化させて絶縁基材１０にするとともにそれを基板Ａ１の上面に接合する。 This multilayer circuit board A is manufactured by a build-up method.
First, the conductor circuit having a predetermined pattern is formed on both sides, between the conductor circuits is to produce a substrate A 1 which is electrically connected with the columnar conductor as a core substrate. The sequentially superposed prepreg material and the copper foil of the B-stage such as glass fiber-reinforced epoxy resin on the substrate A 1 and subjected to hot pressing, it with the prepreg material to the insulating substrate 10 by thermally curing bonded to the upper surface of the substrate a 1.

ついで、柱状導体を形成すべき位置の銅箔の一部を除去し、表出した絶縁基材に基板Ａ１の導体回路１１ａにまで至るレーザビアを穿設したのち、そこに例えば銅めっき処理を行なって当該レーザビアを銅で充填して柱状導体１２を形成する。
ついで、表面の銅箔にフォトリソグラフィー技術とエッチング処理を施して所定パターンの導体回路を形成することにより、基板Ａ２を基板Ａ１の上に組上げる。 Then, to remove a portion of the copper foil position for forming the columnar conductor, after drilling the laser via extending to a conductor circuit 11a of the substrate A 1 to exposed the insulating substrate, there, for example, copper plating treatment The columnar conductor 12 is formed by filling the laser via with copper.
Next, the substrate A 2 is assembled on the substrate A 1 by applying a photolithographic technique and an etching process to the copper foil on the surface to form a conductor circuit having a predetermined pattern.

そして、この基板Ａ２の上に、再び絶縁基材と銅箔を順次重ね合わせて熱圧プレスを行ない、絶縁基材へのレーザビアの穿設と銅めっき処理を行なって基板Ａ２の導体回路と接続する柱状導体を形成したのち、銅箔に、フォトリソグラフィー技術とエッチング処理を適用して、パッド１３ａ、１３ｂを１組とするパッド部１３が所定のマトリックスを構成するように所定の位置に形成されている基板Ａ３を基板Ａ２の上に組上げる。 Then, on this substrate A 2, again sequentially superimposed an insulating base material and the copper foil subjected to hot pressing, the conductor circuit of the substrate A 2 performs a drilled copper plating treatment laser via in the insulating substrate After forming the columnar conductor to be connected to the copper foil, the photolithography technique and the etching process are applied to the copper foil, and the pad portion 13 including the pads 13a and 13b as a set is placed in a predetermined position so as to form a predetermined matrix. assembling the substrate a 3 which is formed on the substrate a 2.

このようにして製造された多層回路基板の基板Ａ３の上に、続いて画素ドットＢが組付けられる。
すなわち、多層回路基板Ａの基板Ａ３上に形成されている一方のパッド１３ａにＬＥＤ素子１４を実装し、このＬＥＤ素子１４の接続端子と他方のパッド１３ｂとの間にＡｕ線（接続手段）１５をワイヤボンディングし、更にこれらパッド部１３とＬＥＤ素子１４とＡｕ線１５を、例えば透明樹脂で封止して樹脂封止部１６を形成することによって画素ドットＢが、基板Ａ３の上に一体的に組付けられる。 Thus on the substrate A 3 of the multilayer circuit board is manufactured, followed by pixel dots B is assembled.
Namely, the LED element 14 is mounted on one of the pads 13a formed on the substrate A 3 of the multilayer circuit board A, Au line between the connection terminal and the other pad 13b of the LED element 14 (connection means) 15 and wire bonding, further these pad portion 13 and the LED element 14 and the Au wire 15, for example, sealed with a transparent resin pixel dot B by forming a resin sealing portion 16, on the substrate a 3 It is assembled integrally.

そして、多層回路基板Ａの背面、すなわち基板Ａ１の導体回路１１ｂには、ＬＥＤ素子１４を適正に駆動するための周辺部品Ｃが実装される。
なお、周辺部品Ｃの実装に関しては、図２のように、多層回路基板Ａの背面に実装されることに限定されることなく、例えば、ビルドアップ工法の過程で各基板の層間に実装して最終的には多層回路基板Ａに内蔵されるようにしてもよい。 Then, the back surface of the multilayer circuit board A, that is, the conductor circuit 11b of the substrate A 1, peripheral components C for properly driving the LED elements 14 are mounted.
The mounting of the peripheral component C is not limited to being mounted on the back surface of the multilayer circuit board A as shown in FIG. 2, for example, it is mounted between the layers of each board during the build-up method. Finally, it may be built in the multilayer circuit board A.

本発明のＬＥＤディスプレーは、上記したような構造になっているので、次のような効果を奏する。
１．まず、基板Ａ３の上には、画素ドットＢのみが配列されてドットマトリックスを構成していて、画素ドットのＬＥＤ素子を駆動する周辺部品Ｃは基板Ａ１の背面（または層間）に実装されているので、画素ドットの配列は、従来のように周辺部品で規制されることはない。そのため、画素ドットＢの相互間のピッチを狭くすることができ、高精細映像の実現が可能となる。 Since the LED display of the present invention has the above-described structure, the following effects can be obtained.
1. First, on the substrate A 3, only the pixel dots B is constituted the dot matrix are arranged, a peripheral component C to drive the LED elements of the pixel dots is mounted on the rear surface of the substrate A 1 (or interlayer) Therefore, the arrangement of pixel dots is not restricted by peripheral components as in the conventional case. Therefore, the pitch between the pixel dots B can be narrowed, and high definition video can be realized.

２．また、多層回路基板Ａにおける各層間の導通構造は、各層を上下方向に貫通する柱状導体で形成されていて、画素ドット内のＬＥＤ素子への駆動信号はこの柱状導体からパッド部を介して当該ＬＥＤ素子に上下方向から入力し、図３で示した従来のチップＬＥＤのように両側から平面的に入力するのではない。
したがって、このＬＥＤディスプレーの場合、平面的な大きさが従来のチップＬＥＤの平面的な大きさよりも小さい画素ドットを多層回路基板の上に配列することができる。すなわち、発光源を従来に比べて小型化することができる。 2. In addition, the conductive structure between the layers in the multilayer circuit board A is formed by columnar conductors that penetrate each layer in the vertical direction, and drive signals to the LED elements in the pixel dots are transmitted from the columnar conductors through the pads. The LED element is input from above and below, and is not input in a planar manner from both sides like the conventional chip LED shown in FIG.
Therefore, in the case of this LED display, pixel dots whose planar size is smaller than the planar size of the conventional chip LED can be arranged on the multilayer circuit board. That is, the light emitting source can be reduced in size as compared with the conventional one.

３．このＬＥＤディスプレーの場合、画素ドットは、ビルドアップ工法で多層回路基板を製造する最後の工程として形成することができ、従来のように完成したデバイスである
チップＬＥＤを回路基板の上に実装してドットマトリックスを形成するのではないので、ＬＥＤディスプレーの製造時における全体の製造工程は簡略化し、その結果、製造コストも低減する。 3. In the case of this LED display, the pixel dots can be formed as the last step of manufacturing a multilayer circuit board by a build-up method, and a chip LED, which is a completed device as in the past, is mounted on the circuit board. Since the dot matrix is not formed, the entire manufacturing process when manufacturing the LED display is simplified, and as a result, the manufacturing cost is also reduced.

本発明のＬＥＤディスプレーは、従来のチップＬＥＤよりも形状が小型化している画素ドットを、狭いピッチで配列してドットマトリックスが形成されているので、全体の形状は小型であり、しかも高精細映像を実現することができる。   In the LED display of the present invention, since the dot matrix is formed by arranging pixel dots whose shape is smaller than that of the conventional chip LED at a narrow pitch, the overall shape is small, and high definition video Can be realized.

本発明のＬＥＤディスプレーの１例を示す斜視図である。It is a perspective view which shows one example of the LED display of this invention. 図１のII−II線に沿う部分断面図である。It is a fragmentary sectional view which follows the II-II line of FIG. 従来のチップＬＥＤの一部を示す断面図である。It is sectional drawing which shows a part of conventional chip LED. 図３のチップＬＥＤの製造時に用いる銅張り板にスリット穴を形成した状態を示す斜視図である。It is a perspective view which shows the state which formed the slit hole in the copper clad board used at the time of manufacture of chip LED of FIG.

符号の説明Explanation of symbols

１、１０ 絶縁基材
１０ａ 絶縁基材１０ａ上面
１０ｂ 〃 下面
１１ａ、１１ｂ 導体回路
１２ 柱状導体
２ａ、２ｂ、１３ａ、１３ｂ パッド
１３ パッド部
４、１４ ＬＥＤ素子
５、１５ Ａｕ線（接続手段）
６、１６ 樹脂封止部
Ａ 多層回路基板
Ａ１、Ａ２、Ａ３ 基板
Ｂ 画素ドット
Ｃ 周辺部品 DESCRIPTION OF SYMBOLS 1, 10 Insulating base material 10a Insulating base material 10a Upper surface 10b 〃 Lower surface 11a, 11b Conductor circuit 12 Columnar conductor 2a, 2b, 13a, 13b Pad 13 Pad part 4, 14 LED element 5, 15 Au wire (connection means)
6, 16 Resin sealing part A Multi-layer circuit board A 1 , A 2 , A 3 board B Pixel dot C Peripheral parts

Claims (2)

絶縁基材に穿設されたレーザビアに導電性材料を充填して成る柱状導体で各層間の導通構造が形成され、かつ最上面には、前記柱状導体と接続する２個のパッドから成るパッド部がマトリックス状に配列されている多層回路基板と、
前記パッド部の一方のパッドに実装されたＬＥＤ素子と、前記パッド部の他方のパッドと前記ＬＥＤ素子間を電気的に接続する接続手段と、前記パッド部と前記接続手段と前記ＬＥＤ素子を封止する樹脂封止部とから成る画素ドットを備えていることを特徴とするＬＥＤディスプレー。 A conductive structure between each layer is formed by a columnar conductor formed by filling a conductive material into a laser via drilled in an insulating base material, and a pad portion comprising two pads connected to the columnar conductor on the uppermost surface Multilayer circuit boards arranged in a matrix,
An LED element mounted on one pad of the pad portion; a connection means for electrically connecting the other pad of the pad portion to the LED element; and the pad portion, the connection means, and the LED element are sealed. An LED display comprising a pixel dot comprising a resin sealing portion to be stopped. 前記多層回路基板の背面または／および層間に、前記画素ドットの駆動用周辺部品が実装されている請求項１のＬＥＤディスプレー。   The LED display according to claim 1, wherein peripheral components for driving the pixel dots are mounted on the back surface and / or the interlayer of the multilayer circuit board.
JP2005259462A 2005-09-07 2005-09-07 Led display Pending JP2007073752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005259462A JP2007073752A (en) 2005-09-07 2005-09-07 Led display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005259462A JP2007073752A (en) 2005-09-07 2005-09-07 Led display

Publications (1)

Publication Number Publication Date
JP2007073752A true JP2007073752A (en) 2007-03-22

Family

ID=37934943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005259462A Pending JP2007073752A (en) 2005-09-07 2005-09-07 Led display

Country Status (1)

Country Link
JP (1) JP2007073752A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100875961B1 (en) 2007-11-29 2008-12-26 삼성전기주식회사 Array light source using led and backlight unit having it
JP2009231634A (en) * 2008-03-24 2009-10-08 Toshiba Lighting & Technology Corp Substrate device and illuminator
JP2016538586A (en) * 2013-12-17 2016-12-08 ルクスビュー テクノロジー コーポレイション Display module and system application
WO2017126160A1 (en) * 2016-01-19 2017-07-27 三菱電機株式会社 Led display panel, led display apparatus, and method for manufacturing led display panel
KR20170101058A (en) * 2016-02-26 2017-09-05 엘지이노텍 주식회사 Display control apparatus and method
CN108140694A (en) * 2015-10-05 2018-06-08 索尼半导体解决方案公司 Light-emitting device
CN109411455A (en) * 2018-09-27 2019-03-01 佛山市国星光电股份有限公司 A kind of LED display unit group and display panel
JP2019192800A (en) * 2018-04-25 2019-10-31 シャープ株式会社 Light-emitting element module
WO2020009349A1 (en) * 2018-07-04 2020-01-09 주식회사 루멘스 Micro-led display module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000089694A (en) * 1998-09-07 2000-03-31 Rohm Co Ltd Dot matrix display device
JP2003124528A (en) * 2001-08-09 2003-04-25 Matsushita Electric Ind Co Ltd Led illumination device and card led illumination light source

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000089694A (en) * 1998-09-07 2000-03-31 Rohm Co Ltd Dot matrix display device
JP2003124528A (en) * 2001-08-09 2003-04-25 Matsushita Electric Ind Co Ltd Led illumination device and card led illumination light source

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100875961B1 (en) 2007-11-29 2008-12-26 삼성전기주식회사 Array light source using led and backlight unit having it
JP2009231634A (en) * 2008-03-24 2009-10-08 Toshiba Lighting & Technology Corp Substrate device and illuminator
EP3521972A1 (en) * 2013-12-17 2019-08-07 Apple Inc. Display module and system applications
US11362076B2 (en) 2013-12-17 2022-06-14 Apple Inc Display module and system applications
CN110231852A (en) * 2013-12-17 2019-09-13 苹果公司 Display module and system application
KR101820258B1 (en) * 2013-12-17 2018-01-18 애플 인크. Display module and system applications
CN110231852B (en) * 2013-12-17 2024-02-02 苹果公司 Display module and system application
US11676953B2 (en) 2013-12-17 2023-06-13 Apple Inc. Display module and system applications
US10957678B2 (en) 2013-12-17 2021-03-23 Apple Inc. Display module and system applications
US10535642B2 (en) 2013-12-17 2020-01-14 Apple Inc. Display module and system applications
US10147711B2 (en) 2013-12-17 2018-12-04 Apple Inc. Display module and system applications
US9922966B2 (en) 2013-12-17 2018-03-20 Apple Inc. Display module and system applications
JP2016538586A (en) * 2013-12-17 2016-12-08 ルクスビュー テクノロジー コーポレイション Display module and system application
US10840226B2 (en) 2015-10-05 2020-11-17 Sony Semiconductor Solutions Corporation Light-emitting apparatus
CN108140694A (en) * 2015-10-05 2018-06-08 索尼半导体解决方案公司 Light-emitting device
EP3407396A4 (en) * 2016-01-19 2019-01-02 Mitsubishi Electric Corporation Led display panel, led display apparatus, and method for manufacturing led display panel
US10403802B2 (en) 2016-01-19 2019-09-03 Mitsubishi Electric Corporation Method for manufacturing LED display panel
WO2017126160A1 (en) * 2016-01-19 2017-07-27 三菱電機株式会社 Led display panel, led display apparatus, and method for manufacturing led display panel
JPWO2017126160A1 (en) * 2016-01-19 2018-04-12 三菱電機株式会社 LED display panel, LED display device, and method of manufacturing LED display panel
KR20170101058A (en) * 2016-02-26 2017-09-05 엘지이노텍 주식회사 Display control apparatus and method
KR102530697B1 (en) * 2016-02-26 2023-05-10 엘지이노텍 주식회사 Display control apparatus and method
CN110400795A (en) * 2018-04-25 2019-11-01 夏普株式会社 Light-emitting device module
JP7267683B2 (en) 2018-04-25 2023-05-02 シャープ株式会社 Light-emitting element module
CN110400795B (en) * 2018-04-25 2023-09-22 夏普株式会社 Light-emitting element module
JP2019192800A (en) * 2018-04-25 2019-10-31 シャープ株式会社 Light-emitting element module
WO2020009349A1 (en) * 2018-07-04 2020-01-09 주식회사 루멘스 Micro-led display module
CN109411455A (en) * 2018-09-27 2019-03-01 佛山市国星光电股份有限公司 A kind of LED display unit group and display panel

Similar Documents

Publication Publication Date Title
JP2007073752A (en) Led display
JP5002470B2 (en) Package substrate
JP6128046B2 (en) Mounting board and electronic equipment
JP2003264253A (en) Semiconductor device and method of manufacturing the same
US9743534B2 (en) Wiring board with built-in electronic component and method for manufacturing the same
JP2007035689A (en) Method of manufacturing electronic component built-in substrate
KR100643935B1 (en) Parallel-type chip embedded pcb and method of the same
JP2010251376A (en) Wiring body, method of manufacturing the same, and electronic equipment
JP2009289802A (en) Module having electronic part built-in and production method thereof
JP5454681B2 (en) Module substrate and manufacturing method thereof
JP5238274B2 (en) Wiring circuit board and manufacturing method thereof
JP2006237320A (en) Flexible mounting substrate
JP2010062199A (en) Circuit board
JP5524315B2 (en) Display element module using multilayer flexible printed wiring board
JP2715934B2 (en) Multilayer printed wiring board device and method of manufacturing the same
CN113811097B (en) Circuit board with high reflectivity and preparation method thereof
JP2017139489A (en) Display device
JP2014149489A (en) Light emission device and electronic equipment
KR102378493B1 (en) Film for package substrate, semiconductor package, display device and methods of fabricating the same
JPH10261854A (en) Printed wiring board and manufacturing method thereof
JP4643281B2 (en) Multilayer flexible printed wiring board and manufacturing method thereof
JP2019125746A (en) Electronic component mounting substrate, circuit board, and manufacturing method of electronic component mounting substrate
JP2013102001A (en) Wiring board and organic device using the same
JP2009129933A (en) Multilayer printed wiring board and method of manufacturing the same
JP2003060324A (en) Printed wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080827

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101222

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110420