JP2007073566A - Semiconductor device and method of mounting semiconductor - Google Patents

Semiconductor device and method of mounting semiconductor Download PDF

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JP2007073566A
JP2007073566A JP2005255782A JP2005255782A JP2007073566A JP 2007073566 A JP2007073566 A JP 2007073566A JP 2005255782 A JP2005255782 A JP 2005255782A JP 2005255782 A JP2005255782 A JP 2005255782A JP 2007073566 A JP2007073566 A JP 2007073566A
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conductor pattern
semiconductor
electrode pad
semiconductor chip
electrode pads
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JP4744246B2 (en
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Tomoaki Kuroishi
友明 黒石
Daido Komyoji
大道 光明寺
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing cost, and to provide a method of mounting the same. <P>SOLUTION: The semiconductor device is provided with a conductor pattern 2 projecting from a printed wiring board 1, which is pinched by an electrode pad 4a formed on the backside of a first semiconductor chip 3a, and an electrode pad 4b formed on the backside of a second semiconductor chip 3b. In this case, a width of mounting places of the first and second semiconductor chips in the conductor pattern 2 is made smaller than that of the electrode pads, and both electrode pads are bonded together. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体チップをプリント配線基板上に実装した半導体装置および半導体実装方法に関するものである。   The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a printed wiring board, and a semiconductor mounting method.

近年、電子部品として半導体パッケージに代えてベアチップを実装するベアチップ実装が利用され、実装面積の大幅縮小が実現されている。（特許文献１）などには図８（ａ）（ｂ）に示すように、プリント配線基板１から突出した導体パターン２に対して、半導体チップ３の裏面に形成された電極パッド４を熱圧着で接合している。５はプリント配線基板１における前記第１，第２の半導体チップ３ａ，３ｂの実装位置に形成された孔である。   In recent years, bare chip mounting, in which a bare chip is mounted instead of a semiconductor package as an electronic component, has been used, and the mounting area has been greatly reduced. As shown in FIGS. 8A and 8B, the electrode pad 4 formed on the back surface of the semiconductor chip 3 is thermocompression-bonded to the conductor pattern 2 protruding from the printed wiring board 1, as shown in FIGS. It is joined with. Reference numeral 5 denotes a hole formed at the mounting position of the first and second semiconductor chips 3a and 3b on the printed wiring board 1.

また、実装密度を向上させるために図９に示すように、プリント配線基板１から突出した導体パターン２を、第１の半導体チップ３ａの裏面に形成された電極パッド４ａと、第２の半導体チップ３ｂの裏面に形成された電極パッド４ｂで挟持して、熱圧着で接合することも行われている。
特開昭６４−７７１３５号公報 In order to improve the mounting density, as shown in FIG. 9, the conductor pattern 2 protruding from the printed wiring board 1 is provided with an electrode pad 4a formed on the back surface of the first semiconductor chip 3a and a second semiconductor chip. It is also carried out by being sandwiched between electrode pads 4b formed on the back surface of 3b and bonded by thermocompression bonding.
Japanese Unexamined Patent Publication No. 64-77135

このように従来では、半導体チップの電極パッドと導体パターンとを熱圧着させて接合しているため、導体パターンには電極パッドと同じ材質のメッキを施すことが必要である。具体的には、一般的に電極パッドがＡｕであるため、導体パターンにＡｕメッキを施す必要があり、材料価格を安価にできない。   Thus, conventionally, since the electrode pad of the semiconductor chip and the conductor pattern are bonded by thermocompression bonding, the conductor pattern must be plated with the same material as the electrode pad. Specifically, since the electrode pad is generally Au, it is necessary to apply Au plating to the conductor pattern, and the material price cannot be reduced.

本発明は実装密度を高くするために、図９のように、第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した場合に、従来よりもコストの低減を期待できる半導体装置とその実装方法を提供することを目的とする。   In order to increase the mounting density according to the present invention, as shown in FIG. 9, an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip, An object of the present invention is to provide a semiconductor device and a mounting method thereof that can be expected to reduce the cost as compared with the conventional device when mounted with a conductor pattern protruding from the surface.

本発明の請求項１記載の半導体装置は、第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した半導体装置であって、前記導体パターンにおける第１，第２の半導体チップの実装個所の幅を前記電極パットの幅よりも狭く形成して、両電極パット同士を接合させたことを特徴とする。   The semiconductor device according to claim 1 of the present invention is a conductor pattern protruding from a printed wiring board with an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip. In the semiconductor device mounted with the electrode pad interposed therebetween, the width of the mounting portion of the first and second semiconductor chips in the conductor pattern is formed narrower than the width of the electrode pad, and the electrode pads are joined to each other. It is characterized by.

本発明の請求項２記載の半導体装置は、第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した半導体装置であって、前記導体パターンにおける第１，第２の半導体チップの実装個所を前記電極パットの幅よりも狭くなる括れ部を形成して、前記括れ部において両電極パット同士が接合したことを特徴とする。   According to a second aspect of the present invention, there is provided a conductive pattern protruding from a printed wiring board with an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip. A semiconductor device mounted on both sides of the conductor pattern, wherein a constriction portion is formed in which the first and second semiconductor chip mounting portions in the conductor pattern are narrower than the width of the electrode pad, and both electrode pads are formed in the constriction portion. It is characterized by joining together.

本発明の請求項３記載の半導体装置は、第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した半導体装置であって、前記導体パターンにおける第１，第２の半導体チップの実装個所に孔を形成して、前記孔において両電極パット同士が接合したことを特徴とする。   According to a third aspect of the present invention, there is provided a semiconductor pattern in which an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip are projected from the printed wiring board. The semiconductor device is mounted with a hole formed in the conductive pattern where the first and second semiconductor chips are mounted, and the electrode pads are joined to each other in the hole.

本発明の請求項４記載の半導体実装方法は、第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装するに際し、両電極パットの間に導体パターンを挟んだ状態で第１，第２の半導体チップを圧着して、両電極パットの間に挟まれる導体パターンで前記両電極パッドを変形させ、電極パッド同士を金属接合させることを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor mounting method comprising: an electrode pad formed on the back surface of the first semiconductor chip; and an electrode pad formed on the back surface of the second semiconductor chip; When mounting by sandwiching the pattern, the first and second semiconductor chips are pressure-bonded with the conductor pattern sandwiched between the electrode pads, and the electrode pads are held by the conductor pattern sandwiched between the electrode pads. The electrode pads are deformed to be metal-bonded.

本発明によれば、第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとが当接して接合され、両電極パッドによってプリント配線基板の導体パターンが挟持された電気接続を得ることができる。   According to the present invention, the electrode pad formed on the back surface of the first semiconductor chip and the electrode pad formed on the back surface of the second semiconductor chip are brought into contact with each other, and the conductor of the printed wiring board is joined by both electrode pads. An electrical connection in which the pattern is sandwiched can be obtained.

以下、本発明の半導体実装方法を具体的な実施の形態に基づいて説明する。
なお、従来例を示す図８，図９と同様の作用をなすものには同一の符号を付けて説明する。 Hereinafter, a semiconductor mounting method of the present invention will be described based on specific embodiments.
In addition, the same code | symbol is attached | subjected and demonstrated to what makes the same effect | action as FIG. 8, FIG. 9 which shows a prior art example.

（実施の形態１）
図１（ａ）〜（ｄ）は本発明の半導体実装方法の工程を示し、図２と図３は仕上がり状態の半導体装置の拡大断面図と平面図を示している。 (Embodiment 1)
1A to 1D show the steps of the semiconductor mounting method of the present invention, and FIGS. 2 and 3 show an enlarged cross-sectional view and a plan view of the finished semiconductor device.

図１（ａ）では、第１の半導体チップ３ａの裏面に形成された電極パッド４ａと、第２の半導体チップ３ｂの裏面に形成された電極パッド４ｂとに対して、紫外線ＵＶを照射することで、電極パッド４ａ，４ｂの表面を活性化する。ここでは、電極パッド４ａ，４ｂの材質は何れもＡｕであった。   In FIG. 1A, ultraviolet rays UV are irradiated to the electrode pad 4a formed on the back surface of the first semiconductor chip 3a and the electrode pad 4b formed on the back surface of the second semiconductor chip 3b. Thus, the surfaces of the electrode pads 4a and 4b are activated. Here, the material of the electrode pads 4a and 4b was Au.

図１（ｂ）では、プリント配線基板１から突出した導体パターン２を中央にして、第１の半導体チップ３ａの電極パッド４ａと第２の半導体チップ３ｂの電極パッド４ｂとで挟む。導体パターン２の材質はＡｕよりも硬いものが使用されている。具体的には、導体パターン２はＣｕなど、Ａｕより硬い材料でできている。   In FIG. 1B, the conductor pattern 2 protruding from the printed wiring board 1 is centered and sandwiched between the electrode pad 4a of the first semiconductor chip 3a and the electrode pad 4b of the second semiconductor chip 3b. The conductor pattern 2 is made of a material harder than Au. Specifically, the conductor pattern 2 is made of a material harder than Au, such as Cu.

図１（ｃ）では、第１，第２の半導体チップ３ａ，３ｂの背面にツール（図示せず）を押し当てて、熱と矢印Ｆ１，Ｆ２の力を与える。このとき、半導体チップ３ａ、３ｂの電極パッドはそれぞれ、図１（ｄ）のように導体パターン２の両側６で、第１の半導体チップ３ａの電極パッド４ａと第２の半導体チップ３ｂ，の電極パッド４ｂとが接触して機械的に十分な強度になるまで、加圧、加熱され、機械的な接合と電気的な接合を同時に実現する。   In FIG.1 (c), a tool (not shown) is pressed on the back surface of the 1st, 2nd semiconductor chip 3a, 3b, and a heat | fever and the force of arrow F1, F2 are given. At this time, the electrode pads of the semiconductor chips 3a and 3b are on both sides 6 of the conductor pattern 2 as shown in FIG. 1D, and the electrodes of the electrode pads 4a and the second semiconductor chips 3b of the first semiconductor chip 3a. Pressing and heating are performed until the pad 4b comes into contact with the pad 4b and has sufficient mechanical strength, so that mechanical bonding and electrical bonding are realized simultaneously.

なお、両面が露出した導体パターンの幅を“ａ”、高さ（厚さ）を“ｃ”とすると、電極パッド４ａ，４ｂの幅“ｂ”は“ａ＋２ｃ”、電極パッド４ａ，４ｂの高さｄは“２ｃ”以上が望ましい。また、間に挟まれる配線基板の両面が露出した導体パターンはＣｕなど、Ａｕより硬い材料でできており、圧着時の荷重による導体パターン２の変形は、半導体チップの電極パッド４ａ，４ｂの変形より小さい。   When the width of the conductor pattern with both surfaces exposed is “a” and the height (thickness) is “c”, the width “b” of the electrode pads 4a and 4b is “a + 2c” and the height of the electrode pads 4a and 4b. The length d is preferably “2c” or more. Also, the conductive pattern with both surfaces of the wiring board sandwiched between them is made of a material harder than Au, such as Cu, and the deformation of the conductive pattern 2 due to the load at the time of crimping is the deformation of the electrode pads 4a and 4b of the semiconductor chip. Smaller than.

この構成によれば、導体パターン２が電極パッド４ａ，４ｂによって挟持されると共に、電極パッド４ａ，４ｂの同士が接触して接合されるため、導体パターン２に対しＡｕメッキなどの処理をなくしても、良好な接合状態が得られる。さらに、電極パッド４ａ，４ｂによって導体パターン２を包み込んでいるため、従来に比べて導体パターンの厚み分だけ薄くできる。   According to this configuration, the conductor pattern 2 is sandwiched between the electrode pads 4a and 4b, and the electrode pads 4a and 4b are brought into contact with each other, so that the conductor pattern 2 is not subjected to processing such as Au plating. Also, a good bonding state can be obtained. Furthermore, since the conductor pattern 2 is wrapped by the electrode pads 4a and 4b, it can be made thinner by the thickness of the conductor pattern than in the prior art.

（実施の形態２）
図４（ａ）（ｂ）は本発明の（実施の形態２）を示す。
上記の（実施の形態１）では、電極パッド４ａ，４ｂは導体パターン２よりも幅が広く構成されていたが、この実施の形態では電極パッド４ａ，４ｂは導体パターン２と幅がほぼ同じで、導体パターン２における前記第１，第２の半導体チップ３ａ，３ｂの実装個所にだけ両側から切り欠き部７を形成して括れ部８を形成して、前記の加圧、加熱によって電極パッド４ａ，４ｂが前記括れ部８の両側において接触して接合される点だけが異なっている。 (Embodiment 2)
4A and 4B show (Embodiment 2) of the present invention.
In the above (Embodiment 1), the electrode pads 4a and 4b are configured to be wider than the conductor pattern 2, but in this embodiment, the electrode pads 4a and 4b are substantially the same in width as the conductor pattern 2. The notch 7 is formed from both sides to form the constricted portion 8 only at the mounting positions of the first and second semiconductor chips 3a and 3b in the conductor pattern 2, and the electrode pad 4a is formed by the pressurization and heating. , 4b are different only in that they are brought into contact with each other on both sides of the constricted portion 8.

（実施の形態３）
図５は本発明の（実施の形態３）を示す。
図４の電極パッド４ａ，４ｂは導体パターン２と幅がほぼ同じであったが、この図５では電極パッド４ａ，４ｂの幅が導体パターン２の幅よりも大きい点だけが（実施の形態２）とは異なっている。 (Embodiment 3)
FIG. 5 shows (Embodiment 3) of the present invention.
The electrode pads 4a and 4b in FIG. 4 have almost the same width as the conductor pattern 2, but in FIG. 5, only the width of the electrode pads 4a and 4b is larger than the width of the conductor pattern 2 (Embodiment 2). ) Is different.

（実施の形態４）
図６は本発明の（実施の形態４）を示す。
上記の（実施の形態１）では、電極パッド４ａ，４ｂは導体パターン２よりも幅が広く構成されていたが、この実施の形態では電極パッド４ａ，４ｂは導体パターン２と幅がほぼ同じで、導体パターン２における前記第１，第２の半導体チップ３ａ，３ｂの実装個所にだけ孔９を形成して、前記の加圧、加熱によって電極パッド４ａ，４ｂが前記孔９の内側において接触して接合される点だけが異なっている。 (Embodiment 4)
FIG. 6 shows (Embodiment 4) of the present invention.
In the above (Embodiment 1), the electrode pads 4a and 4b are configured to be wider than the conductor pattern 2, but in this embodiment, the electrode pads 4a and 4b are substantially the same in width as the conductor pattern 2. A hole 9 is formed only at the mounting position of the first and second semiconductor chips 3a and 3b in the conductor pattern 2, and the electrode pads 4a and 4b come into contact with the inside of the hole 9 by the pressurization and heating. The only difference is that they are joined together.

（実施の形態５）
図７は本発明の（実施の形態５）を示す。
図６の電極パッド４ａ，４ｂは導体パターン２と幅がほぼ同じであったが、この図７では電極パッド４ａ，４ｂの幅が導体パターン２の幅よりも大きい点だけが（実施の形態４）とは異なっている。 (Embodiment 5)
FIG. 7 shows (Embodiment 5) of the present invention.
The electrode pads 4a and 4b in FIG. 6 have substantially the same width as the conductor pattern 2, but in FIG. 7, only the width of the electrode pads 4a and 4b is larger than the width of the conductor pattern 2 (Embodiment 4). ) Is different.

このように構成することによって、前記の加圧、加熱によって電極パッド４ａ，４ｂが前記孔９の内側だけでなく、導体パターン２の両側からはみ出した６ａの部位でも接触して接合される。   With this configuration, the electrode pads 4a and 4b are brought into contact and bonded not only inside the hole 9 but also at the portion 6a protruding from both sides of the conductor pattern 2 by the pressurization and heating.

なお、上記の図４と図５では導体パターン２の括れ部８は導電パターン２の両側から切り欠いて形成したが、片側から切り欠いて括れ部を形成しても同様である。   4 and 5, the constricted portion 8 of the conductor pattern 2 is cut out from both sides of the conductive pattern 2. However, the constricted portion may be formed by cutting out from one side.

本発明の半導体装置構造は、薄型半導体チップを積層して実装するとき、薄型かつ安価に実装することができ、低背化する事が容易であるので、半導体を積層実装するパッケージなどに適用できる。   The semiconductor device structure of the present invention can be mounted thinly and inexpensively when thin semiconductor chips are stacked and mounted, and can easily be reduced in height, and thus can be applied to a package in which semiconductors are stacked and mounted. .

本発明の半導体実装方法の工程図Process drawing of semiconductor mounting method of the present invention 完成した半導体装置のＡ−Ａ拡大断面図AA enlarged sectional view of a completed semiconductor device 図２の平面図Plan view of FIG. 本発明の（実施の形態２）の半導体装置の平面図とＢ−Ｂ拡大断面図Plan view and BB enlarged sectional view of a semiconductor device according to (Embodiment 2) of the present invention 本発明の（実施の形態３）の半導体装置の平面図とＣ−Ｃ拡大断面図The top view and CC expanded sectional view of the semiconductor device of (Embodiment 3) of this invention 本発明の（実施の形態４）の半導体装置の平面図とＤ−Ｄ拡大断面図The top view and DD expanded sectional view of the semiconductor device of (Embodiment 4) of this invention 本発明の（実施の形態５）の半導体装置の平面図とＥ−Ｅ拡大断面図The top view and EE expanded sectional view of the semiconductor device of (Embodiment 5) of this invention 従来の半導体装置の平面図とその拡大断面図A plan view of a conventional semiconductor device and an enlarged sectional view thereof 別の従来例の拡大断面図Expanded sectional view of another conventional example

符号の説明Explanation of symbols

１ プリント配線基板
２ 導体パターン
３ａ，３ｂ 第１，第２の半導体チップ
４ａ，４ｂ 電極パッド
５ プリント配線基板１における半導体チップの実装位置に形成された孔
７ 切り欠き部
８ 括れ部
９ 導体パターンの孔 DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Conductor pattern 3a, 3b 1st, 2nd semiconductor chip 4a, 4b Electrode pad 5 Hole 7 formed in the mounting position of the semiconductor chip in the printed wiring board 1 Notch part 8 Narrow part 9 Conductor pattern Hole

Claims (4)

第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した半導体装置であって、
前記導体パターンにおける第１，第２の半導体チップの実装個所の幅を前記電極パットの幅よりも狭く形成して、両電極パット同士を接合させた
半導体装置。 A semiconductor device mounted with an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip sandwiching a conductor pattern protruding from the printed wiring board,
A semiconductor device in which the width of the mounting portion of the first and second semiconductor chips in the conductor pattern is narrower than the width of the electrode pad, and the electrode pads are joined together. 第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した半導体装置であって、
前記導体パターンにおける第１，第２の半導体チップの実装個所を前記電極パットの幅よりも狭くなる括れ部を形成して、前記括れ部において両電極パット同士が接合した
半導体装置。 A semiconductor device mounted with an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip sandwiching a conductor pattern protruding from the printed wiring board,
A semiconductor device in which a constriction portion that is narrower than a width of the electrode pad is formed at a mounting portion of the first and second semiconductor chips in the conductor pattern, and both electrode pads are joined to each other at the constriction portion. 第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装した半導体装置であって、
前記導体パターンにおける第１，第２の半導体チップの実装個所に孔を形成して、前記孔において両電極パット同士が接合した
半導体装置。 A semiconductor device mounted with an electrode pad formed on the back surface of the first semiconductor chip and an electrode pad formed on the back surface of the second semiconductor chip sandwiching a conductor pattern protruding from the printed wiring board,
A semiconductor device in which a hole is formed at a mounting position of the first and second semiconductor chips in the conductor pattern, and both electrode pads are joined in the hole. 第１の半導体チップの裏面に形成された電極パッドと第２の半導体チップの裏面に形成された電極パッドとで、プリント配線基板から突出した導体パターンを挟んで実装するに際し、
両電極パットの間に導体パターンを挟んだ状態で第１，第２の半導体チップを圧着して、両電極パットの間に挟まれる導体パターンで前記両電極パッドを変形させ、電極パッド同士を金属接合させる
半導体実装方法。 When mounting with the electrode pad formed on the back surface of the first semiconductor chip and the electrode pad formed on the back surface of the second semiconductor chip sandwiching the conductor pattern protruding from the printed wiring board,
The first and second semiconductor chips are pressure-bonded with the conductor pattern sandwiched between both electrode pads, the electrode pads are deformed by the conductor pattern sandwiched between the electrode pads, and the electrode pads are made of metal. Semiconductor mounting method to be joined.
JP2005255782A 2005-09-05 2005-09-05 Semiconductor mounting method Expired - Fee Related JP4744246B2 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61234538A (en) * 1985-04-11 1986-10-18 Seiko Epson Corp Ic mounting structure
JPS63136642A (en) * 1986-11-28 1988-06-08 Dainippon Printing Co Ltd 2-layer type semiconductor integrated circuit
JPH04105339A (en) * 1990-08-24 1992-04-07 Fujitsu Ltd Lead structure of tape carrier
JPH08111432A (en) * 1994-10-12 1996-04-30 Fujitsu Ltd Semiconductor device and production thereof
JP2000340605A (en) * 1999-05-31 2000-12-08 Mitsui Mining & Smelting Co Ltd Semiconductor device, manufacture thereof, card-like semiconductor device and manufacture thereof
JP2001267358A (en) * 2000-03-21 2001-09-28 Rohm Co Ltd Method for assembling semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61234538A (en) * 1985-04-11 1986-10-18 Seiko Epson Corp Ic mounting structure
JPS63136642A (en) * 1986-11-28 1988-06-08 Dainippon Printing Co Ltd 2-layer type semiconductor integrated circuit
JPH04105339A (en) * 1990-08-24 1992-04-07 Fujitsu Ltd Lead structure of tape carrier
JPH08111432A (en) * 1994-10-12 1996-04-30 Fujitsu Ltd Semiconductor device and production thereof
JP2000340605A (en) * 1999-05-31 2000-12-08 Mitsui Mining & Smelting Co Ltd Semiconductor device, manufacture thereof, card-like semiconductor device and manufacture thereof
JP2001267358A (en) * 2000-03-21 2001-09-28 Rohm Co Ltd Method for assembling semiconductor device

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