JP2007072451A - Exposure mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an exposure mask provided with a semi-transparent film, capable of forming a resist in which a projection portion is not formed in an end portion and the end portion has a gentle shape. <P>SOLUTION: The phase difference Δθ between exposure light 107 which transmits a transparent region and exposure light 106 which transmits a semi-transparent region, and transmittance n in the semitransparent region for exposure light are specified to satisfy formula (1). Thereby, a resist having regions with different resist film thicknesses and a gentle edge shape can be formed. By using the resist for processing such as etching, regions having different film thicknesses can be formed in a self-aligned matter. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an exposure mask. In particular, the present invention relates to optimum conditions for the phase difference and transmittance of the exposure mask.

  Note that a semiconductor device in this specification refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, active matrix liquid crystal and EL display technologies using thin film transistors (TFTs) have attracted attention. The active matrix display is advantageous in terms of response speed and contrast compared to the passive matrix display.

  Various TFTs with different roles depending on applications and functions are used in the semiconductor device having the above-mentioned display, and an LDD (Lightly Doped Drain) structure with a small off-current value, a gate electrode and an LDD region excellent in hot carrier countermeasures A GOLD (Gate Overlapped LDD) structure or a single drain structure having an overlapping region is used.

  Conventionally, the LDD region and the GOLD region are formed by self-alignment using a gate electrode as a mask, thereby suppressing an increase in the photolithography process.

  However, when the LDD structure and the GOLD structure are formed only by a process such as dry etching, the single drain structure, the LDD structure, and the GOLD structure cannot be formed separately for each circuit.

  In addition, the method for forming the LDD region includes a step of forming a spacer (also referred to as a side wall) on the side wall of the gate electrode, but a complicated step is required.

As a method for solving the above problem, the present applicant applies a photomask or reticle provided with an auxiliary pattern (halftone film) having a light intensity reducing function made of a translucent film to a photolithography process for forming a gate electrode, A transistor having an LDD structure, a GOLD structure, and a single drain structure is formed for each circuit (see Patent Document 1). Note that a photomask or reticle provided with a halftone film is called an exposure mask (halftone mask).
JP2002-151523

  When a resist for obtaining a desired gate electrode is manufactured using the above-described halftone mask, the resist shape depends on the phase difference and transmittance of the halftone mask with respect to the exposure light. Therefore, it is necessary to control the transmittance and phase difference of exposure light.

  For example, the resist shape for obtaining a gate electrode capable of forming an LDD region by self-alignment has a region having a certain film thickness at the center portion of the resist, and includes both end portions of the resist. In this case, it is necessary to have a region having a film thickness thinner than that of the central portion, and to have gentle slopes at both end portions.

  FIG. 12 shows a resist manufactured using a halftone mask formed under the conditions of i-line (365 nm) transmittance n = 0.2 (or T = 20%) and i-line phase difference (Δθ) = 130 degrees. Show shape. As shown by the arrows, both end portions of the resist are convex. When the conductive layer is etched using the resist shown in FIG. 12 to form the gate electrode, the conductive layer below the convex portion is locally thickened. As a result, in the doping process of the semiconductor layer after the formation of the gate electrode, the carrier concentration of the semiconductor layer provided under the locally thick conductive layer is locally changed.

  This is because the exposure light that passes through the transparent area of the halftone mask interferes with the exposure light that passes through the halftone film (translucent area), and the intensity of the exposure light that passes through the halftone film at the boundary portion decreases. It is considered that a convex portion has been formed at the resist end portion (mask boundary portion).

  An object of the present invention is to provide an optimum halftone mask condition for obtaining resists having different film thicknesses without forming convex portions at the ends.

The present invention is characterized in that the phase difference Δθ of light used for exposure through the transparent region and the semi-transparent region and the transmittance n with respect to the light used for exposure of the semi-transparent region satisfy the following formula (1). .

In the present invention, the phase difference Δθ of light used for exposure through the transparent region and the semi-transparent region and the transmittance n for light used for exposure of the semi-transparent region satisfy the following formula (2), and the transmission The rate n is 0.15 or more and 0.8 or less.

The present invention is an exposure mask having a translucent substrate, a translucent film disposed on the translucent substrate, and a light-shielding film disposed on the translucent film, and is used for exposure light. The phase difference Δθ between the translucent film and the translucent substrate and the transmittance n for light used for exposure of the translucent film satisfy the following formula (3).

  The present invention is an exposure mask having a translucent substrate, a translucent film disposed on the translucent substrate, and a light-shielding film disposed on the translucent film, and is used for exposure light. The phase difference between the translucent film and the translucent substrate is from −100 degrees to 100 degrees.

  The present invention is an exposure mask having a translucent substrate, a translucent film disposed on the translucent substrate, and a light-shielding film disposed on the translucent film, and is used for exposure light. The phase difference between the translucent film and the translucent substrate is −90 degrees or more and 90 degrees or less.

  The present invention is characterized in that a Cr film or a film made of a laminate of Cr is used as the light shielding film.

  The present invention is characterized in that an alloy containing Mo and Si, an alloy containing Cr and Si, or Cr is used as a material for the translucent film.

  The present invention is characterized in that a transmittance n with respect to light used for exposure of a translucent film is 0.15 or more and 0.8 or less.

  The present invention is characterized in that light used for exposure is i-line (wavelength 365 nm).

  The present invention can also be used for an original photomask for holographic exposure.

  Here, the halftone mask is a photomask having a light-shielding region and a region having a certain transmittance in a photolithography process, and a ratio of transmitting exposure light is almost 100% (n = 1). 0.0) an auxiliary pattern having a light intensity reducing function comprising a translucent film having a transmittance of 1% to 99% on a transparent substrate (hereinafter referred to as a halftone film or simply a semitransparent film or auxiliary pattern). And a mask having a structure in which a light shielding film is provided on the auxiliary pattern. Note that the halftone mask is not limited to the above structure as long as it has at least three regions of a transparent region, a semi-transparent region, and a light-shielding region.

  By performing exposure using the halftone mask of the present invention, the resist film thickness can be adjusted within the exposure surface. Accordingly, it is possible to form a resist having regions with different resist film thicknesses and having a gentle edge. By performing processing such as etching using this resist, regions having different film thicknesses can be formed in a self-aligning manner. As a result, transistors, capacitor elements, and resistor elements having different electrode structures and the like can be formed separately by the same patterning (processing) process. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
FIG. 1B shows a halftone mask including a light-transmitting substrate 100, a semitransparent film 101, and a light shielding film 104. FIG. 1A illustrates the exposure light 107 that passes through a transparent region (here, the region of the light-transmitting substrate 100 that does not overlap with the semi-transparent film 101) in the halftone mask illustrated in FIG. The phase difference Δθ of the exposure light 106 that passes through the semi-transparent region (here, the region where only the semi-transparent film 101 and the translucent substrate 100 overlap) and the transmittance n of the semi-transparent film 101 with respect to the exposure light are It is the graph showing the relationship between the intensity | strength of the exposure light 108 which permeate | transmits the boundary vicinity of a semi-transparent area | region and a transparent area | region when it is changed. In other words, exposure light that passes through the vicinity of the boundary can also be expressed as exposure light that passes through the end face or end of the semitransparent film 101. Each curve on the graph is represented by the following approximate expression (4) found by the present inventor.

  In addition, the said Formula (4) is normalized by making exposure intensity when not providing a semi-transparent film | membrane into 1. FIG.

  For example, when n = 0.2, when the phase difference of the exposure light transmitted through the transparent area and the semitransparent area of the halftone mask is 130 degrees, the exposure intensity in the vicinity of the boundary between the transparent area and the semitransparent area is 1 The value is smaller. As a result, the light transmittance in the boundary region between the transparent film and the semi-transparent film is lowered, so that convex portions are formed on the edge of the resist as shown in FIG.

  Next, when the phase difference is about 90 degrees or less, the exposure intensity is 1 or more at the transmittance n = 0.1 to 0.7. Accordingly, at this time, the exposure light transmitted through the transparent region of the halftone mask and the semitransparent film provided on the halftone mask interfere with each other and strengthen each other, so that the convex portion is not formed at the end portion and has a gentle edge. A resist can be formed. Note that, as the transmittance n approaches 1, the exposure intensity at a phase difference of 90 degrees increases. However, when the transmittance n is as close to 1 as possible, the resist corresponding to the translucent film disappears during development. Therefore, the transmittance n of the translucent film is preferably 0.8 or less.

  When the exposure light that passes through the transparent area of the halftone mask and the exposure light that passes through the translucent area interfere with each other, that is, when the value of f (Δθ) is 1 or more in equation (4) A resist in which no convex shape is formed on the portion can be formed. When f (Δθ) ≧ 1 is solved in the equation (4), the following equation (5) is obtained.

  Therefore, the phase difference Δθ and the transmittance n need only satisfy Expression (5). The transmittance n may be from 0.1 to 0.8 (preferably from 0.15 to 0.8, more preferably from 0.2 to 0.5). Further, the phase difference Δθ may be −100 degrees to 100 degrees (preferably −90 degrees to 90 degrees, more preferably 60 degrees to 90 degrees).

  FIG. 2 is a schematic diagram of a resist pattern formed using the halftone mask according to the present invention. In the exposure mask, a halftone film 201 made of molybdenum silicide (MoSi) is provided on a light-transmitting substrate 200, and a light shielding film 204 made of a metal film such as chromium (Cr) is provided so as to be laminated with the halftone film 201. . As the halftone film 201, i-line (wavelength 365 nm) having a transmittance (n) with respect to exposure light of 0.15 or more is used. The i-line transmitted through the translucent substrate 200 and the translucent substrate 200 are used. In addition, a film having a phase difference (Δθ) of i-line transmitted through the halftone film 201 of 90 degrees or less is used. In addition, the halftone film 201 uses a compound of Si and a metal that satisfies the phase difference and transmittance of the formula (5), for example, n ≧ 0.15 and Δθ ≦ 90 degrees. Can be formed. As the compound of Si and metal, for example, an alloy or compound of Si and Mo such as MoSi, MoSiO, and MoSiON is used. In addition, an alloy or compound of Cr and Si such as CrSi can be used. Further, Cr alone can be used. Exposure light from above the exposure mask is applied to the flat resist 203 formed on the substrate 202. Then, a resist pattern 205 is formed by a photoresist process.

  Since the light intensity at both ends of the halftone film is increased by the interference between the exposure light that passes through the transparent area and the exposure light that passes through the translucent area, at the end of the boundary between the transparent area and the translucent area, as shown in FIG. It is possible to obtain a resist pattern 205 that does not have a convex portion and has a gentle end. In other words, the first region 206 having a large film thickness formed at a position corresponding to the light shielding film 204 and the film thickness formed at a position corresponding to a translucent film not overlapping with the light shielding film are larger than those in the first region. In the thin second region 207 and the third region 208 on the substrate corresponding to the light-transmitting substrate 200 that does not overlap with the light-shielding film 204 and the halftone film 201, the second region 207 and the third region 208 are included. A resist pattern having no shape in which the second region 207 protrudes in the vicinity of the boundary can be formed. By using this resist pattern 205, gate electrodes having different shapes can be formed on the same substrate in a self-aligned manner, and the width of the LDD region can be controlled in accordance with each structure.

  Here, semi-transparent means that the transmissivity of the semi-transparent film is 1% or more and 99% or less, assuming that the ratio of exposure light passing through the transparent region is 100%. Note that the optimum transmittance of the translucent film is in the range of 15 to 80% (more preferably 20% to 50%) from the inventors' experience.

  Therefore, if the i-line phase difference transmitted through the transparent region and the translucent region in the halftone mask is 100 degrees or less (preferably 90 degrees or less), and the transmittance n is 0.15 or more and 0.8 or less. Good.

  As a method for accurately controlling the phase difference of the exposure light that passes through the transparent region and the semi-transparent region, the transparent substrate may be removed by a predetermined depth by processing such as etching.

  In FIG. 2, the light-shielding film 204 is not necessarily provided if a resist having a similar shape is formed by adjusting the thickness of the halftone film 201 and the interval between the halftone films.

  In this embodiment mode, the pattern configuration of the gate electrode forming photomask or reticle uses a positive resist. The positive type resist is a type of resist in which an exposure light irradiation region is solubilized in a developer. If applicable, a negative resist may be used. A negative resist is a resist of a type in which an irradiation area of exposure light is insoluble in a developer.

  Next, a process of forming a TFT gate electrode using the halftone mask of the present invention will be described with reference to FIGS.

  First, a first insulating film 302 serving as a base film is formed over a substrate 301 having an insulating surface. As the substrate 301 having an insulating surface, a light-transmitting substrate such as a glass substrate, a crystallized glass substrate, or a plastic substrate can be used. When a thin film transistor to be formed later is applied to a top emission type (upward emission type) light emitting display device or a reflection type liquid crystal display device, a ceramic substrate, a semiconductor substrate, a metal substrate, or the like can also be used. . As the semiconductor substrate, a silicon substrate such as an N-type or P-type single crystal silicon substrate or a high-purity silicon substrate can be used. For example, when the substrate is n-type, a p-well into which p-type impurities are implanted may be formed, and a MOS transistor using the upper layer of this well as a semiconductor layer may be used instead of the TFT.

As the first insulating film 302, a single layer or a stacked layer of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is used. Next, a semiconductor layer 303 is formed over the first insulating film 302.

  For the semiconductor layer 303, a semiconductor film having an amorphous structure is formed by a known means (such as a sputtering method, an LPCVD method, or a plasma CVD method), and a crystalline semiconductor film crystallized by heat treatment is formed. After forming a resist film on the conductive semiconductor film, it is processed into a desired shape using a first resist mask obtained by exposure and development.

The semiconductor layer 303 is formed with a thickness of 25 to 80 nm (preferably 30 to 70 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

The heat treatment may be a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof.

Alternatively, the crystalline semiconductor film may be formed by a thermal crystallization method in which the above heat treatment is performed after adding a catalyst such as nickel. Note that in the case where a crystalline semiconductor film is obtained by crystallization using a thermal crystallization method using a catalyst such as nickel, it is preferable to perform a gettering treatment for removing the catalyst such as nickel after crystallization.

In the case of manufacturing a crystalline semiconductor film by a laser crystallization method, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, a great improvement in output can be expected.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  When a semiconductor film is annealed using a linear beam having a uniform intensity obtained in this manner and an electronic device is manufactured using this semiconductor film, the characteristics of the electronic device are good and uniform.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the semiconductor layer in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

Next, after removing the first resist mask, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the semiconductor layer is washed. Then, a second insulating film 304 serving as a gate insulating film covering the semiconductor layer is formed. The second insulating film 304 is formed by plasma CVD, sputtering, or thermal oxidation, and has a thickness of 1 to 200 nm, preferably 70 to 120 nm. As the second insulating film 304, a film formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by plasma CVD.

  In addition, after forming an insulating layer, a semiconductor layer, a gate insulating layer, an interlayer insulating layer, and the like as a substrate and a base film, the substrate, the insulating layer as a base film, and a semiconductor are oxidized or nitrided using plasma treatment. The surface of the layer, gate insulating layer, or interlayer insulating layer may be oxidized or nitrided. When a semiconductor layer or an insulating layer is oxidized or nitrided using plasma treatment, the surface of the semiconductor layer or the insulating layer is modified, so that the insulating film becomes denser than an insulating film formed by a CVD method or a sputtering method. be able to. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved. The plasma treatment as described above can also be performed on the gate electrode layer, the source electrode layer, the drain electrode layer, the wiring layer, and the like, and a nitride film or an oxide film can be formed by performing nitridation or oxidation.

Note that in the case of oxidizing a film by plasma treatment, an oxygen atmosphere (for example, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen and hydrogen are used. (H ₂ ) and a rare gas atmosphere or dinitrogen monoxide and a rare gas atmosphere). On the other hand, in the case of nitriding a film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or nitrogen and hydrogen And a rare gas atmosphere or NH ₃ and a rare gas atmosphere). As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating film formed by the plasma treatment contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing, and when Ar is used, the insulating film Contains Ar.

Also, if the second insulating film 304 is subjected to plasma treatment, a plasma treatment is performed in the atmosphere containing the aforementioned gas, an electron density of 1 × ¹⁰ 11 ^{cm -3} or more, the electron temperature of plasma is less 1.5eV . More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the electron temperature of plasma is 0.5 eV to 1.5 eV. Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the second insulating film 304 functioning as a gate insulating layer) formed on the substrate is low, Damage can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower by 100 degrees or more than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

  Next, a stack of a first conductive layer 305a and a second conductive layer 306a is formed. Further, the stacking is not limited to two layers of the first conductive layer and the second conductive layer, and may be three or more layers.

  The first conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. It is formed with a thickness of ˜50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm.

  Here, two layers, that is, the first conductive layer and the second conductive layer are used as different conductive materials so that a difference in etching rate is generated in an etching process performed later. TaN is used as the first conductive layer, and a tungsten film is used as the second conductive layer.

Next, after a resist film is applied over the entire surface of the second conductive layer 306a, exposure is performed using a mask illustrated in FIG. Here, a resist film having a thickness of 1.5 μm is applied, and exposure is performed using an exposure machine having a resolution of 1.5 μm. The light used for exposure is i-line (wavelength 365 nm), and the exposure energy is selected from the range of 20 to 140 mJ / cm ² . The light is not limited to i-line, and light obtained by mixing i-line, g-line (wavelength 436 nm) and h-line (wavelength 405 nm) may be used for exposure.

  In FIG. 3A, the exposure mask has a light shielding portion 401 made of a metal film such as Cr and a portion provided with a semitransparent film 402 as an auxiliary pattern having a light intensity reducing function (semitransparent portion, halftone film). Also called). The translucent film 402 has an i-line transmittance (n) of 0.2, exposure light that passes through the light-transmitting substrate 400, and exposure light that passes through the light-transmitting substrate 400 and the translucent film 402. A semitransparent film is used in which the film thickness, material, composition, etc. are controlled so that the phase difference with respect to 90 degrees is 90 degrees. In the cross-sectional view of the exposure mask, the width of the light shielding portion 401 is indicated by t2, and the width of the portion provided with the semitransparent film 402 is indicated by t1.

  When the resist film is exposed using the exposure mask shown in FIG. 3A, a non-exposed region 403a and an exposed region 403b are formed. At the time of exposure, light passes around the light shielding portion 401 or passes through a portion where the semitransparent film 402 is provided, so that a non-exposed region 403a shown in FIG.

  When development is performed, the exposed region 403b is removed, and as shown in FIG. 3B, a resist pattern 307a having a thick film region and a thin film region is formed in the second conductive layer. Obtained on 306a. In the resist pattern 307a, the thin film thickness region can be adjusted by adjusting the exposure energy.

Next, the second conductive layer 306a and the first conductive layer 305a are etched by dry etching. As the etching gas, CF ₄ , SF ₆ , Cl ₂ , and O ₂ are used. For improving the etching rate, a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) is used. Note that depending on the etching conditions, the second insulating film 304 is also etched, and the film thickness is partially reduced.

  Although an example using an ICP etching apparatus is shown here, the invention is not particularly limited. For example, a parallel plate etching apparatus, a magnetron etching apparatus, an ECR etching apparatus, or a helicon etching apparatus may be used. Further, the method is not limited to the dry etching method, and a wet etching method may be used, or a combination of the dry etching method and the wet etching method may be used.

Thus, as shown in FIG. 3C, a conductive laminated pattern including the first conductive layer 305b and the second conductive layer 306b is formed over the second insulating film 304. By etching, both side walls of the first conductive layer 305b are exposed, and further, a region that does not overlap with the second conductive layer 306b is exposed. Note that both side walls of the first conductive layer 305b may be tapered. Further, both side walls of the second conductive layer 306b may be tapered.

  Next, after removing the resist pattern 307 b, one conductivity type impurity is added to the semiconductor layer 303. Here, phosphorus (or As) is used as an ion of one conductivity type impurity, and an n-channel TFT is manufactured. An LDD region (GOLD region), a source region, and a drain region can be formed in a self-aligning manner using a conductive laminated pattern without forming a sidewall.

In the case of performing a doping process for forming a source region and a drain region located outside the gate electrode, ions of one conductivity type impurity are added to the semiconductor layer 303 by using the conductive stacked pattern as a mask, and the one conductivity type impurity having a high concentration is added. The regions 310 and 311 may be formed. Doping conditions for forming the source region and the drain region are performed with an acceleration voltage of 50 kV or less. The impurity concentration of the high-concentration one-conductivity type impurity regions 310 and 311 is 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ (peak value in SIMS measurement).

In addition, in the case of performing a doping process for forming an LDD region (GOLD region) overlapping with the gate electrode, the first conductive layer 305b in a region not stacked with the second conductive layer is passed through, so that one conductivity type impurity These ions may be added to the semiconductor layer 303 to form the low-concentration one-conductivity type impurity regions 309a and 309b. This doping condition depends on the thickness of the second conductive layer or the first conductive layer, but in this case, an acceleration voltage of 50 kV or more is required. The impurity concentration of the low-concentration one-conductivity type impurity regions 309a and 309b is 1 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ (peak value in SIMS measurement) assuming the LDD region.

  Note that the order of doping is not particularly limited, and a doping process for forming an LDD region (GOLD region) may be performed after performing a doping process for forming a source region and a drain region first. Further, after performing a doping process for forming an LDD region (GOLD region), a doping process for forming a source region and a drain region may be performed.

Although an example in which the doping process is divided into two times to form impurity regions having different concentrations has been described here, the impurity regions having different concentrations can be formed by one doping process by adjusting the processing conditions. Good.

  Moreover, although the example which removed the resist pattern before doping was shown, you may remove a resist pattern after performing a doping process. When doping is performed with the resist pattern remaining, doping can be performed while protecting the surface of the second conductive layer with the resist pattern.

  Note that in the doping process, the semiconductor layer in a position overlapping with the second conductive layer is a region to which ions of one conductivity type impurity are not added, and functions as a channel formation region of a TFT to be formed later.

  In addition, the conductive stacked pattern (the first conductive layer 305b and the second conductive layer 306b) serves as a gate electrode at a portion where the semiconductor layer 303 intersects. In addition, a region of the first conductive layer 305b that does not overlap with the second conductive layer 306b is a Lov region. Note that the Lov region refers to a low concentration impurity region (LDD region) overlapping with the gate electrode. The length of the required Lov region may be determined in accordance with the type and application of the circuit having the TFT, and the exposure mask and etching conditions may be set based on the length. “Ov” means “overlap”.

  After that, a third insulating film 312 using silicon nitride oxide is formed. Then, the impurity element added to the semiconductor layer is activated and hydrogenated.

  Next, a light-transmitting inorganic material (silicon oxide, silicon nitride, silicon oxynitride, etc.) or a low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material (eg, polyimide or polybenzoxazole)) ) Is used to form the fourth insulating film 313. Alternatively, the fourth insulating film may be formed using a material containing siloxane. Siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, a resist mask is formed using a third photomask, and a third insulating film 312 that functions as an interlayer insulating film, a fourth insulating film 313, and a second insulating film 304 that functions as a gate insulating film are formed. A contact hole is formed by selective etching. Then, the resist mask is removed.

  Next, after a metal stacked film is formed over the fourth insulating film 313 by a sputtering method, a resist mask is formed using a fourth photomask, the metal stacked film is selectively etched, and a semiconductor layer is formed. A source electrode 314 or a drain electrode 315 in contact with the electrode is formed.

  A connection electrode (an electrode for electrically connecting a plurality of TFTs) and a terminal electrode (an electrode for connecting to an external power source) are also formed on the fourth insulating film 313 simultaneously with the source electrode 314 or the drain electrode 315 of the TFT. can do. Then, the resist mask is removed. Note that the metal stacked film is a three-layer stack including a Ti film with a thickness of 100 nm, an Al film containing a small amount of Si with a thickness of 350 nm, and a Ti film with a thickness of 100 nm. The metal laminated film is preferably formed continuously in the same metal sputtering apparatus.

  Through the above steps, a top-gate TFT having low-concentration one-conductivity type impurity regions (low-concentration impurity regions) 309a and 309b on both sides of the channel formation region shown in FIG. 3D is completed. FIG. 3D shows the channel length L.

  As described above, in this embodiment, the resist pattern 307a having a gentle shape at the end portion is formed by performing exposure using a photomask in which the transmittance and the phase difference with respect to the exposure light of the halftone film are controlled. The gate electrode is obtained using the resist pattern. By adjusting the length of the thin portion of the resist pattern 307a, the length of the Lov region can be adjusted in a self-aligning manner.

Note that in this embodiment mode, an n-channel TFT is described; however, a p-channel TFT can be formed by using a p-type impurity element instead of an n-type impurity element.

  Further, an n-channel TFT and a p-channel TFT can be formed on the same substrate, and a CMOS circuit can be configured by combining these TFTs in a complementary manner. A CMOS circuit is a circuit having at least one n-channel TFT and one p-channel TFT (inverter circuit, NAND circuit, AND circuit, NOR circuit, OR circuit, shift register circuit, sampling circuit, D / A converter) Circuit, A / D converter circuit, latch circuit, buffer circuit, etc.). In addition, by combining these CMOS circuits, memory elements such as SRAM and DRAM and other elements can be formed on the substrate. It is also possible to configure a CPU on a substrate by integrating various elements and circuits.

  Although this embodiment mode is described using a single-gate top-gate TFT, a top-gate TFT having a multi-gate structure having a plurality of channel formation regions can also be formed. In addition, a single-gate top gate TFT and a multi-gate top gate TFT can be formed on the same substrate without changing the number of steps simply by changing the exposure mask. Note that the single gate structure is a structure in which one TFT has one gate electrode. The multi-gate structure is a structure having a plurality of gates, and refers to a structure in which two or more TFTs are connected in series and the gate electrodes of the TFTs are connected.

Therefore, by simply changing the exposure mask, various circuits can be configured by assigning transistors having an optimal structure on the same substrate without increasing the number of steps.

  In this embodiment mode, the present invention is applied to the step of forming the gate electrode. However, the present invention is not limited to the gate electrode, but can be applied to other electrodes and wirings.

(Embodiment 2)
In this embodiment, using an exposure mask that satisfies the conditions of the present invention, without increasing the number of steps, a top gate TFT having a structure in which the drain side has a wider Lov region than the source side on the same substrate; FIG. 4 shows an example of forming a top gate TFT having a structure having a Lov region having the same width on both sides of a channel formation region.

  In FIG. 4A, a semiconductor layer 502 and a semiconductor layer 503 are formed over a substrate 500 and an insulating layer 508. A gate insulating layer 504, a first conductive film 505, and a second conductive film 506 are formed so as to cover the semiconductor layer 502 and the semiconductor layer 503, and have a shape manufactured as shown in FIG. Different resist patterns 529, resist patterns 539, and resist patterns 549 are formed. As shown in the first embodiment, these resist patterns include an exposure light that transmits through the halftone film and the light-transmitting substrate, and a light-transmitting substrate, among the exposure masks that include the halftone film and the light-transmitting substrate. Is formed using an exposure mask in which the phase difference of the exposure light passing through and the transmittance of the halftone film satisfy Expression (5). Therefore, a convex part is not formed in the edge part of each resist pattern, but an edge part becomes a gentle shape.

  The resist pattern 529 has a shape having gentle steps on both sides (symmetrical shape in the cross section of FIG. 4A), and the resist pattern 539 has a shape in which the convex portion is shifted from the center (FIG. 4A). The resist pattern 549 has a shape with no step and unevenness (a shape that is symmetrical in the cross section of FIG. 4A).

  Patterning is performed by etching using the resist pattern 529, the resist pattern 539, and the resist pattern 549, and the first gate electrode layer 521, the second gate electrode layer 522, the first gate electrode layer 531, and the second gate are formed. An electrode layer 532, a first wiring layer 541, and a second wiring layer 542 are formed.

  Using the second gate electrode layer 522 and the second gate electrode layer 532 as masks, an impurity element having one conductivity type is added to the semiconductor layer 502 and the semiconductor layer 503, so that the low concentration impurity region 524a and the low concentration impurity region are added. A low concentration impurity region 534a and a low concentration impurity region 534b are formed (see FIG. 4B).

  Further, the semiconductor layer 502 and the semiconductor layer 503 have one conductivity type using the first gate electrode layer 521, the second gate electrode layer 522, the first gate electrode layer 531 and the second gate electrode layer 532 as a mask. An impurity element is added to form a high concentration impurity region 525a, a high concentration impurity region 525b, a high concentration impurity region 535a, and a high concentration impurity region 535b.

  Next, the resist pattern 523, the resist pattern 533, and the resist pattern 543 are removed.

  Thus, the first TFT portion 530, the second TFT portion 520, and the wiring portion 540 can be formed on the same substrate. In the first TFT portion 530, a TFT having a low concentration impurity region 536a on the source side and a low concentration impurity region 536b on the drain side is formed. Note that the low concentration impurity region 536b is wider than the low concentration impurity region 536a. In the second TFT portion 520, a TFT having low-concentration impurity regions 526a and 526b on both sides of the channel formation region is manufactured (see FIG. 4C). Further, in the wiring portion 540, a stack in which the positions of the end faces coincide, that is, a stack of the first wiring layer 541 and the second wiring layer 542 is obtained.

  In addition, by using the same resist pattern, the same structure as the first TFT portion 530 can be formed, and the capacitor and the TFT can be formed on the same substrate. In that case, a capacitor using the gate insulating layer 504 as a dielectric can be formed.

(Embodiment 3)
In this embodiment mode, a structure of an active matrix light-emitting device will be described below together with a manufacturing method with reference to FIGS.

First, a base insulating film 611 is formed over a substrate 610 having an insulating surface. In the case where light emission is extracted using the substrate 610 side as a display surface, a light-transmitting glass substrate or quartz substrate may be used as the substrate 610. Alternatively, a light-transmitting plastic substrate having heat resistance that can withstand the processing temperature may be used. In the case where light emission is extracted using a surface opposite to the substrate 610 side as a display surface, a substrate in which an insulating film is formed on the surface of a silicon substrate, a metal substrate, or a stainless steel substrate in addition to the above substrate may be used. Here, a glass substrate is used as the substrate 610. The refractive index of the glass substrate is around 1.55.

  As the base insulating film 611, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example in which a single layer structure is used as the base film is shown, but a structure in which two or more insulating films are stacked may be used. Note that the base insulating film is not necessarily formed if unevenness of the substrate or impurity diffusion from the substrate is not a problem.

  Next, a semiconductor layer is formed over the base insulating film 611. The semiconductor layer is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then known crystallization treatment (laser crystallization method, thermal crystallization method). Or a crystalline semiconductor film obtained by performing a thermal crystallization method using a catalyst such as nickel) is processed (patterned) into a desired shape using a first photomask to form a semiconductor layer. . Note that when the plasma CVD method is used, the base insulating film 611 and the semiconductor film having an amorphous structure can be stacked successively without being exposed to the air. The semiconductor film is formed with a thickness of 25 to 80 nm (preferably 30 to 70 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  Here, as a technique for crystallizing a semiconductor film having an amorphous structure, the technique described in JP-A-8-78329 is used for crystallization. The technology described in this publication is based on a crystal structure in which an amorphous silicon film (also referred to as an amorphous silicon film) is selectively added with a metal element that promotes crystallization, and heat treatment is performed to expand the added region as a starting point. The semiconductor film which has this is formed.

  Hereinafter, an example of a method for forming a crystalline semiconductor film will be described in detail.

  First, a nickel acetate solution containing a catalytic metal element (here, nickel) that promotes crystallization on a surface of an amorphous semiconductor film containing 1 to 100 ppm by weight is applied by a spinner. A containing layer is formed. As a means other than the method for forming the nickel-containing layer by coating, a means for forming an extremely thin film by sputtering, vapor deposition, or plasma treatment may be used. Although an example in which the coating is performed on the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Next, heat treatment is performed to perform crystallization. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Thus, a semiconductor film having a crystal structure is formed. Note that the concentration of oxygen contained in the semiconductor film after crystallization is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C. to 650 ° C. for 4 to 24 hours) is performed. When crystallization is performed by irradiation with strong light, any one of infrared light, visible light, and ultraviolet light, or a combination thereof can be used. Note that if necessary, heat treatment for releasing hydrogen contained in the semiconductor film having an amorphous structure may be performed before irradiation with strong light. In addition, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. In consideration of productivity, it is desirable to perform crystallization by irradiation with strong light.

In the crystalline semiconductor film thus obtained, a metal element (here, nickel) remains. Although it is not uniformly distributed in the film, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ in terms of an average concentration. Of course, various semiconductor elements including TFT can be formed even in such a state, but the element is removed by a gettering method described below.

  Here, the natural oxide film formed in the crystallization step is removed before the laser light irradiation. Since this natural oxide film contains nickel in high concentration, it is preferably removed.

Next, the crystalline semiconductor film is irradiated with laser light in order to increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains. When laser light is irradiated, distortion and ridges are formed in the semiconductor film, and a thin surface oxide film (not shown) is formed on the surface. As this laser light, an excimer laser light having a wavelength of 400 nm or less emitted from a pulsed laser light source, or a second harmonic or a third harmonic of a YAG laser may be used. In addition, a solid-state laser capable of continuous oscillation may be used as the laser light, and the second to fourth harmonics of the fundamental wave may be used. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied.

  Next, first heat treatment (heat treatment in which the semiconductor film is instantaneously heated to about 400 to 1000 ° C.) for reducing distortion of the crystalline semiconductor film is performed in a nitrogen atmosphere to obtain a flat semiconductor film. As the heat treatment for instantaneously heating, heating may be performed by heat treatment for irradiating strong light, or heat treatment for putting a substrate into a heated gas and leaving it for several minutes, and then removing the substrate. Further, depending on the conditions of this heat treatment, it is possible to reduce the distortion and repair defects left in the crystal grains, that is, improve the crystallinity. This heat treatment also reduces the strain and makes it easier for the nickel to be gettered in a later gettering step. When the temperature in this heat treatment is lower than the temperature in crystallization, nickel moves into the film while the silicon film remains in a solid state.

  Next, a semiconductor film containing a rare gas element is formed above the crystalline semiconductor film. An oxide film (referred to as a barrier layer) serving as an etching stopper may be formed with a thickness of 1 to 10 nm before forming the semiconductor film containing a rare gas element. The barrier layer may be formed at the same time by heat treatment for reducing distortion of the semiconductor film.

  The semiconductor film containing a rare gas element is formed by a plasma CVD method or a sputtering method to form a gettering site with a thickness of 10 nm to 300 nm. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Among them, argon (Ar) which is an inexpensive gas is preferable.

Here, the PCVD method is used, monosilane and argon are used as source gases, and the ratio (monosilane: argon) is controlled to 0.1: 99.9 to 1: 9, preferably 1:99 to 5:95. Film. In addition, the RF power density during film formation is desirably 0.0017 W / cm ^{2 to} 0.48 W / cm ² . A high RF power density is preferable because a film quality that can provide a gettering effect can be obtained, and in addition, the film forming speed is improved. The pressure during film formation is preferably 1.333 Pa (0.01 Torr) to 133.322 Pa (1 Torr). The higher the pressure, the higher the deposition rate. However, the higher the pressure, the lower the concentration of Ar contained in the film. Further, it is desirable that the film forming temperature be 300 ° C. to 500 ° C. Thus, plasma CVD is performed on a semiconductor film containing argon at a concentration of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ^{3 in} the film. The film can be formed by the method. By adjusting the film formation conditions of the second semiconductor film within the above range, damage to the barrier layer during film formation can be reduced, and variations in the film thickness of the semiconductor film and holes in the semiconductor film can be generated. It is possible to prevent the occurrence of defects such as forming.

There are two meanings of including a rare gas element ion which is an inert gas in the film. One is to form a dangling bond to give distortion to the semiconductor film, and the other is to give distortion to the lattice of the semiconductor film. Distortion between the lattices of the semiconductor film is remarkably obtained when an element having a larger atomic radius than silicon, such as argon (Ar), krypton (Kr), or xenon (Xe), is used. Further, by containing a rare gas element in the film, not only lattice distortion but also dangling bonds are formed, contributing to the gettering action.

  Next, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the crystalline semiconductor film. As the heat treatment for performing gettering, heat treatment may be performed by irradiating with strong light, heat treatment using a furnace, or by putting the substrate into a heated gas, leaving it for a few minutes, and taking it out. Here, second heat treatment for performing gettering (heat treatment in which the semiconductor film is instantaneously heated to about 400 to 1000 ° C.) is performed in a nitrogen atmosphere.

  By this second heat treatment, the metal element moves to the semiconductor film containing the rare gas element, and the metal element contained in the crystalline semiconductor film covered with the barrier layer is removed or the concentration of the metal element is reduced. The metal element contained in the crystalline semiconductor film moves in a direction perpendicular to the substrate surface and toward the semiconductor film containing a rare gas element.

The distance that the metal element moves during gettering may be about the thickness of the crystalline semiconductor film, and the gettering can be completed in a relatively short time. Here, nickel is transferred to a semiconductor film containing a rare gas element so as not to segregate in the crystalline semiconductor film, and the nickel contained in the crystalline semiconductor film is almost absent, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm. Gettering is sufficiently performed so that it is ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less. Note that not only a semiconductor film containing a rare gas element but also a barrier layer functions as a gettering site.

Next, only the semiconductor film containing a rare gas element is selectively removed using the barrier layer as an etching stopper. As a method of selectively etching only a semiconductor film containing a rare gas element, dry etching without using plasma with ClF ₃ , hydrazine, tetramethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NOH) (abbreviation TMAH) It can be performed by wet etching with an alkaline solution such as an aqueous solution containing. Note that in order to prevent pinholes from being formed in the crystalline semiconductor film by this etching, the overetching time is reduced.

  Next, the barrier layer is removed with an etchant containing hydrofluoric acid.

Further, before the semiconductor film containing a rare gas element is formed, a flushing process may be performed using a flash substance in order to remove impurities such as F in the chamber. A process of flushing the substrate surface (also called silane flash) is performed by using monosilane as a flash substance and continuously introducing a gas flow rate of 8 to 10 SLM into the chamber for 5 to 20 minutes, preferably 10 to 15 minutes. Note that 1 SLM is 1000 sccm, that is, 0.06 m ³ / h.

  Through the above steps, a good crystalline semiconductor film can be obtained.

After processing the crystalline semiconductor film into a desired shape using the first photomask, the resist mask is removed. Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the semiconductor layer in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film on the surface of the semiconductor layer is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the semiconductor layer is washed.

  Then, an insulating film covering the semiconductor layer is formed. The insulating film is formed by plasma CVD or sputtering and has a thickness of 1 to 200 nm. It is preferably formed as a single layer or a laminated structure of an insulating film containing silicon by thinning to 10 nm to 50 nm, and then surface nitriding treatment using plasma by microwave is performed. The insulating film functions as a gate insulating film of a TFT formed later.

  Next, a first conductive film with a thickness of 20 to 100 nm and a second conductive film with a thickness of 100 to 400 nm are stacked over the insulating film. In this embodiment mode, a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 370 nm are sequentially stacked over the insulating film 613, and the processing (patterning) described in Embodiment Mode 1 is performed to form each gate electrode and each wiring. Form.

  Here, the conductive film is a laminate of a TaN film and a W film, but is not particularly limited, and an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy containing the above element as a main component You may form by lamination | stacking of material or a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked. Also good.

  An ICP (Inductively Coupled Plasma) etching method may be used for etching the first conductive film and the second conductive film (first etching process and second etching process). Using the ICP etching method, the film is formed into a desired shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.). It can be etched.

Next, in order to add an impurity element imparting n-type conductivity to the semiconductor layer, a first doping step is performed in which the entire surface is doped using the gate electrode as a mask. The first doping step may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 kV. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity.

  Next, after forming a mask made of a resist, a second doping step is performed for doping the semiconductor with an impurity element imparting n-type at a higher concentration than in the first doping step. The mask includes a source region and a drain region of a semiconductor layer forming a p-channel TFT in the pixel portion, and a peripheral region thereof, a part of the n-channel TFT in the pixel portion, and a p-channel TFT in the driver circuit portion. Are provided to protect the source region, the drain region, and the region around them.

The conditions of the ion doping method in the second doping step are a dose amount of 5 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 50 to 100 kV. Note that the acceleration voltage in the second doping step is lower than that in the first doping step.

  Next, after removing the mask, a new mask made of resist is formed, and a third doping step for doping the semiconductor with p-type impurity element (typically boron) at a high concentration is performed. The mask includes a source region and a drain region of a semiconductor layer in which an n-channel TFT in the pixel portion is formed, and a peripheral region thereof, and a source region and a drain region in a semiconductor layer in which the n-channel TFT in the driver circuit portion is formed, And their surrounding areas are provided for protection.

  Thereafter, the resist mask is removed. Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer.

  Next, after an insulating film containing hydrogen is formed by an LPCVD method, a plasma CVD method, or the like, the impurity element added to the semiconductor layer is activated and hydrogenated. As the insulating film containing hydrogen, a silicon nitride oxide film (SiNO film) obtained by a PCVD method is used. Here, the thickness of the insulating film containing hydrogen is 50 nm to 200 nm. Note that the insulating film containing hydrogen is the first layer of the interlayer insulating film and contains silicon oxide.

  Next, an inorganic insulating film serving as a second layer of the interlayer insulating film is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. As the inorganic insulating film, a single layer or a stacked layer of insulating films such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Here, the thickness of the inorganic insulating film is 600 nm to 800 nm.

Next, a resist mask is formed using a photomask, and the insulating film is selectively etched to form contact holes. Then, the resist mask is removed.

  Next, after a metal film is stacked by sputtering, a mask made of a resist is formed using a photomask, and the metal stacked film is selectively etched to form an electrode that functions as a source electrode or a drain electrode of the TFT. . The metal laminated film is continuously formed in the same metal sputtering apparatus. Then, the resist mask is removed.

Through the above steps, top-gate TFTs 636, 637, 638, and 639 using a polysilicon film as an active layer can be manufactured over the same substrate.

Note that the TFT 638 arranged in the pixel portion is an n-channel TFT having a plurality of channel formation regions in one TFT. The TFT 638 is a double gate type TFT. In the pixel portion, a TFT 639 that is electrically connected to a light-emitting element to be formed later is provided. Here, a double gate p-channel TFT is shown as the TFT 639 in order to reduce off-state current; however, there is no particular limitation, and a single gate TFT may be used. Note that the double gate type is a structure having two gates, and refers to a structure in which two TFTs are connected in series and the gate electrodes of the TFTs are connected. Compared with a single gate structure, the number of off electrodes can be reduced.

  The TFT 636 arranged in the driver circuit portion is an n-channel TFT including two low-concentration impurity regions (also referred to as Lov regions) having different widths on both sides of the channel formation region. The two low concentration impurity regions overlap with the gate electrode in a self-aligning manner. The TFT 637 is a p-channel TFT having a low-concentration impurity region (Lov region) having the same width on both the source side and the drain side. Both are single-gate TFTs. In the driver circuit portion, a CMOS circuit can be configured by complementarily connecting the TFT 636 and the TFT 637, and various types of circuits can be realized. If necessary, a multi-gate TFT can be formed.

Next, the first electrode 623, that is, the anode (or cathode) of the light-emitting element is formed. As the first electrode 623, a material having a high work function, for example, an element selected from Ni, W, Cr, Pt, Zn, Sn, In, or Mo, or an alloy material containing the element as a main component, for example, TiN, A single layer film or a laminated film thereof may be used in a total film thickness range of 100 nm to 800 nm using TiSi _X N _Y , WSi _X , WN _X , WSi _X N _Y , and NbN.

Specifically, a transparent conductive film formed using a light-transmitting conductive material may be used as the first electrode 623, and includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, and titanium oxide. Indium oxide, indium tin oxide containing titanium oxide, or the like can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

  In addition, compositional proportions of each light-transmitting conductive material will be described. The composition ratio of indium oxide containing tungsten oxide may be 1.0 wt% tungsten oxide and 99.0 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1.0 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The indium oxide containing titanium oxide may be 1.0 wt% to 5.0 wt% titanium oxide and 99.0 wt% to 95.0 wt% indium oxide. The composition ratio of indium tin oxide (ITO) may be 10.0 wt% tin oxide and 90.0 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10.7 wt% zinc oxide and 89.3 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5.0 wt% titanium oxide, 10.0 wt% tin oxide, and 85.0 wt% indium oxide. The above composition ratio is an example, and the ratio of the composition ratio may be set as appropriate.

Next, an insulator 629 (referred to as a bank, a partition, a barrier, a bank, or the like) is formed to cover an end portion of the first electrode 623 by a processing method such as etching on an insulating film (eg, an organic resin film) obtained by a coating method. To do. Note that the formation of the insulator 629 is not limited to processing using a mask, and the insulating material 629 may be formed only by exposure and development using a photosensitive material.

  Next, a light-emitting layer (EL layer) 624 is formed using an evaporation method or a coating method.

The light-emitting layer 624 is a stacked layer, and a buffer layer may be used as one layer of the light-emitting layer 624. The buffer layer is a composite material including an organic compound and an inorganic compound, and the inorganic compound exhibits an electron accepting property with respect to the organic compound. In the buffer layer, the inorganic compound is any one selected from the group consisting of titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide. One or more. The buffer layer is a composite material including an organic compound having a hole transporting property and an inorganic compound.

For example, a stack including a light-emitting layer (a stack of a buffer layer and a light-emitting layer) is preferably provided between the first electrode 623 and the second electrode. The buffer layer includes a metal oxide (molybdenum oxide, tungsten oxide, rhenium oxide, etc.) and an organic compound (a material having a hole transporting property (for example, 4,4′-bis [N- (3-methylphenyl) -N-phenylamino). ] Biphenyl (abbreviation: TPD), 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD), 4,4′-bis {N- [4- ( N, N-di-m-tolylamino) phenyl] -N-phenylamino} biphenyl (abbreviation: DNTPD) and the like)). The light-emitting layer provided over the buffer layer includes, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), α -NPD etc. can be used. The EL layer may contain a dopant material. For example, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, rubrene, or the like can be used. The stack including the light-emitting layer provided between the first electrode and the second electrode may be formed by an evaporation method such as a resistance heating method.

By adjusting the thickness of the buffer layer, the distance between the first electrode and the light emitting layer can be controlled to increase the light emission efficiency. By adjusting the thickness of the buffer layer, it is possible to display an excellent image in which the emission color from each light emitting element is clearly displayed, and to realize a light emitting device with low power consumption.

  Next, a second electrode 625, that is, a cathode (or an anode) of the light-emitting element is formed. As the second electrode 625, an alloy such as MgAg, MgIn, or AlLi, or a transparent conductive film (such as ITO) is used.

  Next, the protective layer 626 is formed by an evaporation method or a sputtering method. The protective layer 626 protects the second electrode 625. In the case where light emitted from the light-emitting element is extracted through the protective layer 626, a transparent material is preferably used. Note that a third electrode for protecting the second electrode may be formed between the protective layer 626 and the second electrode 625. Note that the protective layer 626 is not necessarily provided if not necessary.

  Next, the sealing substrate 633 is attached with a sealant 628 to seal the light-emitting element. That is, the light emitting display device is sealed with a pair of substrates by surrounding the outer periphery of the display region with a sealant. Since the interlayer insulating film of the TFT is provided on the entire surface of the substrate, when the sealing material pattern is drawn on the inner side of the outer peripheral edge of the interlayer insulating film, one of the interlayer insulating films located outside the sealing material pattern. There is a risk of moisture and impurities entering from the part. Therefore, the outer periphery of the insulating film used as the interlayer insulating film of the TFT is overlapped with the inside of the sealing material pattern, preferably the sealing material pattern so as to cover the end portion of the insulating film. Note that a region surrounded by the sealant 628 is filled with a filler 627. Alternatively, the region surrounded by the sealant 628 is filled with a dry inert gas.

  Finally, an FPC (Flexible Print Circuit) 632 is attached to the terminal electrode by an anisotropic conductive film 631 by a known method. A cross-sectional view at this stage is shown in FIG. Note that the transparent conductive film obtained in the same step as the first electrode 623 is preferably used for the terminal electrode, and the terminal electrode is formed over the terminal electrode formed at the same time as the gate wiring.

  6 shows a top view of the pixel portion, and the cross section taken along the chain line EF in FIG. 6 corresponds to the cross-sectional structure of the p-channel TFT 639 in the pixel portion in FIG. 6 corresponds to the sectional structure of the n-channel TFT 638 in the pixel portion in FIG. Note that the solid line indicated by 680 in FIG. 6 indicates the periphery of the insulator 629. However, in FIG. 6, only the first electrode 623 is illustrated, and the organic compound layer, the second electrode, and the like formed thereon are not illustrated.

  Through the above steps, the pixel portion, the driver circuit, and the terminal portion can be formed over the same substrate.

  In this embodiment mode, in order to reduce off-state current, a TFT in a pixel portion has a double gate structure, and a TFT having different widths of LDD regions on both sides of a channel formation region is used as an n-channel TFT of a driver circuit.

  In the light emitting device, the light emitting display surface of the light emitting device may be one surface or both surfaces. In the case where the first electrode 623 and the second electrode 625 are formed using a transparent conductive film, light from the light-emitting element passes through the substrate 610 and the sealing substrate 633 and is extracted to both sides. In this case, it is preferable to use a transparent material for the sealing substrate 633 and the filler 627.

  In the case where the second electrode 625 is formed using a metal film and the first electrode 623 is formed using a transparent conductive film, light emitted from the light-emitting element passes through only the substrate 610 and is extracted to one side, that is, bottom emission. Become a mold. In this case, the sealing substrate 633 and the filler 627 need not use a transparent material.

  In the case where the first electrode 623 is formed using a metal film and the second electrode 625 is formed using a transparent conductive film, light emitted from the light-emitting element passes through only the sealing substrate 633 and is extracted to one side, that is, Top emission type. In this case, the substrate 610 need not use a transparent material.

  In addition, materials for the first electrode 623 and the second electrode 625 need to be selected in consideration of a work function. However, each of the first electrode and the second electrode can be an anode or a cathode depending on the pixel configuration. When the polarity of the driving TFT is a p-channel type, the first electrode may be an anode and the second electrode may be a cathode. In the case where the polarity of the driving TFT is an N-channel type, it is preferable that the first electrode be a cathode and the second electrode be an anode.

FIG. 7 shows an equivalent circuit diagram in the pixel portion of this embodiment in the case of full color display. The TFT 638 in FIG. 7 corresponds to the switching TFT 638 in FIG. 5, and the TFT 639 corresponds to the current control TFT 639 in FIG. In the pixel displaying red, an OLED 703R that emits red light is connected to the drain region of the current control TFT 639, and an anode-side power supply line (R) 706R is provided in the source region. The OLED 703R is provided with a cathode side power supply line 700. In the pixel displaying green, an OLED 703G that emits green light is connected to the drain region of the current control TFT, and an anode power supply line (G) 706G is provided in the source region. In the pixel displaying blue, an OLED 703B that emits blue light is connected to the drain region of the current control TFT, and an anode power supply line (B) 706B is provided in the source region. Different voltages are applied to the pixels of different colors depending on the EL material.

In the light emitting device, a driving method for screen display is not particularly limited, and for example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the light-emitting device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

Further, in a light emitting device in which a video signal is digital, there are a video signal input to a pixel having a constant voltage (CV) and a constant current (CC). A video signal having a constant voltage (CV) includes a signal having a constant voltage applied to the light emitting element (CVCV) and a signal having a constant current applied to the light emitting element (CVCC). . In addition, when the video signal has a constant current (CC), the signal voltage applied to the light emitting element is constant (CCCV), and the signal applied to the light emitting element has a constant current (CCCC). There is.

  In the light emitting device, a protection circuit (such as a protection diode) for preventing electrostatic breakdown may be provided.

  Here, in order to correspond to FIG. 5, the switching TFT and the current control (driving) TFT have a double gate structure, but of course, either one or both may have a P-type or N-type single gate structure. Good.

  Although an example of an active matrix light-emitting device is described here as a display device, the present invention can also be applied to an active matrix liquid crystal display device. When applied to a liquid crystal display device, an exposure mask having the translucent film of the present invention is used when forming TFTs used for a pixel portion and a drive circuit portion of the liquid crystal display device. The gate electrode having different thicknesses in a self-aligned manner by performing processing such as etching using a resist having a region having at least two different resist film thicknesses and smooth edges. Can be formed. Furthermore, the present invention can also be applied when a contact hole communicating with a source or drain electrode is formed in an interlayer insulating film formed on a gate electrode. Therefore, electrodes having different shapes and openings having different depths can be formed without increasing the number of steps. As a result, elements can be integrated and formed according to the characteristics of the circuit.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1 and Embodiment Mode 2.

(Embodiment 4)
In the first to third embodiments, an example in which a photomask or reticle provided with a halftone film is used for pattern formation of a gate wiring is shown. However, a photomask or reticle provided with a halftone film is used as an interlayer insulating film. You may use for contact opening formation.

  In this embodiment, the photomask or reticle provided with the halftone film of the present invention is used for forming the gate electrode, forming the contact opening of the interlayer insulating film, and forming the pattern of the connection wiring. An example will be described with reference to FIG.

  In accordance with Embodiment 2, a base insulating film 718 is provided over a substrate 710 having an insulating surface, and then a semiconductor layer and a gate insulating film 714 covering the semiconductor layer are formed. Then, a first conductive film and a second conductive film are stacked, a resist pattern is formed using a photomask or a reticle provided with an auxiliary pattern having a light intensity reducing function, and etching is performed to form a gate electrode and a wiring.

Here, as in the first to third embodiments, the first conductive layer 731 and the second conductive layer 732 are formed in the first TFT portion 730, and the first conductive layer 721 and the second conductive layer 732 are formed in the second TFT portion 720. A conductive layer 722 is formed. In addition, since these electrode structures were demonstrated in Embodiment 1-3, detailed description is abbreviate | omitted here.

  8A, in the wiring portion and the contact portion 740, the first conductive layer 744 is wider than the second conductive layer 745 at a place where it is in contact with the upper wiring. In this way, even if a misalignment of the wiring with the upper layer occurs, the first conductive layer can be contacted. In addition, in the wiring other than the portion to be contacted, the end portions of the first conductive layer 741 and the second conductive layer 742 are formed to coincide with each other.

  Next, after forming a resist pattern covering the second TFT portion 720, an impurity element imparting n-type conductivity is added to the semiconductor layer. By adding the impurity element imparting n-type conductivity, the drain region 735a, the source region 735b, the first LDD region 736a, and the second LDD region 736b are formed in a self-aligned manner. Note that the addition of an impurity element imparting n-type conductivity may be performed by one doping process, or the doping process may be performed in a plurality of times.

  As shown in FIG. 8A, the first LDD region 736a is longer in the channel length direction than the second LDD region 736b. In addition, the first LDD region 736 a and the second LDD region 736 b overlap with the first conductive layer 731 with the gate insulating film 714 interposed therebetween.

  Next, after removing the resist pattern, a resist pattern covering the first TFT portion 730 is newly formed. Then, an impurity element imparting p-type conductivity is added to the semiconductor layer. By the addition of the impurity element imparting p-type, the drain region 725a, the source region 725b, the third LDD region 726a, and the fourth LDD region 726b are formed in a self-aligned manner.

As shown in FIG. 8A, the third LDD region 726a has substantially the same width in the channel length direction as the fourth LDD region 726b. In addition, the third LDD region 726 a and the fourth LDD region 726 b overlap with the first conductive layer 721 with the gate insulating film 714 interposed therebetween.

  The order of adding the impurity elements is not particularly limited. For example, the impurity element imparting p-type conductivity may be added to the semiconductor layer first, and then the impurity element imparting n-type conductivity may be added to the semiconductor layer.

Next, after the impurity element added to the semiconductor layer is activated, an interlayer insulating film 715 is formed, and a resist film is applied thereon.

  Next, the resist film is exposed and developed using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function, so that a resist pattern 750 shown in FIG. 8A is formed. The resist pattern 750 is a mask for forming an opening in a lower insulating film, and openings having different depths are provided by a photomask or a reticle provided with an auxiliary pattern having a light intensity reducing function.

  Next, etching is performed using the resist pattern 750 to form openings in the interlayer insulating film 715 and the gate insulating film 714. In this etching, openings of the interlayer insulating film 715 and the gate insulating film 714 are formed while the resist pattern 750 is etched, so that openings with different depths can be formed.

  Next, the resist pattern is removed. A cross-sectional view at this stage is illustrated in FIG.

  Next, a stack of a third conductive layer (such as a titanium nitride film) and a fourth conductive layer (such as an aluminum film) is formed. Then, patterning is performed to connect the third conductive layer 761 of the connection wiring, the fourth conductive layer 766 of the connection wiring, the third conductive layer 762 of the drain wiring, the fourth conductive layer 767 of the drain wiring, and the third conductive layer of the source wiring. A conductive layer 763 and a fourth conductive layer 768 of a source wiring are formed. In addition, in the second TFT portion, a third conductive layer 765 as a connection electrode, a fourth conductive layer 770 as a connection electrode, a third conductive layer 764 as a source electrode, and a fourth conductive layer 769 as a source electrode are formed. Here, the photomask or reticle provided with the halftone film of the present invention is used for forming the pattern of the connection electrode. The third conductive layer 765 of the connection electrode is wider in the channel length direction than the fourth conductive layer 770 of the connection electrode.

  Next, plasma treatment is performed to oxidize the fourth conductive layer to form an oxide film 771 on the surface of the fourth conductive layer.

Note that when the fourth conductive layer is oxidized by plasma treatment, the atmosphere is an oxygen atmosphere (for example, an atmosphere of oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or Plasma treatment is performed in an atmosphere of oxygen and hydrogen (H ₂ ) and a rare gas atmosphere or a dinitrogen monoxide and rare gas atmosphere. On the other hand, in the case of nitriding a film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or nitrogen and hydrogen And a rare gas atmosphere or NH ₃ and a rare gas atmosphere). As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating film formed by the plasma treatment contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing, and when Ar is used, the insulating film Contains Ar.

In addition, when plasma treatment is performed on the fourth conductive layer, the plasma treatment is performed in an atmosphere of the above gas with an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the electron temperature of plasma is 0.5 eV to 1.5 eV. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (herein, the fourth conductive layer) formed on the substrate is low, damage to the object to be processed can be prevented. . In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower by 100 degrees or more than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma.

Next, one electrode 772 included in the light-emitting element is formed. The electrode 772 is disposed so as to partially overlap with the third conductive layer 765 of the connection electrode, and is electrically connected to the TFT. The electrode 772 is made of a material having a high work function, for example, an element selected from Ni, W, Cr, Pt, Zn, Sn, In, or Mo, or an alloy material containing the element as a main component, for example, TiN, TiSi _X N _A single layer film or a stacked film thereof may be used in a total film thickness range of 100 nm to 800 nm using _Y , WSi _X , WN _X , WSi _X N _Y , and NbN.

  Next, an insulator 773 (referred to as a bank, a partition, a barrier, a bank, or the like) is formed to cover an end portion of one electrode 772 included in the light-emitting element.

  Next, a light-emitting layer (EL layer) 774 is formed over the electrode 772 by an evaporation method or a coating method.

  Next, another electrode 775 which forms a light-emitting element is formed over the light-emitting layer 774. For the electrode 775, an alloy such as MgAg, MgIn, or AlLi, or a transparent conductive film (such as ITO) may be used.

  In this manner, in the second TFT portion 720, a light-emitting element including one electrode 772, the light-emitting layer 774, and the other electrode 775 and a p-channel TFT connected to the light-emitting element are formed. The The TFT connected to the light emitting element preferably has an LDD region having the same width in order to reduce off current.

  In addition, as a TFT constituting a part of the buffer circuit of the driver circuit, an n-channel TFT shown in the first TFT portion 730 is preferably arranged. The n-channel TFT shown in the first TFT portion 730 can alleviate electric field strength near the drain and suppress circuit deterioration. In addition, the n-channel TFT shown in the first TFT portion 730 can reduce parasitic capacitance, so that power consumption of the circuit can be reduced.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3.

(Embodiment 5)
Here, an example in which an FPC or a driving IC for driving is mounted on a light-emitting display panel will be described with reference to FIG.

  FIG. 9A illustrates an example of a top view of a light-emitting device in which an FPC 1209 is attached to four terminal portions 1208. Over a substrate 1210, a pixel portion 1202 including a light emitting element and a TFT, a gate side driver circuit 1203 including a TFT, and a source side driver circuit 1201 including a TFT are formed. The active layer of the TFT is composed of a semiconductor film having a crystal structure, and these circuits are formed on the same substrate. Therefore, an EL display panel that realizes system-on-panel can be manufactured.

Note that the substrate 1210 is covered with a protective film except for the contact portion, and a base layer containing a substance having a photocatalytic function is provided over the protective film.

  In addition, connection regions 1207 provided at two positions so as to sandwich the pixel portion are provided in order to contact the second electrode of the light emitting element with a lower wiring. Note that the first electrode of the light-emitting element is electrically connected to a TFT provided in the pixel portion.

  Further, the sealing substrate 1204 is fixed to the substrate 1210 with a sealant 1205 that surrounds the pixel portion and the driver circuit and a filling material that is surrounded by the sealant. Moreover, it is good also as a structure filled with the filling material containing a transparent desiccant. Further, a desiccant may be disposed in a region that does not overlap with the pixel portion.

  Further, the structure shown in FIG. 9A shows a preferable example of a light emitting device having a relatively large size (for example, 4.3 inches diagonal) of the XGA class, but FIG. 9B shows a narrow frame. This is an example in which a suitable COG method is adopted with a small size (for example, a diagonal of 1.5 inches).

  In FIG. 9B, a driver IC 1301 is mounted on a substrate 1310, and an FPC 1309 is mounted on a terminal portion 1308 arranged at the tip of the driver IC. A plurality of driver ICs 1301 to be mounted may be formed on a rectangular substrate having a side of 300 mm to 1000 mm or more from the viewpoint of improving productivity. That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit are formed on the substrate, and finally, the drive ICs may be taken out by dividing them. The length of the driving IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel portion and the pixel pitch. May be formed to have a length obtained by adding one side of the pixel region or one side of the pixel portion and one side of each driver circuit.

  The advantage of the external dimensions of the driving IC over the IC chip is the length of the long side. When a driving IC having a long side of 15 to 80 mm is used, the number required for mounting corresponding to the pixel portion is obtained. This is less than when an IC chip is used, and the manufacturing yield can be improved. Further, when the driving IC is formed over the glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

  Alternatively, a TAB (Tape Automated Bonding) method may be employed. In that case, a plurality of tapes may be attached and a driving IC may be mounted on the tapes. As in the case of the COG method, a single drive IC may be mounted on a single tape. In this case, a metal piece or the like for fixing the drive IC may be attached together due to strength problems. .

  A connection region 1307 provided between the pixel portion 1302 and the driver IC 1301 is provided in order to contact the second electrode of the light-emitting element with a lower wiring. Note that the first electrode of the light-emitting element is electrically connected to a TFT provided in the pixel portion.

  In addition, the sealing substrate 1304 is fixed to the substrate 1310 with a sealing material 1305 surrounding the pixel portion 1302 and a filling material surrounded by the sealing material.

  In the case where an amorphous semiconductor film is used as the active layer of the TFT in the pixel portion, it is difficult to form a driver circuit over the same substrate. It becomes.

  Although an example of an active matrix light-emitting device is shown here as a display device, it is needless to say that the present invention can also be applied to an active matrix liquid crystal display device. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, thereby arranging the pixel electrode provided on the element substrate and the counter electrode provided on the counter substrate. The optical modulation of the liquid crystal layer is performed, and this optical modulation is recognized by the observer as a display pattern. The counter substrate and the element substrate are arranged at equal intervals and filled with a liquid crystal material. The liquid crystal material may be a method of dropping the liquid crystal under reduced pressure so that bubbles do not enter with the sealing material as a closed pattern, and bonding both substrates together, or providing a sealing pattern having an opening, and a TFT substrate Alternatively, a dip type (pumping type) in which liquid crystal is injected by using a capillary phenomenon after bonding may be used.

  The present invention can also be applied to a liquid crystal display device using a field sequential driving method in which an optical shutter is used without using a color filter and the backlight light sources of three colors of RGB blink at high speed.

  As described above, various electronic devices can be completed using the manufacturing method or the structure according to any one of Embodiments 1 to 4 in accordance with the present invention.

(Embodiment 6)
Semiconductor devices and electronic devices manufactured using the exposure mask of the present invention include video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), notebooks Type personal computer, game machine, portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), and image playback device (specifically, Digital Versatile Disc (DVD)) provided with a recording medium For example, a device provided with a display capable of reproducing the image and displaying the image. Specific examples of these electronic devices are shown in FIGS.

  FIG. 10A illustrates a digital camera, which includes a main body 2101, a display portion 2102, an imaging portion, operation keys 2104, a shutter 2106, and the like. Note that FIG. 10A is a view from the display portion 2102 side, and the imaging portion is not shown. By using the halftone mask according to the present invention, a highly reliable digital camera having a high-definition display portion can be realized. Note that the digital camera in FIG. 10A can be a digital camera with a TV that can display a television screen on the display portion 2102.

FIG. 10B illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. By using the halftone mask according to the present invention, a notebook personal computer having a high-definition display portion and high reliability can be realized.

  FIG. 10C illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. A display portion A2403 mainly displays image information, and a display portion B2404 mainly displays character information. Note that an image reproducing device provided with a recording medium includes a home game machine and the like. By using the halftone mask according to the present invention, a highly reliable image reproducing device having a high-definition display portion can be realized.

  FIG. 10D illustrates a display device, which includes a housing 1901, a support base 1902, a display portion 1903, a speaker 1904, a video input terminal 1905, and the like. This display device is manufactured by using a thin film transistor formed by the manufacturing method described in the above embodiment for the display portion 1903 and a driver circuit. The display device includes a liquid crystal display device, a light emitting device, and the like, and specifically includes all information display devices such as a computer, a television receiver, and an advertisement display. By using the halftone mask according to the present invention, a highly reliable display device having a high-definition display portion, particularly a large display device having a large screen of 22 inches to 65 inches can be realized. it can.

  Further, in addition to a thin film integrated circuit having a TFT formed using the halftone mask according to the present invention, an antenna or the like is formed, so that a non-contact thin film integrated circuit device (wireless IC tag, RFID (wireless authentication, radio) (Also called Frequency Identification)). In addition, by attaching the IC tag to various electronic devices, the distribution route of the electronic devices can be clarified.

  FIG. 10E shows a state where the wireless IC tag 1942 is attached to the passport 1941. A wireless IC tag may be embedded in the passport 1941. Similarly, you can attach or embed a wireless IC tag to a driver's license, credit card, banknote, coin, securities, gift certificate, ticket, traveler's check (T / C), health insurance card, resident card, family register copy, etc. it can. In this case, only information indicating authenticity is input to the wireless IC tag, and an access right is set so that information cannot be read or written illegally. By using it as a tag in this way, it becomes possible to distinguish it from a forged one. In addition, a wireless IC tag can be used as a memory. In addition, by providing wireless IC tags in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, and the like, it is possible to improve the efficiency of systems such as inspection systems.

11 includes a main body (A) 901 provided with operation switches 904, a microphone 905, a display panel (A) 908, a display panel (B) 909, a speaker 906, and the like. A main body (B) 902 is connected with a hinge 910 so as to be opened and closed. The display panel (A) 908 and the display panel (B) 909 are housed in the housing 903 of the main body (B) 902 together with the circuit board 907. The pixel portions of the display panel (A) 908 and the display panel (B) 909 are arranged so as to be visible from an opening window formed in the housing 903.

  In the display panel (A) 908 and the display panel (B) 909, specifications such as the number of pixels can be set as appropriate in accordance with the function of the mobile phone 900. For example, the display panel (A) 908 can be combined as a main screen and the display panel (B) 909 can be combined as a sub-screen.

  By using the halftone mask according to the present invention, a highly reliable portable information terminal having a high-definition display portion can be realized.

  The mobile phone according to the present embodiment can be transformed into various modes depending on the function and application. For example, a mobile phone with a camera may be obtained by incorporating an image sensor at the hinge 910. In addition, the above-described effects can be obtained even when the operation switches 904, the display panel (A) 908, and the display panel (B) 909 are housed in one housing. Moreover, even if the configuration of the present embodiment is applied to an information display terminal having a plurality of display units, the same effect can be obtained.

  As described above, various electronic devices can be completed using the manufacturing method or the structure according to any one of Embodiments 1 to 5 according to the present invention.

  In the halftone mask, the phase difference and the transmittance of the exposure light transmitted through the halftone film with respect to the exposure light transmitted through the transparent region satisfy the relationship of Expression (5), thereby having regions having different film thicknesses. In the resist, it is possible to form a resist in which a convex portion is not formed at the end portion and the end portion has a gentle shape. Various circuits can be formed on the same substrate in a self-aligned manner without increasing the number of steps by using a halftone mask that satisfies this condition.

Corresponds to the vicinity of the boundary between the translucent area and the transparent area when the phase difference Δθ between the exposure light that passes through the translucent area of the halftone mask and the exposure light that passes through the transparent area and the transmissivity n of the translucent film are changed. The graph (A) showing the relationship with the exposure intensity on the board | substrate to perform, and sectional drawing (B) of a halftone mask. Sectional drawing of the resist pattern formed using the halftone mask. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. Sectional drawing of a light-emitting device. The top view in a pixel part. FIG. 6 is a diagram illustrating an equivalent circuit in a pixel portion. Sectional drawing of a light-emitting device. The figure which shows an example of a module. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. A cross-sectional photograph of a resist pattern formed using a conventional halftone mask.

Explanation of symbols

100 translucent substrate 101 translucent film 104 light shielding film 106 exposure light 107 exposure light 108 exposure light 200 translucent substrate 201 halftone film 202 substrate 203 resist 204 light shielding film 205 resist pattern 301 substrate 302 first insulating film 303 semiconductor Layer 304 Second insulating film 305a Conductive layer 305b Conductive layer 306a Conductive layer 306b Conductive layer 307a Resist pattern 307b Resist pattern 309a Low-concentration one-conductivity type impurity region (low-concentration impurity region)
309b Low-concentration one-conductivity type impurity region (low-concentration impurity region)
310 High-concentration one-conductivity type impurity region 312 Insulating film 313 Insulating film 314 Source electrode 315 Drain electrode 400 Substrate 401 Light shielding portion 402 Translucent film 403a Non-exposed region 403b Exposed region 500 Substrate 502 Semiconductor layer 503 Semiconductor layer 504 Gate insulating layer 505 Conductive film 506 Conductive film 508 Insulating layer 520 TFT portion 521 Gate electrode layer 522 Gate electrode layer 523 Resist pattern 524a Low concentration impurity region 524b Low concentration impurity region 525a High concentration impurity region 525b High concentration impurity region 526a Low concentration impurity region 529 Resist pattern 530 TFT portion 531 Gate electrode layer 532 Gate electrode layer 533 Resist pattern 534a Low concentration impurity region 534b Low concentration impurity region 535a High concentration impurity region 535b High concentration impurity region 536a Concentration impurity region 536b Low concentration impurity region 539 Resist pattern 540 Wiring portion 541 Wiring layer 542 Wiring layer 543 Resist pattern 549 Resist pattern 610 Substrate 611 Underlying insulating film 613 Insulating film 623 First electrode 624 Light emitting layer 625 Second electrode 626 Protection Layer 627 Filler 628 Sealant 629 Insulator 631 Anisotropic conductive film 632 FPC (Flexible Print Circuit)
633 Sealing substrate 636 TFT
637 TFT
638 TFT
639 TFT
700 Cathode side power supply line 703B OLED
703G OLED
703R OLED
706B Anode power line (B)
706G Anode power line (G)
706R Anode power line (R)
710 Substrate 714 Gate insulating film 715 Interlayer insulating film 718 Base insulating film 720 TFT portion 721 Conductive layer 722 Conductive layer 725a Drain region 725b Source region 726a LDD region 726b LDD region 730 TFT portion 731 Conductive layer 732 Conductive layer 735a Drain region 735b Source region 736a LDD region 736b LDD region 740 Contact portion 741 Conductive layer 742 Conductive layer 744 Conductive layer 745 Conductive layer 750 Resist pattern 761 Conductive layer 762 Conductive layer 763 Conductive layer 764 Conductive layer 765 Conductive layer 766 Conductive layer 767 Conductive layer 768 Conductive layer 769 Conductive Layer 770 Conductive layer 771 Oxide film 772 Electrode 773 Insulator 774 Light-emitting layer 775 Electrode 900 Mobile phone 901 Main body (A)
902 Body (B)
903 Housing 904 Operation switches 905 Microphone 906 Speaker 907 Circuit board 908 Display panel (A)
909 Display panel (B)
910 Hinge 1201 Source side driving circuit 1202 Pixel portion 1203 Gate side driving circuit 1204 Sealing substrate 1205 Sealing material 1207 Connection region 1208 Terminal portion 1209 FPC
1210 Substrate 1301 Drive IC
1302 Pixel portion 1304 Sealing substrate 1305 Sealing material 1307 Connection region 1308 Terminal portion 1309 FPC
1310 Substrate 1901 Case 1902 Support base 1903 Display unit 1904 Speaker 1905 Video input terminal 1941 Passport 1942 Wireless IC tag 2101 Main unit 2102 Display unit 2104 Operation key 2106 Shutter 2201 Main unit 2202 Case 2203 Display unit 2204 Keyboard 2205 External connection port 2206 Pointing mouse 2401 body 2402 housing 2403 display part A
2404 Display B
2405 Recording medium (DVD etc.) reading unit 2406 Operation key 2407 Speaker unit

Claims (8)

An exposure mask characterized in that a phase difference Δθ of light used for exposure passing through a transparent region and a semi-transparent region and a transmittance n for light used for exposure of the semi-transparent region satisfy Expression (1).
The phase difference Δθ of light used for exposure through the transparent region and the semi-transparent region and the transmittance n for the light used for exposure of the semi-transparent region satisfy the formula (2), and the transmittance n is 0. An exposure mask characterized by being 15 or more and 0.8 or less.
An exposure mask having a translucent substrate, a translucent film disposed on the translucent substrate, and a light-shielding film disposed on the translucent film,
An exposure mask characterized in that a phase difference Δθ between the translucent film and the translucent substrate for light used for exposure and a transmittance n for light used for exposure of the translucent film satisfy Expression (3). .
An exposure mask having a translucent substrate, a translucent film disposed on the translucent substrate, and a light-shielding film disposed on the translucent film,
An exposure mask, wherein a phase difference between the translucent film and the translucent substrate with respect to light used for exposure is −90 degrees or more and 90 degrees or less.   5. The exposure mask according to claim 3, wherein the light shielding film is a Cr film or a film made of a laminate of Cr.   6. The exposure mask according to claim 3, wherein an alloy containing Mo and Si, an alloy containing Cr and Si, or Cr is used as a material of the translucent film.   7. The exposure mask according to claim 3, wherein a transmittance for light used for exposure of the translucent film is 0.15 or more and 0.8 or less.   8. The exposure mask according to claim 1, wherein the light used for the exposure is i-line.