JP2002151523A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve the problem in a conventional method such as that the gate electrode frequently becomes a two-layer structure, so a film growth process and an etching process become complicated, though the LDD structure and the GOLD structure in a semiconductor device are made in a self alignment manner, using a gate electrode as a mask, and that the transistor structures all become the same since the LDD structure and the GOLD structure are made with only the process of dry etching or the like, and it is difficult to form the LDD structure, the GOLD structure, and the single drain structure separately for each circuit. SOLUTION: It is possible to simply form a transistor of GOLD structure, LDD structure, or single drain structure separately for each circuit through dry etching and ion implantation process, by applying a photomask, where a diffraction grating pattern or an auxiliary pattern having a luminous intensity reducing function and consisting of a semitransparent film is installed, or a reticle to a photolithography process for formation of a gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of a thin film transistor (hereinafter abbreviated as TFT) and a MOS transistor. As the semiconductor device, for example, there are electro-optical devices such as a liquid crystal display and an EL (electroluminescence) display constituted by TFTs, and an LSI constituted by MOS transistors.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display technology using a TFT has attracted attention. Active matrix displays are more advantageous than passive matrix displays in terms of response speed, viewing angle, and contrast.
Currently, notebook PCs, LCD TVs, etc. have become mainstream.

In general, a TFT uses amorphous silicon or polycrystalline silicon as a channel layer (channel formation region). In particular, a polycrystalline silicon TFT manufactured only by a low-temperature process (generally 600 ° C. or lower) has a low electric field and a large area, and at the same time, has a large electric field mobility of electrons or holes. The feature is that not only transistors for pixels but also drivers as peripheral circuits can be integrated, and development has been promoted by each liquid crystal display manufacturer.

However, in the case of a polycrystalline silicon TFT, when continuously driven, the mobility and the on-current (current flowing when the TFT is on) decrease and the off-current (current flowing when the TFT is off) increases. Degradation phenomena such as reliability may be observed, which may be a serious problem in reliability. This phenomenon is called a hot carrier phenomenon, and it is known that hot carriers are generated by a high electric field near the drain.

Incidentally, this hot carrier phenomenon is a phenomenon first discovered in MOS transistors. For this reason, various basic studies have been conducted as measures against hot carriers, and the design rule is 1.5 μm
In the following MOS transistors, as a countermeasure against the hot carrier phenomenon due to a high electric field near the drain, an LDD (Ligh
tly Doped Drain) structure is adopted. In the LDD structure, a low-concentration impurity region (n-region or p-region) is provided at the end of the drain region using the sidewall of the gate side wall, and the impurity concentration at the junction between the channel formation region and the drain region is inclined. This reduces the electric field concentration in the vicinity of the drain.

However, in the case of the LDD structure, the drain withstand voltage is considerably improved as compared with the single drain structure, but the drain current is reduced because the resistance of the low concentration impurity region (n-region or p-region) is large. There are difficulties. In addition, a high electric field region exists directly below the sidewall, where impact ionization is maximized and hot electrons are injected into the sidewall, so that the low-concentration impurity region (n-region or p-region) is depleted, Further, a degradation mode peculiar to the LDD in which the resistance increases is a problem. Since the above problems have become apparent with the decrease in channel length, in a MOS transistor of 0.5 μm or less, as a structure to overcome this problem, a low-concentration impurity region (n -Region forming G)
An OLD (Gate-drain Overlapped LDD) structure has been devised and adopted.

In a polycrystalline silicon TFT, a MOS
In order to reduce the high electric field near the drain similarly to the transistor, adoption of an LDD structure and a GOLD structure is being studied. In the case of the LDD structure, a low-concentration impurity region (n-region or p-region) is formed in a polycrystalline silicon layer corresponding to a region outside the gate electrode, and a high-concentration impurity region (n + region) serving as source and drain regions further outside thereof. Or p + region), and the effect of suppressing the off-current value is high, but the effect of countermeasures against hot carriers by relaxing the electric field near the drain is small. On the other hand, in the case of the GOLD structure, the low-concentration impurity region (n-region or p-region) of the LDD structure is formed so as to overlap the end of the gate electrode, and the hot carrier countermeasure effect is larger than that of the LDD structure. However, a disadvantage is that the off-current value increases.

[0008]

SUMMARY OF THE INVENTION Polycrystalline silicon TFT
Structure and GOLD in MOS and MOS transistors
High-concentration impurity regions (n
+ Region or p + region) and the low concentration impurity region (n− region or p− region) inside thereof are conventionally formed in a self-aligned manner using a gate electrode as a mask, and an increase in the photolithography process can be suppressed. Although there is an advantage, when the gate electrode is formed in a two-layer structure, the gate electrode can be manufactured more easily than in the case of a single-layer structure. However, when the gate electrode has a two-layer structure, there is a problem that a film forming process and an etching process are complicated.

Various circuits are included in a semiconductor device, and a GOLD structure having an excellent hot carrier countermeasure effect is suitable for some circuits, and an LDD structure having a small off-current value is suitable for some circuits. In some cases, in some cases, a single drain structure is suitable. Since the LDD structure and the GOLD structure are formed only by a process such as dry etching, the transistor structures in the semiconductor device are all the same, and the single drain structure, the LDD structure, and the GOLD structure are formed separately for each circuit. There is a problem that can not be.

In the GOLD structure, the length of the low-concentration impurity region (n-region or p-region) is basically equal to that of the first gate electrode film formed by etching such as side etching. Is determined by the area where only
There is a problem that the length of the low-concentration impurity region (n-region or p-region) is restricted or the length cannot be sufficiently secured.

An object of the present invention is to provide a method for manufacturing a semiconductor device which can solve the above-mentioned problems.

[0012]

In a photomask or reticle for forming a gate electrode used in a photolithography process, the light intensity of exposure light is reduced at one or both ends of a mask pattern for forming a gate electrode. (In this specification, this pattern is referred to as an auxiliary pattern.) As a specific pattern having a function of reducing the light intensity of the exposure light in the auxiliary pattern, a diffraction grating pattern having a slit portion composed of lines and spaces equal to or less than the resolution limit of the exposure device, and reducing the transmittance of the exposure light Semi-permeable membranes are conceivable. In the case of a diffraction grating pattern, the light intensity of transmitted light can be adjusted by adjusting the pitch of the slit (space) portion and the slit width. In the case of one semipermeable membrane, the light intensity of the transmitted light can be adjusted by adjusting the transmittance of the semipermeable membrane.

According to another configuration of the present invention, the transmittance of the auxiliary pattern is not uniform but inclined, and the transmittance is high in proportion to the distance from the gate electrode forming mask pattern. It is configured to gradually increase as approaching the area. In this configuration, the diffraction grating pattern can adjust the light intensity of transmitted light by adjusting the pitch of the slit portion and the slit width, and can increase the transmittance in proportion to the distance from the end of the gate electrode forming mask pattern. In order to increase the slit width, the slit width is gradually increased. In the case of the semi-permeable film, the light intensity of the transmitted light can be adjusted by adjusting the thickness of the semi-permeable film or the transmittance itself, and is proportional to the distance from the end of the gate electrode forming mask pattern. The structure is such that the thickness of the semi-permeable membrane gradually decreases, or the transmittance itself of the semi-permeable membrane gradually increases.

In addition, since it is difficult to apply a negative resist as a resist used in the photolithography process in the present invention, the pattern configuration of the photomask or reticle for forming the gate electrode is based on a positive resist. .

[0015] The positive resist is a resist in which a region irradiated with exposure light is solubilized in a developing solution.
The negative resist is a type of resist in which a region irradiated with exposure light is insoluble in a developing solution.

In the case of performing exposure using the photomask or reticle for forming the gate electrode, the light intensity is zero in the main pattern region of the mask pattern for forming the gate electrode because the region is a light shielding portion. Since the outer region is a light transmitting portion, the light intensity is 100%. On the other hand, the light intensity is adjusted in the range of 10 to 70% in the auxiliary pattern area, which is a boundary area between the light shielding part and the light transmitting part. Then, by applying the photomask or reticle for forming the gate electrode to a photolithography process,
The resist thickness after development of one or both ends of the resist pattern after development is 10 to 10 times larger than the normal resist thickness.
It is formed thin in the range of 60%. Therefore, when both ends of the resist pattern are formed thin, a resist pattern having a convex shape is formed. When the transmittance of the auxiliary pattern is not uniform and is inclined, the film thickness at one or both ends of the developed resist pattern is in the range of 10 to 60% as compared with the normal case. Thus, a resist pattern shape having a tapered region in which the resist film thickness gradually decreases as approaching the end portion is formed.

Incidentally, single-wavelength exposure using a reduction projection exposure apparatus such as a stepper is partial coherent light in which the phase of exposure light is aligned to some extent. It is conceivable that the film acts as a halftone phase shifter. In this case, it is necessary to pay attention to the adjustment of the thickness of the semi-permeable film so that the phase between the adjacent exposure light does not reverse to about 180 °, and if possible, it is adjusted to about 360 °. Therefore, in the case of a reticle applied to a reduction projection exposure apparatus, in applying a semi-permeable film as an auxiliary pattern, the thickness of the semi-permeable film is considered in consideration of both the amount of phase shift and the transmittance. To adjust.

In the photolithography process of the present invention, it has already been described that only a positive resist is used. The reason will be described here. In the case of a negative resist, contrary to the positive resist, the main pattern area of the photomask or reticle for forming a gate electrode is a light-transmitting part, the area outside the auxiliary pattern is a light-shielding part, and the auxiliary pattern area is light intensity adjusted. Part (light intensity 10 ~
(Adjusted in the range of about 70%). When a negative resist is exposed using a photomask or a reticle having the pattern configuration, the auxiliary pattern area is not irradiated with exposure energy necessary and sufficient for forming a resist pattern, so that only the upper layer portion of the resist film is exposed. , And the lower layer is in an unexposed or underexposed state. When the negative resist in this state is developed, the upper layer of the resist film in the region is insoluble in the developing solution, but the lower layer is soluble in the developing solution. And a good pattern cannot be formed.

For the above reasons, in the photolithography process of the present invention, it is difficult to apply a negative resist.
Only positive resist is applied.

Structure 1 of the invention disclosed in this specification
Is a method of forming a conductive film on a semiconductor layer via an insulating film.
And a second step of forming a resist pattern having a region with a smaller thickness at the end than at the center using a photomask or a reticle having a diffraction grating pattern on the conductive film, and dry etching. A third step of forming a gate electrode having a thinner region at an end portion than at a central portion.
And implanting an impurity element into the semiconductor layer using the gate electrode as a mask to form a first layer outside the gate electrode.
And a fourth step of forming a second impurity region overlapping the thin region of the gate electrode.

In the second step, a resist pattern in which the thickness of the resist at one or both ends is reduced is formed.

In the third step, dry etching is performed. In the dry etching step, the region where the resist film thickness is small at the end of the resist pattern is gradually etched due to the problem of the selectivity between the gate electrode film and the resist film. The electrode film is exposed, and the etching of the gate electrode film in the region proceeds from this stage, so that the remaining thickness of the gate electrode film becomes a predetermined thickness of about 5 to 30% of the initial film thickness. In this way, a gate electrode structure having a region in which one or both ends of the gate electrode are thinner is formed.

In the fourth step, an n-type impurity or a p-type impurity is ion-implanted using the gate electrode as a mask, so that a high-concentration impurity region serving as a source and drain region is formed in a lower region corresponding to the outside of the gate electrode. (N +
Region or p + region), and a low-concentration impurity region (n− region or p− region) is formed in one or both sides of the gate electrode in a lower layer region corresponding to a thinned region of the gate electrode film. At this time, the acceleration voltage and the ion implantation amount during ion implantation are appropriately selected in consideration of the difference in the thickness of the gate electrode, so that the high-concentration impurity region (n + region or p + region) and the low-concentration impurity region (n− Region or p-
Region) can be formed simultaneously.

Here, the definition of the term "ion implantation" will be clarified. In general, the term “ion implantation” is applied to impurity ions with mass separation, and the term “ion doping” is applied to impurity ions without mass separation. In this specification, the terms “ion implantation” and “ion doping” are not used properly, and the term “ion implantation” is used regardless of the mass separation of impurity ions.

According to a second aspect of the invention, a first step of forming a conductive film on a semiconductor layer via an insulating film, and using a photomask or a reticle having a light intensity reducing means on the conductive film. A second step of forming a resist pattern having a thinner region at the end than the center, and a first dry etching to form a gate having a thinner region at the end from the center. A third step of forming an electrode, and injecting an impurity element into the semiconductor layer using the gate electrode as a mask, so that the first impurity region and the thin region of the gate electrode overlap with the outside of the gate electrode. A fourth step of forming a second impurity region; and a fifth step of performing a second dry etching to recede an end of the gate electrode.
And a step of:

In the second step, a resist pattern having a tapered region having a thinner resist film is formed as approaching one or both ends of the resist pattern.

In the third step, first dry etching is performed. Due to the problem of the selectivity between the gate electrode film and the resist film, the resist film is gradually etched by the dry etching process for the predetermined time, so that during the dry etching, the end of the resist pattern in the tapered region is formed. The underlying gate electrode film is gradually exposed from the region where the resist film thickness is small, and the etching of the gate electrode film proceeds from the end of the region. After the dry etching is performed so that the thickness of the gate electrode in the region becomes a predetermined thickness of about 5 to 30% of the initial thickness, the thickness of the gate electrode becomes thinner as approaching one or both ends of the gate electrode. A gate electrode structure having a tapered region is formed. The underlying gate insulating film exposed from the gate electrode is dry-etched and thinned to some extent.

In the fourth step, high-concentration ion implantation of an n-type impurity element or a p-type impurity element is performed using the gate electrode as a mask, so that a source is formed in a polycrystalline silicon film or a semiconductor substrate corresponding to the outside of the gate electrode. And a high-concentration impurity region (n + region or p
+ Region), and a low-concentration impurity region (n− region or p− region) is formed in the polycrystalline silicon film or semiconductor substrate corresponding to the thinned tapered region of the gate electrode film on one or both sides of the gate electrode. It is formed. On this occasion,
By appropriately selecting the acceleration voltage and the ion implantation amount at the time of ion implantation in consideration of the difference in the thickness of the gate electrode, a high-concentration impurity region (n + Region or p + region)
And simultaneously forming a low-concentration impurity region (n-region or p-region) in a polycrystalline silicon film or a semiconductor substrate corresponding to a tapered region having a thin gate electrode at the end of the gate electrode. be able to. In the tapered region at the end of the gate electrode, the thickness of the gate electrode gradually decreases as approaching the end of the gate electrode. Therefore, a low-concentration impurity region (n− region or There is a concentration gradient in the impurity concentration of the (p− region), and the impurity concentration tends to gradually increase as approaching the end of the gate electrode, that is, the end of the source and drain regions.

In the fifth step, a second dry etching is performed. By this dry etching for a predetermined time, the tapered region at the end of the gate electrode is dry-etched. As a result, the thickness of the gate electrode in the tapered region is further reduced, and the end of the gate electrode, which is the end of the tapered region, recedes. Therefore, the low-concentration impurity region (n-region or p-region) having the concentration gradient overlaps with the gate electrode (L-region).
ov area) and an area that does not overlap (Loff
Area and definition). At this time, the dimensions of the gate electrode can be freely adjusted within the range of the tapered region by appropriately changing the dry etching processing conditions. That is, within the range of the tapered region, L
The size of the ov region and the size of the Loff region can be freely adjusted. The underlying gate insulating film exposed from the gate electrode is further thinned by dry etching. Thereafter, an unnecessary resist pattern serving as a dry etching mask for the gate electrode is removed.

It is known that the Lov region is effective for hot carrier measures and the Loff region is effective for suppressing off current. The transistor formed here is a GOLD structure transistor effective for hot carrier countermeasures and has an Loff region that is effective for suppressing off-state current. As far as the current suppressing effect is concerned, the LDD described later
Structured transistors are more advantageous.

The above describes the method of forming a GOLD structure transistor. However, various circuits are included in a semiconductor device, and depending on the circuit, a GOLD structure transistor having an excellent hot carrier countermeasure effect is suitable. In some cases, an LDD transistor with a small off-current value is suitable. In some cases, a single-drain structure transistor is suitable. Therefore, a method for separately forming a GOLD structure, an LDD structure, and a single drain structure transistor for each circuit will be described below.

First, the method of forming the GOLD structure and the LDD structure transistors separately for each circuit in the first aspect of the invention can be handled by changing the process from the ion implantation step. After the dry etching step is completed, a first ion implantation step is performed to form a low-concentration impurity region (n− region or p− region) in the lower region corresponding to the outside of the gate electrode. Next, the resist pattern serving as a dry etching mask when the gate electrode is formed is removed. The removal of the resist pattern may be performed before the first ion implantation step. Next, in the LDD structure forming region, a new resist pattern is formed so as to cover the gate electrode. Next, high-concentration impurity regions (n + regions or p + regions) to be source and drain regions are formed by performing second ion implantation.

At this time, in the LDD structure forming region,
By performing ion implantation using the resist pattern covering the gate electrode as a mask, high-concentration impurity regions (n + regions or p + regions) serving as source and drain regions are formed in lower layers corresponding to regions exposed from the resist pattern. You. In the lower layer region outside the gate electrode and corresponding to the region inside the resist pattern, the low-concentration impurity region (n− region or p− region) has already been formed by the first ion implantation step.
− Region), and an LDD structure transistor is formed by forming the high concentration impurity region (n + region or p + region) this time.

On the other hand, in the GOLD structure forming region,
By performing ion implantation using the gate electrode as a mask, a high-concentration impurity region (n +
A region or p + region is formed, and at the same time, a low-concentration impurity region (n- region or p- region) is formed in a lower region corresponding to a thinned region of the gate electrode film on one or both sides of the gate electrode. The GOLD structure transistor has a high concentration impurity region (n + region or p + region) and a low concentration impurity region by appropriately selecting the acceleration voltage and the ion implantation amount at the time of ion implantation in consideration of the difference in the thickness of the end portion at the gate electrode. This can be realized by simultaneously forming a concentration impurity region (n-region or p-region).

It is to be noted that a low concentration impurity is implanted into the region already exposed from the gate electrode by the first ion implantation step, and a high concentration impurity which is the second ion implantation step is implanted therefrom. However, there is no particular problem in the formation of the high-concentration impurity regions (n + regions) serving as the source and drain regions. Thereafter, the resist pattern formed in the LDD structure forming region is removed.

Next, a method of forming a single drain structure transistor will be described below. The formation of a single-drain structure transistor is simple, and a single-drain structure transistor can be formed when an auxiliary pattern having a light intensity reducing function in a photomask for forming a gate electrode or a reticle is not provided. If there is no auxiliary pattern having a light intensity reducing function, the resist pattern and the gate electrode each have a rectangular shape, so that the low-concentration impurity regions ( The n− region or the p− region and the high-concentration impurity region (n + region or the p + region) overlap in the lower region corresponding to the outside of the gate electrode, thereby forming a single drain structure transistor. Note that the rectangular shape referred to in the present invention is not limited to a shape having four right angles, and includes a trapezoidal shape. Further, a shape like a rectangular shape and a shape like a trapezoid are also included.

By combining the above-described method for forming the GOLD structure and the transistor having the LDD structure with the above-described method for forming the single drain structure transistor, a GO
The LD structure, the LDD structure, and the single drain structure transistor can be formed separately.

Further, a method of separately forming a GOLD structure transistor and an LDD structure transistor for each circuit in Configuration 2 of the present invention will be described. First, a resist pattern is formed. At this time, in the photomask or reticle to be applied, an auxiliary pattern having a light intensity reducing function is provided in a mask pattern for forming a GOLD structure and a gate electrode forming region corresponding to the LDD structure forming region. In the gate electrode forming mask pattern corresponding to the above, the auxiliary pattern is not provided. As a result, in the resist patterns of the GOLD structure forming region and the LDD structure forming region, a tapered region in which the resist film thickness gradually decreases as approaching the end portion is formed. There is no tapered region, and a rectangular resist pattern is formed.

The dimensions of the tapered region in the resist pattern in the GOLD structure forming region and the LDD structure forming region are determined by the GOLD structure and the LD formed finally.
The mask pattern is formed to have an appropriate length by adjusting the size of the auxiliary pattern region of the mask pattern in consideration of the size of the low-concentration impurity region (n-region or p-region) in the D-structure transistor. At this time, the dimensions of the low-concentration impurity regions (n-regions or p-regions) of the GOLD structure and LDD structure transistors can be freely adjusted by adjusting the sizes of the auxiliary pattern regions provided in the corresponding mask patterns. Can be set. The thickness of the tapered region in the resist pattern of the GOLD structure forming region and the LDD structure forming region is determined by setting the transmittance of the auxiliary pattern region provided in the corresponding mask pattern to 1
By adjusting the thickness in the range of 0 to 70%, an appropriate resist film thickness (10 to 60% of the initial film thickness) is formed.

Next, a first dry etching process is performed.
GOLD is performed by this dry etching process for a predetermined time.
In the structure forming region and the LDD structure forming region, a gate electrode having a tapered region in which the gate electrode film thickness becomes thinner toward one or both ends of the gate electrode is formed. On the other hand, in the single drain structure formation region, a rectangular gate electrode is formed.

Next, high-concentration ion implantation of n-type impurities is performed using the gate electrode as a mask. In the GOLD structure forming region and the LDD structure forming region, high-concentration impurity regions (n + regions or p + regions) serving as source and drain regions are formed in a polycrystalline silicon film or a semiconductor substrate corresponding to the outside of the gate electrode. A low-concentration impurity region (n-region) is formed in the polycrystalline silicon film or the semiconductor substrate corresponding to the tapered region having a small gate electrode film thickness. On the other hand, in the single drain structure formation region, only the high concentration impurity region (n + region or p + region) serving as the source and drain regions is formed.

Next, a second dry etching process is performed. By the dry etching process for this predetermined time, GO
In the LD structure formation region, the tapered region at the end of the gate electrode is dry-etched, the gate electrode film thickness in the tapered region is further reduced, and the gate electrode end, which is the end of the tapered region, recedes. I do. After performing the dry etching process until the end of the gate electrode recedes to some extent, the low-concentration impurity region (n− region) is divided into an Lov region overlapping the gate electrode and an Loff region not overlapping. You. The tapered region of the gate electrode in the LDD structure forming region also has G
Dry etching is performed as in the case of the OLD structure forming region. On the other hand, the gate electrode in the single drain structure formation region is also dry-etched in the same manner. However, since the gate electrode has a rectangular shape, only the underlying gate insulating film is further etched. Thereafter, an unnecessary resist pattern serving as a dry etching mask for the gate electrode is removed.

When the second dry etching process and the removal of the resist pattern used as a mask for the dry etching are completed, the tapered region of the gate electrode in the LDD structure forming region may remain. Since it has disappeared and the future processing process changes, it is separately described below.

When the tapered region of the gate electrode in the LDD structure forming region remains after the dry etching for a predetermined time by the second dry etching process, the tapered region is selectively dry-etched. Then, it is necessary to remove the tapered region. Therefore, a new resist pattern is formed so as to open only the LDD structure formation region, and a third dry etching process is performed. By the dry etching process for the predetermined time, the tapered region is selectively removed, and a rectangular gate electrode is formed. As a result, in the polycrystalline silicon film or semiconductor substrate corresponding to the outside of the gate electrode, an L region having a low concentration impurity region (n− region or p− region) and a high concentration impurity region (n + region or p + region) is formed.
A DD transistor is formed. Thereafter, the resist pattern serving as the dry etching mask is removed.

On the other hand, if the tapered region of the gate electrode in the LDD structure forming region has disappeared after the dry etching for a predetermined time by the second dry etching process, only the LDD structure forming region is opened. The formation of a resist pattern and the third dry etching process are unnecessary. In this case, the formation of the LDD structure transistor has already been completed at the stage when the removal of the resist pattern serving as a mask for the second dry etching process and the dry etching is completed.

Through the above manufacturing steps, a GOLD structure, an LDD structure, and a single drain structure transistor can be separately formed for each circuit of a semiconductor device.

Further, the present invention is characterized in that a first step of forming a conductive film on a semiconductor layer via an insulating film and a photomask or a reticle having a light intensity reducing means on the conductive film are used. A second step of forming a resist pattern having a region with a smaller thickness at the end than the center and a first dry etching to form a gate electrode having a region with a smaller thickness at the end from the center. A third step of forming and a second step of injecting an impurity element into the semiconductor layer using the gate electrode as a mask and overlapping a first impurity region and a thin region of the gate electrode outside the gate electrode. And a fifth step of performing a second dry etching to recede an end of the gate electrode.

A resist pattern having a thin short portion is formed using a photomask or reticle having a diffraction grating, or is formed using a photomask or reticle having a semipermeable film.

According to the present invention, by applying a photomask or reticle for forming a gate electrode, in which an auxiliary pattern having a light intensity reducing function is provided to a mask pattern, to a photolithography process, GOLD can be easily performed through etching and ion implantation processes. A semiconductor device including a structured transistor can be manufactured.

Since the transmittance and the size of the light intensity reducing means can be arbitrarily set, the thickness of the tapered region at the end of the gate electrode formed through the photolithography process and the dry etching process is reduced. The film thickness and dimensions can be adjusted. For this reason, the low-concentration impurity region (n
(Region or p-region) and the size in the channel direction can be optimized, and the performance of the GOLD structure and LDD structure transistors can be improved.

In the manufacture of the semiconductor device comprising the GOLD structure transistor, the ion implantation step is divided into two steps, the first ion implantation step for low concentration impurities is performed, and then only the LDD structure forming region is formed. After a resist pattern is formed so as to cover the gate electrode, the process is changed so that the second ion implantation for the high-concentration impurities is performed, so that the LDD structure and GOLD structure transistors are separately provided for each circuit. It can be formed.

In the photomask or reticle for forming a gate electrode, an auxiliary pattern having a light intensity reducing function is provided in an arbitrary mask pattern, so that a single drain structure and a GOLD structure are provided for each circuit pattern of the semiconductor device. This makes it possible to form transistors separately.

Further, since the light intensity reducing means can be provided on an arbitrary mask pattern, the GOL is provided for each circuit of the semiconductor device.
A transistor having a D structure, an LDD structure, and a single drain structure can be easily formed.

[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) A photolithography process using a photomask or a reticle for forming a gate electrode having a light intensity reducing function composed of a diffraction grating pattern or a semi-permeable film has a GOLD structure polycrystalline silicon TFT.
A case where the present invention is applied to the formation of a film will be described with reference to FIGS.

First, the configuration of a photomask or a reticle for forming a gate electrode provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function formed of a semi-permeable film will be described with reference to FIG.

An auxiliary pattern having a light intensity reducing function is provided at one or both ends of a mask pattern in a photomask or a reticle for forming a gate electrode. FIGS. 1A and 1B show specific examples of the auxiliary pattern.
FIG. 1 shows an example of a diffraction grating pattern having a slit portion composed of lines and spaces below the resolution limit of the exposure apparatus.
Since it is difficult to apply a negative resist as the resist used in the photolithography process, the pattern configuration of the gate electrode forming photomask or the reticles 101 and 105 is based on a positive resist. Therefore, the main pattern region of the gate electrode forming mask pattern is the light shielding portions 102 and 106, the auxiliary pattern region having the light intensity reducing function is the slit portions 103 and 107, and the region outside the auxiliary pattern is the light transmitting portion 104. , 108. The direction of the slit in the slit portion is the same as that of the slit portion 103 in the main pattern (the light shielding portion 10).
The direction may be parallel to the direction of 2) or may be perpendicular to the direction of the main pattern (light-shielding portion 106) like the slit portion 107 (FIG. 1).
(A) and FIG. 1 (B)).

When the photomask or reticle 101 or 105 for forming the gate electrode is exposed to exposure light, the light intensity of the light shielding portions 102 and 106 is zero, and the light transmitting portion 10
The light intensity of 4,108 is 100%. On the other hand, the light intensity of the auxiliary pattern having the light intensity reduction function constituted by the slit portions 103 and 107 of the diffraction grating pattern composed of lines and spaces below the resolution limit of the exposure apparatus is 10 to
The light intensity distribution can be adjusted within a range of 70%, and a typical light intensity distribution is shown in a light intensity distribution 109. Adjustment of the light intensity of the slit portions 103 and 107 in the diffraction grating pattern is realized by adjusting the pitch and slit width of the slit portions 103 and 107 (FIG. 1C).

Next, as a specific example of the auxiliary pattern, FIG.
(D) shows an example of a semi-permeable film having a function of reducing the light intensity of exposure light. The main pattern region of the gate electrode forming photomask or the gate electrode forming mask pattern in the reticle 110 is a light shielding portion 111, and the auxiliary pattern region having a light intensity reducing function is a semi-transmissive portion 1 made of a semi-transmissive film.
In FIG. 12, the region outside the region is the light transmitting portion 113 (FIG. 1).
(D)).

When the photomask or reticle 110 for forming a gate electrode is irradiated with exposure light,
The light intensity of the light transmitting portion 113 is zero and 100%, respectively, and the light intensity of the auxiliary pattern region formed by the semi-light transmitting portion 112 made of a semi-transparent film can be adjusted within a range of 10 to 70%. An example of a typical light intensity distribution is shown in a light intensity distribution 114 (FIG. 1-E).

Next, G using a photomask or reticle 101, 105, 110 for forming a gate electrode having a light intensity reducing function consisting of a diffraction grating pattern or a semi-permeable film.
A method for forming an OLD structure polycrystalline silicon TFT will be described with reference to FIG.

The photomask or reticle 101, 10 for forming a gate electrode provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function composed of a semi-permeable film.
By applying 5,110 to the photolithography process, the resist pattern after development is reduced in the range of 10 to 60% of the thickness of the resist after development at one or both ends of the resist pattern. 205a are formed (FIG. 2A).

Next, the post-development resist pattern 205
Dry etching is performed using a as a mask. In this embodiment, the etching conditions are ICP (Inductively Coupling).
led Plasma (inductively coupled plasma) etching method, using CF ₄ and Cl _{2 as} etching gases, setting the respective gas flow ratios to 40:40 (sccm), and using 1.2.
450W RF (13.56MH
z) Power is applied, RF power (13.56 MHz) of 20 W is also applied to the substrate side (sample stage), plasma is generated, and etching is performed. In the dry etching step, the gate electrode film 204a exposed from the post-development resist pattern 205a is completely etched, and the underlying gate insulating film 203a made of a silicon oxynitride film is slightly over-etched. Dry etching is performed until On the other hand, in the region where the thickness of the resist is reduced at one or both ends of the post-development resist pattern 205a, the resist film is gradually etched due to the problem of the selectivity with respect to the gate electrode film 204a. Then, the resist film in the region disappears, and the gate electrode film 204a under the resist film is exposed. From this stage, the etching of the gate electrode film 204a in the region proceeds, and the remaining film thickness becomes 5 to 30 times the initial film thickness. % So as to have a predetermined thickness.

Here, the shape of the resist pattern in the dry etching step is changed from the post-development resist pattern 205a having the thinned resist film on one or both ends to the final resist pattern after the dry etching. It has changed to the shape of the pattern 205b. A gate electrode 204b having a region where one or both ends of the gate electrode film is thinned by dry etching is formed, and a gate made of a silicon oxynitride film as a lower layer film existing in a region exposed from the gate electrode 204b The insulating film 203b has a shape thinned by over-etching (FIG. 2B).

Next, using the gate electrode 204b as a mask, high-concentration ion implantation of n-type impurities is performed in the source and drain regions. A high-concentration impurity region (n + region) 206 serving as a source and drain region is formed in the polycrystalline silicon film 202 corresponding to a region exposed from the gate electrode 204b having a thinned region on one or both ends. Further, a low-concentration impurity region (n− region) 207 is formed in the polycrystalline silicon film 202 corresponding to the region where the thickness of the end portion of the gate electrode 204b is small. At this time, the high-concentration impurity region (n + region) 206 and the low-concentration impurity region (n− region) 207 take into account the difference in the thickness of the gate electrode, and appropriately adjust the acceleration voltage and the ion implantation amount during ion implantation. By selection, the high concentration impurity region (n + region) 2
06 and the low concentration impurity region (n− region) 207 can be formed at the same time. Note that the post-dry etching resist pattern 205b may be removed either before or after the ion implantation step (FIG. 2C).

Although the method of forming a GOLD structure polycrystalline silicon TFT has been described herein, the photomask or reticle 101, 105, 110 for forming a gate electrode on which an auxiliary pattern having a light intensity reducing function is provided is
GOLD structure M using semiconductor substrate such as silicon substrate
Of course, the present invention can be applied to the formation of an OS transistor.
In this case, the high-concentration impurity regions (n + regions) serving as source and drain regions and the low-concentration impurity regions (n− regions) overlapping the gate electrode are formed on a semiconductor substrate such as a silicon substrate.

(Embodiment 2) Various circuits are included in a semiconductor device such as a liquid crystal display. In some cases, a GOLD structure excellent in a hot carrier countermeasure effect is suitable for some circuits. In some cases, a small LDD structure is suitable, and in some cases, a single drain structure is suitable. Therefore, G
It is necessary to separately form a polycrystalline silicon TFT having an OLD structure, an LDD structure, and a single drain structure. In the second embodiment, a method of separately forming a polycrystalline silicon TFT having a GOLD structure, an LDD structure, and a single drain structure for each circuit will be described with reference to FIG.
The photomask or reticle 101, 105, 110 for forming the gate electrode (FIGS. 1A, 1B,
The configuration of (D)) has already been described in the first embodiment, and will not be described here.

As for the substrate structure used here, a polycrystalline silicon film 302 of a predetermined thickness and a gate insulating film 303 of a predetermined thickness of a silicon oxynitride film and a gate insulating film 303 of a predetermined thickness are formed on a glass substrate 301 of quartz glass or the like. A substrate having a structure in which gate electrode films 304 each having a thickness are stacked is used. Photomask or reticle 10 for forming a gate electrode in which a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function is provided on the substrate having the above structure.
Photolithography steps using 1, 105, and 110 (FIGS. 1A, 1B, and 1D) are performed to form resist patterns 305 and 306 after development for forming gate electrodes. Note that the resist pattern in (A-2) may be rectangular. (FIG. 21)

The GOLD structure forming region 401 and the LDD
In the structure forming region 402, since a mask pattern is provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function made of a semi-permeable film, the resist film thickness at both ends is smaller than that of the normal by 10%. The resist pattern 305 after development which is thinned in the range of about 60% is formed. On the other hand, in the single drain structure formation region 403,
Since there is no auxiliary pattern in the mask pattern, a normal rectangular post-development resist pattern 306 is formed (FIG. 3A).

Next, the post-development resist pattern 30
Dry etching is performed using 5,306 as a mask. In the dry etching process, the GOLD structure forming region 4
01 and the gate electrode film 30 exposed from the post-development resist pattern 305 in the LDD structure formation region 402
4 and the gate electrode film 304 exposed from the post-development resist pattern 306 in the single drain structure formation region 403 is completely etched, and a gate insulating film 303 made of a silicon oxynitride film existing further below. Is dry-etched until is slightly over-etched.

Post-development resist pattern 305 in GOLD structure forming region 401 and LDD structure forming region 402
In the regions where the thickness of the resist on both sides of the resist film is reduced, the resist film is gradually etched due to the problem of the selectivity with the gate electrode film 304, and the resist film in the region disappears during the dry etching. The lower gate electrode film 304 is exposed. From this stage, the etching of the gate electrode film 304 in the region proceeds, and the remaining film thickness is 5 to 30 times the initial film thickness.
% So as to have a predetermined thickness. Here, the shape of the resist pattern in the dry etching step has changed from the post-development resist pattern 305 to the shape of the post-dry etching resist pattern 307 finally. By dry etching, a gate electrode 308 having a region in which both ends on both sides of the pattern are thinned is formed, and a gate insulating film 309 made of a silicon oxynitride film as a lower layer present in a region exposed from the gate electrode 308 includes: It has a thin shape due to over-etching.

On the other hand, the single drain structure forming region 40
When dry etching is performed using the resist pattern 306 after development in Step 3 as a mask, the gate electrode film 304 as the lower layer film existing in the region exposed from the resist film is completely etched, and the gate electrode 311 is formed. Also,
Further, the gate insulating film 303 made of a silicon oxynitride film, which is a lower layer film, is subjected to dry etching until it is slightly over-etched, whereby a gate insulating film 312 thinned by over-etching is obtained (FIG. 3 ( B)).

Next, low concentration ion implantation of an n-type impurity, which is a first ion implantation process, is performed using the gate electrodes 308 and 311 formed by dry etching as a mask to cover regions exposed from the gate electrodes 308 and 311. Low concentration impurity region (n− region) 3 in the polycrystalline silicon film 302
13, 314 are formed (FIG. 3B).

Next, unnecessary post-dry etching resist patterns 307 and 3 serving as a mask for dry etching are used.
10 is resist-removed. Of course, the resist patterns 307 and 310 may be removed before the low concentration ion implantation. Then, in the LDD structure forming region 402, the resist pattern 3 is formed so as to cover the gate electrode 308.
15 is newly formed (FIG. 3C).

Next, high-concentration ion implantation of n-type impurities is performed as a second ion implantation process. At this time, in the GOLD structure forming region 401, ion implantation is performed using the gate electrode 308 as a mask, so that the gate electrode 308 is formed.
High-concentration impurity regions (n +) serving as source and drain regions in the polycrystalline silicon film 302 corresponding to regions exposed from
Region 316 is formed, and at the same time, the gate electrode 308
In the polycrystalline silicon film 302 corresponding to the thinned region of the gate electrode film existing on both sides of the gate electrode film.
Region 317 is formed. The GOLD structure polycrystalline silicon TFT has a high-concentration impurity region (n + region) by appropriately selecting an acceleration voltage and an ion implantation amount at the time of ion implantation in consideration of a difference in thickness of an end portion of the gate electrode 308. 316 and the low-concentration impurity region (n-region) 317 are formed at the same time.

In the region already exposed from the gate electrode 308, a low-concentration impurity region (n-region) 313 is formed by the first ion implantation process, and the second
The high-concentration impurity, which is the ion implantation process, is implanted, but there is no particular problem in the formation of the high-concentration impurity region (n + region) 316 to be the source and drain regions (FIG. 3D).

In the LDD structure forming region 402, the polysilicon film 302 corresponding to the region exposed from the resist pattern 315 is implanted by ion implantation using the resist pattern 315 covering the gate electrode 308 as a mask. A high-concentration impurity region (n + region) 318 serving as a source and drain region is formed. In the polycrystalline silicon film 302 corresponding to the region outside the gate electrode 308 and inside the resist pattern 315, the low-concentration impurity region (n− region) 3 is already formed by the first ion implantation process.
19 are formed, and together with the formation of the high-concentration impurity region (n + region) 318 by the second ion implantation process,
An LDD structure polycrystalline silicon TFT is formed (FIG. 3).
(D)).

The single drain structure forming region 40
In 3, a low-concentration impurity region (n− region) 314 is already formed in the polycrystalline silicon film 302 corresponding to the region exposed from the gate electrode 311 by the first ion implantation process. A high-concentration impurity region (n + region) 320 is formed by the second ion implantation process so as to overlap with. As described above, the single-drain structure polycrystalline silicon TFT has a structure in which the source and drain regions are formed only with the high-concentration impurity regions (n + regions) 320 (FIG. 3D).

Although the method of separately forming the GOLD structure, the LDD structure, and the single-drain structure polycrystalline silicon TFT has been described above, the photomask for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function is described. Alternatively, the reticles 101, 105, 110
MOS of the same structure using a semiconductor substrate such as a silicon substrate
Of course, the present invention can be applied to the formation of a type transistor. In this case, the high-concentration impurity region (n + region) and the low-concentration impurity region (n- region) are each formed on a semiconductor substrate such as a silicon substrate.

(Embodiment 3) A case where a photolithography process using a photomask or reticle for forming a gate electrode having a light intensity reducing function composed of a diffraction grating pattern or a semi-permeable film is applied to the formation of a GOLD structure polycrystalline silicon TFT. Will be described with reference to FIGS.
First, the configuration of a gate electrode forming photomask or a reticle provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function formed of a semi-permeable film will be described with reference to FIG.

A light intensity reduction function configured such that the transmittance is gradually increased in proportion to the distance from the mask pattern at one or both ends of the mask pattern in the photomask or reticle for forming a gate electrode. Is provided. FIGS. 9A and 9B show an example of a diffraction grating pattern having a plurality of slits formed of lines and spaces below the resolution limit of the exposure apparatus as a specific example of the auxiliary pattern. The structure is such that the slit width gradually increases in proportion to the distance from the pattern. Since it is difficult to apply a negative resist to the resist used in the photolithography process, the pattern configuration of the photomask for forming the gate electrode or the reticles 901 and 905 is based on a positive resist. Therefore, the main pattern region of the gate electrode forming mask pattern is the light shielding portions 902 and 906, and the auxiliary pattern region having the light intensity reducing function is the slit portion 9.
03, 907, the region outside the auxiliary pattern is the light transmitting portion 9
04,908. The direction of the slit of the slit portion may be parallel to the direction of the main pattern (light-shielding portion 902) as in the slit portion 903, or may be perpendicular to the direction of the main pattern (light-shielding portion 906) as in the slit portion 907 (FIG. 9-A and FIG. 9-B).

When the exposure light is applied to the photomask or reticle 901 or 905 for forming the gate electrode, the light intensity of the light shielding portions 902 and 906 is zero and the light transmitting portion 90
The light intensity of 4,908 is 100%. On the other hand, the light intensity of an auxiliary pattern having a light intensity reduction function constituted by a diffraction grating pattern having a plurality of slit portions 903 and 907 formed of lines and spaces equal to or less than the resolution limit of the exposure apparatus is in the range of 10 to 70%. The light intensity distribution 909 shows an example of a typical light intensity distribution. still,
The slit portions 903 and 90 in the diffraction grating pattern
7 is realized by adjusting the pitch and slit width of the slit portions 903 and 907 (FIG. 9-).
C).

FIG. 9D shows an example of a semi-permeable film having a function of reducing the light intensity of exposure light as a specific example of the auxiliary pattern. The transmissivity of the semi-permeable membrane is configured to gradually increase. Photomask or reticle 91 for forming gate electrode
The region of the main pattern of the mask pattern for forming a gate electrode at 0 is a light shielding portion 911, and the region of an auxiliary pattern having a light intensity reducing function is a semi-light transmitting portion 912 made of a semi-transmissive film.
The area outside the area is the light transmitting portion 913 (FIG. 9-D).

When the exposure light is irradiated on the photomask or reticle 910 for forming the gate electrode, the light shielding portion 911 is formed.
And the light intensity of the light transmitting portion 913 is zero and 100%, respectively. The transmittance is increased in proportion to the distance, and a typical example of the light intensity distribution is shown in FIG.
This is shown in FIG. 14 (FIG. 9-E).

Next, a photomask or reticle 901, 905, 910 for forming a gate electrode having a light intensity reducing function composed of a diffraction grating pattern or a semi-permeable film is used.
A method for forming an OLD structure polycrystalline silicon TFT will be described with reference to FIG.

The photomask or reticle 901 or 90 for forming a gate electrode on which a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function composed of a semi-permeable film is provided.
By applying 5,910 to the photolithography process, the film thickness at both side edges of the resist pattern is formed to be thinner within a range of 10 to 60% as compared with the normal, and the closer to the edge portion, the more the resist becomes. Post-development resist pattern 1005 having a tapered region with a gradually reduced thickness
Is formed (FIG. 10-A).

Note that the post-development resist pattern 1005
The resist film thickness of the tapered region becomes thinner as it approaches the end of the tapered region, and is freely set by appropriately adjusting the transmittance of the auxiliary pattern region provided in the corresponding mask pattern. It is possible. In consideration of the remaining etching thickness of the tapered region of the gate electrode formed in the first dry etching process and the second dry etching process as a post-process, the tapered region of the post-development resist pattern 1005 is appropriately adjusted. The resist is formed with a proper thickness. Further, the dimensions of the tapered region of the developed resist pattern 1005 can be freely set by adjusting the dimensions of the auxiliary pattern region provided in the corresponding mask pattern. The tapered region of the post-development resist pattern 1005 is formed to have an appropriate length in consideration of the size of the low-concentration impurity region (n-region) in the finally formed GOLD structure transistor ( FIG. 10-A).

Next, the post-development resist pattern 100
Using the mask 5 as a mask, a first dry etching process is performed. In this dry etching process for a predetermined time, the gate electrode film 1004 exposed from the post-development resist pattern 1005 is completely etched, and the gate insulating film 1003 existing on the lower layer is slightly over-etched. , A dry etching process is performed. On the other hand, in the tapered region where the resist film thickness is small at the end of the post-development resist pattern 1005, the selectivity between the gate electrode film 1004 and the resist film is problematic.
Since the resist film is gradually etched, the underlying gate electrode film 1004 is gradually exposed from the region where the resist film thickness is small at the end of the resist pattern in the tapered region during the dry etching. The etching of the gate electrode film 1004 proceeds from the portion.
Therefore, after the dry etching is performed so that the remaining film thickness of the gate electrode film 1004 in the region becomes a predetermined film thickness of about 5 to 30% of the initial film thickness, the gate electrode film thickness becomes smaller as approaching the gate electrode end. A gate electrode 1007 having a tapered region having a thin structure is formed.

Here, the shape of the resist pattern in the first dry etching step is finally changed from the post-development resist pattern 1005 having a tapered region in which the resist film thickness becomes thinner toward the pattern end. Has changed to the shape of the resist pattern 1006 after dry etching. By this dry etching, a gate electrode 1007 having a tapered region having a structure in which the film thickness becomes smaller as approaching the end of the gate electrode is formed. 1008 is obtained by over-etching
It has changed to a thinner shape (FIG. 10-B).

Next, using the gate electrode 1007 as a mask, high-concentration ion implantation of n-type impurities is performed into the source and drain regions. In the polycrystalline silicon film 1002 corresponding to the region exposed from the gate electrode 1007, a high-concentration impurity region (n + region) 1009 serving as a source and a drain region
Is formed. Further, a low-concentration impurity region (n− region) 1010 is formed in the polycrystalline silicon film 1002 corresponding to the tapered region having a structure in which the gate electrode becomes thinner as the gate electrode becomes closer to the end. At this time, in the tapered region at the end of the gate electrode 1007, the thickness of the gate electrode gradually decreases as approaching the end of the gate electrode 1007. There is a concentration gradient in the impurity concentration of the impurity region (n − region) 1010, and the impurity concentration tends to gradually increase as approaching the end of the gate electrode 1007, that is, the end of the source and drain regions. (Fig. 10-
B).

The ion implantation conditions are as follows:
The dose is 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² and the acceleration voltage is 60 to 100 kV. In the high concentration impurity region (n + region) 1009, 1 × 10 ²⁰ to 1 ×
An impurity of about 10 ²² atoms / cm ³ is ion-implanted, and in the low-concentration impurity region (n− region) 1010, 1 ×
Impurities of about 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ are ion-implanted.

Next, a second dry etching process is performed using the gate electrode 1007 as a mask. By this dry etching for a predetermined time, the tapered region at the end of the gate electrode 1007 is etched, the gate electrode film thickness in the tapered region is further reduced, and the end of the tapered region recedes. As a result, the gate electrode 1007
Is changed to the shape of the gate electrode 1011, and the low-concentration impurity region (n− region) 1010 having a concentration gradient is changed to the Lov region 10 overlapping the gate electrode 1011.
Loff area 1010b which does not overlap with 10a
Is divided into At this time, the dimensions of the gate electrode 1011 can be freely adjusted within the range of the tapered region of the gate electrode 1007 by appropriately changing the dry etching processing conditions. That is, the gate electrode 100
7, within the range of the tapered region, the Lov region 101
The size of Oa and the size of Loff region 1010b can be freely adjusted. The underlying gate insulating film 1012 exposed from the gate electrode 1011 is further thinned by dry etching. After that, the gate electrode 101
The unnecessary resist pattern 1006 serving as the dry etching mask 1 is removed (FIG. 10C). Of course, before the high-concentration ion implantation, the resist pattern 1
006 may be removed.

Although the method of forming a GOLD-structured polycrystalline silicon TFT has been described here, the gate electrode forming photomask or reticle 901, 905, 910 provided with an auxiliary pattern having a light intensity reducing function is as follows.
GOLD structure M using semiconductor substrate such as silicon substrate
Of course, the present invention can be applied to the formation of an OS transistor.
In this case, the high concentration impurity region (n + region) and the low concentration impurity region (n− region) are formed on a semiconductor substrate such as a silicon substrate.

(Embodiment 4) Various circuits are included in a semiconductor device such as a liquid crystal display. Depending on the circuit, a GOLD structure excellent in a hot carrier countermeasure effect is suitable in some cases. In some cases, a small LDD structure is suitable, and in some cases, a single drain structure is suitable. Therefore, G
It is necessary to separately form a polycrystalline silicon TFT having an OLD structure, an LDD structure, and a single drain structure. In the fourth embodiment, a method for separately forming a polycrystalline silicon TFT having a GOLD structure, an LDD structure, and a single drain structure for each circuit will be described with reference to FIG.

In the present embodiment, a case where a tapered region as an etching residual film remains in the gate electrode 1123 of the LDD structure forming region 1502 after the second dry etching process is described. The case where the formation of a resist pattern for opening only the LDD structure formation region 1502 and the third dry etching process in the process are required is described. Also, the photomask or reticle 901, 905, 910 for forming the gate electrode is formed.
The configuration of (FIGS. 9A, 9B, and 9D) has already been described in the first embodiment, and will not be described here.

The substrate structure used in this embodiment is such that a polycrystalline silicon film 1102 having a predetermined thickness is formed on a glass substrate 1101.
A substrate having a structure in which a gate insulating film 1103 having a predetermined thickness and a gate electrode film 1104 having a predetermined thickness are stacked is used. Photomask or reticle 9 for forming a gate electrode, on which a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function, which is formed of a semi-permeable film, is provided on a substrate having the above structure.
A photolithography process is performed by using the photolithography steps 01, 905, and 910 (FIGS. 9A, 9B, and 9D) to form resist patterns 1105, 1106, and 1107 after development. here,
The width of the auxiliary pattern in 1105 and the width of the auxiliary pattern in 1106 are different, but may of course be the same width.

At this time, in the photomask or reticle 901, 905, 910 for forming the gate electrode to be applied, the light intensity is applied to the mask pattern for forming the gate electrode corresponding to the GOLD structure forming region 1501 and the LDD structure forming region 1502. Install an auxiliary pattern with a reduction function,
The gate electrode forming mask pattern corresponding to the single drain structure forming region 1503 has a pattern configuration in which the auxiliary pattern is not provided. As a result, in the post-development resist patterns 1105 and 1106 in the GOLD structure forming region 1501 and the LDD structure forming region 1502, a tapered region in which the resist film thickness gradually decreases toward the end is formed, and the single drain structure is formed. Area 1503
The tapered region does not exist in the post-development resist pattern 1107, and a rectangular post-development resist pattern 1107 is formed (FIG. 11-A).

The GOLD structure forming region 1501 and the LD
The resist film thickness of the tapered regions of the post-development resist patterns 1105 and 1106 in the D structure forming region 1502 becomes thinner as approaching the end of the tapered region, and the resist film is provided on the corresponding mask pattern. It can be set freely by appropriately adjusting the transmittance of the auxiliary pattern area. Then, the post-development resist pattern 110 is taken into consideration in consideration of the remaining etching thickness of the tapered region of the gate electrode formed in the first dry etching process and the second dry etching process, which are later processes.
5, 1106 of the tapered region are formed with an appropriate resist film thickness. The GOLD structure forming region 150
1 and the dimensions of the tapered regions of the post-development resist patterns 1105 and 1106 in the LDD structure forming region 1502 are freely set by adjusting the dimensions of the auxiliary pattern regions provided in the corresponding mask patterns. It is possible. And the resist pattern 11 after development
The tapered regions 05 and 1106 are formed in consideration of the dimensions of each low-concentration impurity region (n-region) in a GOLD structure and an LDD structure transistor to be finally formed.
It is formed to an appropriate length.

In this embodiment, the GOLD structure forming region 1
The resist film thickness in the tapered regions of the developed resist patterns 1105 and 1106 in the LDD structure formation region 1502 and the LDD structure formation region 1502 are equal, and the GOLD structure formation region 1
Compared to the case of the post-developed resist pattern 1105 of 501, the case where the tapered region in the post-developed resist pattern 1106 of the LDD structure forming region 1502 is smaller in size is illustrated (FIG. 11-A).

Next, a first dry etching process is performed. By the dry etching process for this predetermined time, GO
LD structure forming region 1501 and LDD structure forming region 150
In No. 2, gate electrodes 1111 and 1112 having a tapered region having a structure in which the thickness of the gate electrode is reduced toward the end of the gate electrode are formed. At this time, dry etching is performed so that the remaining film thickness of the tapered regions of the gate electrodes 1111 and 1112 becomes a predetermined film thickness of about 5 to 30% of the initial film thickness. In one single drain structure formation region 1503, a rectangular gate electrode 1113 is formed. Note that the resist patterns used as the masks for the dry etching are the resist patterns 1108, 1109, and 11 after the dry etching, respectively, based on the shapes of the resist patterns 1105, 1106, and 1107 after the development.
The shape has changed to 10. Also, the gate electrode 111
The shape of the gate insulating film in the region exposed from 1, 1112, and 1113 has been thinned by etching, and has changed to the shape of the gate insulating films 1114, 1115, and 1116 (FIG. 11B).

Next, the gate electrodes 1111, 111
High-concentration ion implantation of n-type impurities is performed using 2, 1113 as a mask. In the GOLD structure formation region 1501 and the LDD structure formation region 1502, the gate electrodes 1111, 11
High-concentration impurity regions (n + regions) 1117 and 1119 serving as source and drain regions are formed in a polycrystalline silicon film 1102 corresponding to the outside of the polycrystalline silicon film 12, and the polycrystalline silicon corresponding to the tapered region having a small gate electrode film thickness. A low concentration impurity region (n− region) 1118, 1
120 are formed. Single drain structure formation region 1
In 503, only a high-concentration impurity region (n + region) 1121 serving as a source and drain region is formed in the polycrystalline silicon film 1102 corresponding to the outside of the gate electrode 1113 (FIG. 11-B).

Next, a second dry etching process is performed. By the dry etching process for this predetermined time, GO
In the LD structure formation region 1501, the gate electrode 11
11 is dry-etched, the thickness of the gate electrode in the tapered region is further reduced, and the gate electrode 1111 which is the end of the tapered region.
Is receded, and a gate electrode 1122 is formed. The low-concentration impurity region (n− region) 1118 is overlapped with the gate electrode 1122 in the Lov region 1.
Loff area 111 which does not overlap with 118a
8b. The tapered region of the gate electrode 1112 in the LDD structure forming region 1502 is also GO
Dry etching is performed in the same manner as in the case of the LD structure formation region 1501, and a gate electrode 1123 having a tapered region as an etching remaining film is formed. On the other hand, the gate electrode 11 in the single drain structure formation region 1503
Similarly, a dry etching process is performed on the gate electrode 13 to form the gate electrode 1124. However, since the gate electrode 1113 has a rectangular shape, the underlying gate insulating film 1116 is further etched and becomes thinner. Thereafter, an unnecessary resist pattern serving as a dry etching mask for the gate electrodes 1122, 1123, and 1124 is removed (FIG. 11C). Of course, an unnecessary resist pattern may be removed before the high-concentration ion implantation.

Next, since the tapered region, which is the remaining film of the gate electrode 1123 in the LDD structure forming region 1502, remains, it is necessary to selectively remove the tapered region. Therefore, new resist patterns 1125 to 1127 are formed so as to open only the LDD structure formation region 1502 (FIG. 11D).

Next, a third dry etching process is performed. By the dry etching process for this predetermined time, LD
The tapered region of the gate electrode 1123 in the D structure forming region 1502 is selectively etched away,
A rectangular gate electrode 1128 is formed. As a result, the low-concentration impurity region (n− region) 1120 formed in the polycrystalline silicon film and the gate electrode 1128 do not overlap, and an LDD transistor is formed. Thereafter, the resist patterns 1125 to 1127, which are dry etching masks, are removed (FIG. 11-E).

The method of forming a polycrystalline silicon TFT having a GOLD structure, an LDD structure, and a single drain structure has been described above. , 905, and 910 can of course be applied to the formation of a MOS transistor having the same structure using a semiconductor substrate such as a silicon substrate. In this case, the high concentration impurity region (n + region) and the low concentration impurity region (n− region) are formed on a semiconductor substrate such as a silicon substrate.

By the above manufacturing process, GOLD
A thin film transistor having a structure, an LDD structure, and a single drain structure can be separately formed.

(Embodiment 5) In Embodiment 5, in a method of separately forming a GOLD structure, an LDD structure, and a single drain structure thin film transistor for each circuit, an LDD
A process for forming a resist pattern for opening only the structure forming region 1502 and a process for simplifying the process that does not require the third dry etching process will be described with reference to FIG.

The substrate structure used in this embodiment is such that a polycrystalline silicon film 1202 having a predetermined thickness is formed on a glass substrate 1201.
A substrate having a structure in which a gate insulating film 1203 having a predetermined thickness and a gate electrode film 1204 having a predetermined thickness are stacked is used. Photomask or reticle 9 for forming a gate electrode, on which a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function, which is formed of a semi-permeable film, is provided on a substrate having the above structure.
A photolithography process using 01, 905, 910 (FIGS. 9A, 9B, 9D) is performed to form resist patterns 1205, 1206, 1207 after development.

At this time, in the gate electrode forming photomask or reticle 901, 905, 910 to be applied, the gate electrode forming mask pattern corresponding to the GOLD structure forming region 1501 and the LDD structure forming region 1502 has light intensity. Install an auxiliary pattern with a reduction function,
The gate electrode forming mask pattern corresponding to the single drain structure forming region 1503 has a pattern configuration in which the auxiliary pattern is not provided. As a result, in the developed resist patterns 1205 and 1206 in the GOLD structure forming region 1501 and the LDD structure forming region 1502, a tapered region in which the resist film thickness gradually decreases toward the end is formed, and the single drain structure is formed. Forming area 150
In the third developed resist pattern 1207, the tapered region does not exist, and a rectangular shaped developed resist pattern 1207 is formed (FIG. 12A).

In the present embodiment, after the second dry etching process, the GOLD structure forming region 1501 is formed so that the tapered region which is an etching residual film does not remain in the gate electrode of the LDD structure forming region 1502. LD pattern compared with resist pattern 1205 after development
The configuration is such that the resist film thickness in the tapered region of the post-development resist pattern 1206 in the D structure formation region 1502 is relatively thin (FIG. 12-A).

Next, a first dry etching process is performed. By the dry etching process for this predetermined time, GO
LD structure forming region 1501 and LDD structure forming region 150
In No. 2, gate electrodes 1211 and 1212 having a tapered region having a structure in which the thickness of the gate electrode becomes thinner toward the end of the gate electrode are formed. At this time, GOL
D structure formation region 1501 and LDD structure formation region 1502
The remaining film thickness of the tapered region in the gate electrodes 1211 and 1212 is dry-etched to a predetermined thickness of about 5 to 30% of the initial film thickness. The remaining film thickness in the shape region is
It is relatively thinner than the gate electrode 1211.
In one single drain structure forming region 1503, a rectangular gate electrode 1213 is formed. still,
The resist pattern used as a mask for dry etching is the resist pattern 1205, 1206, 12
07, the shapes of the resist patterns 1208, 1209, and 1210 are changed after dry etching. In addition, the shape of the gate insulating film in a region exposed from the gate electrodes 1211, 1212, and 1213 is thinned by etching.
15 and 1216 (FIG. 12-B).

Next, the gate electrodes 1211, 121
High-concentration ion implantation of n-type impurities is performed using masks 2 and 1213 as masks. In the GOLD structure formation region 1501 and the LDD structure formation region 1502, the gate electrodes 1211, 12
High-concentration impurity regions (n + regions) 1217 and 1219 serving as source and drain regions are formed in a polycrystalline silicon film 1202 corresponding to the outside of the polycrystalline silicon film 12, and the polycrystalline silicon corresponding to the tapered region having a thin gate electrode film. A low concentration impurity region (n− region) 1218,1
220 is formed. Single drain structure formation region 1
In 503, only a high-concentration impurity region (n + region) 1221 serving as a source and drain region is formed in the polycrystalline silicon film 1202 corresponding to the outside of the gate electrode 1213 (FIG. 12-B).

Next, a second dry etching process is performed. By the dry etching process for this predetermined time, GO
In the LD structure formation region 1501, the gate electrode 12
11 is dry-etched, the thickness of the gate electrode in the tapered region is further reduced, and the gate electrode 1211 which is the end of the tapered region.
Is receded, and a gate electrode 1222 is formed. The low-concentration impurity region (n− region) 1218 overlaps the gate electrode 1222 with the Lov region 1.
Loff area 121 not overlapping with 218a
8b. In the case of the LDD structure formation region 1502, the remaining thickness of the tapered region of the gate electrode 1212 is relatively small after the first dry etching process. This is completely removed by etching to form a rectangular gate electrode 1223. This gate electrode 122
Reference numeral 3 has a structure not overlapping with the low-concentration impurity region (n-region) 1220, and an LDD structure transistor is formed. On the other hand, the gate electrode 1213 in the single drain structure formation region 1503 is similarly subjected to dry etching to form the gate electrode 1224. Since the gate electrode 1213 has a rectangular shape, the underlying gate insulating film 1216 is It is only further etched and thinned. Thereafter, the gate electrodes 1222 and 122
The resist pattern which is the dry etching mask 31224 is removed (FIG. 12C). Of course, the resist pattern may be removed before the high-concentration ion implantation.

Through the above simplified manufacturing steps, thin film transistors having a GOLD structure, an LDD structure, and a single drain structure can be separately formed for each circuit.

The present invention described in the first to fifth embodiments will be described in more detail with reference to the following examples.

[0115]

(Embodiment 1) A photomask or reticle 101, 105, 110 provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function formed of a semi-permeable film.
(FIGS. 1A, 1B, and 1D) are applied to a photolithography process for forming a gate electrode, and the GOLD structure and L
FIG.
This will be described in detail with reference to FIGS. In the second embodiment, a method of separately forming a polycrystalline silicon TFT having a GOLD structure, an LDD structure, and a single drain structure has been described. A method for manufacturing a liquid crystal display composed of crystalline silicon TFTs will be described.

First, the circuit configuration of the entire liquid crystal display is shown in FIG. The liquid crystal display includes a pixel region 501 and peripheral circuits for driving the pixel region 501. Peripheral circuits include shift register circuits 502 and 506, level shifter circuits 503 and 507, and buffer circuit 50.
4, 508 and a sampling circuit 505. Shift register circuits 502 and 506 as peripheral circuits
And level shifter circuits 503 and 507 and buffer circuit 50
No. 4,508 describes a GO with excellent hot carrier countermeasure effect.
A polycrystalline silicon TFT having an LD structure is used. On the other hand, the pixel region 501 and a sampling circuit 505 which is a part of a peripheral circuit are provided with an LD having an excellent effect of suppressing an off-current value.
A polycrystalline silicon TFT having a D structure is used (FIG. 4).

A method for manufacturing a liquid crystal display having the above circuit configuration will be specifically described below with reference to FIGS.

First, the plasma C is placed on the glass substrate 601.
By a VD method, a first-layer silicon oxynitride film 602a and a second-layer silicon oxynitride film 602b having different composition ratios are deposited to a thickness of 50 nm and a second silicon oxynitride film 602b, respectively, to form a base film 602. The glass substrate 601 used here
Examples thereof include quartz glass, barium borosilicate glass, and aluminoborosilicate glass. Next, plasma CVD is performed on the base film 602 (602a and 602b).
After a 55 nm amorphous silicon film was deposited by the method, a nickel-containing solution was held on the amorphous silicon film. After dehydrogenating this amorphous silicon film (at 500 ° C. for 1 hour), thermal crystallization (at 550 ° C. for 4 hours) is performed.
Further, a polycrystalline silicon film was formed by laser annealing. Next, the polycrystalline silicon film was patterned by a photolithography step and an etching step to form semiconductor layers 603 to 607. At this time, the semiconductor layer 603
After forming 607, doping of an impurity element (boron or phosphorus) for controlling Vth of the TFT may be performed. Next, a gate insulating film 608 made of a 110-nm-thick silicon oxynitride film is formed by a plasma CVD method so as to cover the semiconductor layers 603 to 607, and a gate electrode film made of a 400-nm-thick TaN film is formed on the gate insulating film 608. 609 was deposited by a sputtering method (FIG. 5).
(A)).

Next, a photomask or reticle 101, 105, 110 (FIG. 1) provided with a diffraction grating pattern composed of lines and spaces having a function of reducing the transmittance of exposure light or an auxiliary pattern composed of a semi-permeable film.
(A), (B), and (D)) are applied to a photolithography process for forming a gate electrode, and the developed resist patterns 610a to 610a to 6g for forming a gate electrode having both sides thinned.
15a is formed (FIG. 5B).

Next, using the post-development resist patterns 610a to 615a for forming the gate electrode as a mask, a 400 nm-thick gate electrode film 609 made of a TaN film is dry-etched. The shape of the gate electrode after dry etching is a convex shape in which both ends are thinned, and the film thickness of the thin region is about 5 to 30% of the initial film thickness of 400 nm (preferably about 7 to 8%, about 30 nm). And gate electrodes 617 to 622 are formed. At this time, the shape of the resist pattern in the dry etching process is such that the post-development resist patterns 610a to 615a in which the resist film thickness at both end portions is formed are reduced from the post-development resist patterns 610a to 615a in which the regions having a small resist film thickness disappear. The shape has changed to patterns 610b to 615b.
Further, the gate insulating film 608 made of the silicon oxynitride film in a region exposed from the gate electrodes 617 to 622 has a gate insulating film 61 thinned by dry etching.
It has changed to 6.

Next, low-concentration ion implantation of an n-type impurity, which is a first ion implantation process, is performed without removing the resist patterns 610b to 615b after the dry etching, so as to correspond to the regions exposed from the gate electrodes 617 to 622. Low-concentration impurity regions (n-regions) 62 in the semiconductor layers 603 to 607
3 to 627 are formed. The ion implantation conditions at this time are phosphorus (P) as an n-type impurity, and the dose amount is 3 × 10 4.
^{12 to} 3 × 10 ¹³ atoms / cm ² and acceleration voltage of 60 to 100
Processing was performed under the condition of kV (FIG. 6 (A)).

Next, the resist patterns 610b to 615b are removed after the dry etching. After this, the pixel TFT
In order to form the LDD structure 704, a resist pattern 628 serving as a mask for the second ion implantation treatment is formed so as to cover the gate electrode 620 existing in the region. Of course, before the low-concentration ion implantation, the resist pattern 6
10b to 615b may be removed.

Then, high-concentration ion implantation of an n-type impurity, which is a second ion implantation process, is performed. As the ion implantation conditions, the dose amount is 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm.
^{In 2} , ions are implanted under the conditions of an acceleration voltage of 60 to 100 kV.

At this time, the pixel region 7 in the LDD structure forming region
In the region of the pixel TFT 704 which is 07, the resist pattern 628 covering the gate electrode 620 is ion-implanted using the resist pattern 628 as a mask.
A high-concentration impurity region (n + region) 632 serving as a source and a drain region is formed in the semiconductor layer 606 corresponding to the region exposed from. In the semiconductor layer 606 corresponding to a region outside the gate electrode 620 and inside the resist pattern 628, a low-concentration impurity region (n− region) 626 has already been formed by the first ion implantation process, and the second ion implantation is performed. Along with the formation of the high-concentration impurity region (n + region) 632 by the ion implantation process, an LDD-structure polycrystalline silicon TFT is formed.

On the other hand, in the driving circuit 706 of the peripheral circuit, which is the GOLD structure forming region, the gate electrodes 617 to 6
By performing ion implantation using mask 19 as a mask, high-concentration impurity regions (n + regions) 629 to 631 serving as source and drain regions are formed in semiconductor layers 603 to 605 corresponding to regions exposed from gate electrodes 617 to 619. At the same time, low-concentration impurity regions (n-regions) 634 are formed in the semiconductor layers 603 to 605 corresponding to the thinned regions of the gate electrode film existing on both sides of the gate electrodes 617 to 619.
To 636 are formed. Thus, the gate electrodes 617 to
In consideration of the difference in film thickness on both sides in 619, by appropriately selecting the acceleration voltage and the ion implantation amount during ion implantation, the high-concentration impurity regions (n + regions) 629 to 631 and the low-concentration impurity regions (n− Regions 634 to 636 can be formed at the same time to form a GOLD structure polycrystalline silicon TFT.

Note that, also in the storage capacitor 705 in the pixel region 707, the second ion implantation process is performed using the gate electrode 621 (more precisely, not the gate electrode but a mere electrode for the capacity forming region) as a mask. By utilizing the difference in the thickness of the gate electrode 621, the semiconductor layer 607 is provided with a high-concentration impurity region (n +
A region 633 and a low-concentration impurity region (n-region) 637 are formed at the same time, and a structure similar to the GOLD structure is formed. However, since the region is not a polycrystalline silicon TFT formation region, the structure is not a GOLD structure. (FIG. 6 (B)).

Next, by performing a new photolithography step, the p-channel type TF in the drive circuit 706 is formed.
Storage capacitor 705 in T702 region and pixel region 707
A resist opening is formed in a region, and the other region is patterned so as to be covered with resist patterns 638 to 640.

Using the resist patterns 638 to 640 as masks, high-concentration ion implantation of p-type impurities is performed as a third ion implantation process. At this time, the p-channel TFT 702
In the region, boron (B) which is an impurity element imparting a conductivity type opposite to the one conductivity type using the gate electrode 618 as a mask
A high-concentration impurity region (p + region) 64 serving as a source and drain region is formed in the semiconductor layer 604 corresponding to a region exposed from the gate electrode 618 by ion implantation of a p-type impurity such as
1 and a low-concentration impurity region (p− region) 64 in the semiconductor layer 604 corresponding to the thin region on both sides of the gate electrode 618.
3 is formed, and a GOLD structure polycrystalline silicon TFT is formed. In the third ion-implanted region, phosphorus (P) as an n-type impurity has already been ion-implanted by the first and second ion implantations, but the concentration of boron (B) as a p-type impurity is 2 × 10 3. ^Since ions are implanted so as to be ^{20 to} 2 × 10 ²¹ atoms / cm ³ , a p-channel type polycrystalline silicon TFT
Can function as source and drain regions.

The storage capacitor 705 region also has a corresponding semiconductor layer 60 as in the case of the p-channel TFT 702.
7, a high-concentration impurity region (n + region) 642 and a low-concentration impurity region (n− region) 644 are formed.
Although a structure similar to the LD structure is formed, it is not a GOLD structure because it is not a region where a polycrystalline silicon TFT is formed (FIG. 7A).

Next, the resist patterns 638 to 640 are used.
Is removed, a first interlayer insulating film 645 made of a 150-nm-thick silicon oxynitride film is deposited by a plasma CVD method. Further, in order to thermally activate each of the impurity elements implanted into the semiconductor layers 603 to 607, thermal annealing is performed at 550 ° C. for 4 hours. In this embodiment, the TFT
In order to reduce the off-current value and improve the field-effect mobility of the semiconductor layers 603 to 6
Nickel (N) used as a catalyst in the crystallization of
i) is an impurity region 629-6 containing a high concentration of phosphorus (P)
The gettering at 33 realizes a reduction in the concentration of nickel (Ni) in the semiconductor layer serving as a channel formation region. A polycrystalline silicon TFT having a channel formation region manufactured by such a method has good crystallinity and high field-effect mobility, and thus can exhibit favorable electric characteristics such as a decrease in off-current value. The thermal activation treatment may be performed before depositing the first interlayer insulating film 645. However, if the heat resistance of the wiring material of the gate electrodes 617 to 622 is weak, the thermal activation treatment may be performed as in this embodiment. It is preferable to perform a thermal activation process after depositing the insulating film. Next, a hydrogenation treatment for terminating dangling bonds in the semiconductor layers 603 to 607 is performed by performing a heat treatment at 410 ° C. for one hour in a nitrogen atmosphere containing 3% of hydrogen (FIG. 7).
(B)).

Next, a second interlayer insulating film 646, which is an organic insulating material made of an acrylic resin film having a thickness of 1.6 μm, is formed on the first interlayer insulating film 645 made of a silicon oxynitride film. After that, contact holes for connecting to the gate electrode 622 functioning as a source wiring and the impurity regions 629, 631, 632, 641, 642 which are the first and third ion-implanted regions are formed by a photolithography process and a dry etching process. (FIG. 8A).

Next, metal wirings 647 to 652 for electrically connecting to the respective impurity regions 629, 631, 641 in the driving circuit 706 are formed. The connection electrodes 653, 655, and 656 in the pixel portion 707 and the gate wiring 6
54 are formed simultaneously with the metal wirings 647 to 652.
In addition, as a metal wiring material, a 50 nm thick Ti film and a 50 nm thick
A laminated film of an Al-Ti alloy film having a thickness of 0 nm is applied.
The connection electrode 653 is for electrically connecting the gate electrode 622 functioning as a source wiring to the pixel TFT 704 via the impurity region 632. Connection electrode 655
Are electrically connected to the impurity region 632 of the pixel TFT 704, and the connection electrode 656 is electrically connected to the impurity region 642 of the storage capacitor 705. Gate wiring 654
Is for electrically connecting the plurality of gate electrodes 620 of the pixel TFT 704. Next, ITO (Indium-T
A transparent conductive film such as i-Oxide) is deposited to a thickness of 80 to 120 nm, and a pixel electrode 657 is formed by a photolithography process and an etching process. The pixel electrode 657 includes an impurity region 632 which is a drain region of the pixel TFT 704.
Are electrically connected to each other through the connection electrode 655, and further electrically connected to the impurity region 642 functioning as one electrode forming the storage capacitor 705 through the connection electrode 656 (FIG. 8B).

As described above, the n-channel TFT 70
1, p-channel TFT 702, n-channel TFT 7
03, and a liquid crystal display including a pixel region 707 having a pixel TFT 704 and a storage capacitor 705 can be manufactured.

(Example 2) A photomask or reticle 901, 905, 91 provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function composed of a semi-permeable film.
0 (FIGS. 9A, 9B, and 9D) are applied to a photolithography process for forming a gate electrode, and a method of manufacturing an active matrix liquid crystal display composed of a polycrystalline silicon TFT having a GOLD structure and an LDD structure is shown in FIG. ~ Figure 1
7 will be described in detail.

In this embodiment, after the second dry etching process, the gate electrode 1 in the LDD structure forming region is formed.
735 (FIG. 14-B) illustrates a case where a tapered region as an etching residual film remains, and a resist pattern formation for opening only an LDD structure formation region in the next step and a third dry etching The case where processing is necessary is described.

First, a first silicon oxynitride film 1702a having a different composition ratio and a second silicon oxynitride film 1702b each having a different composition ratio are formed on a glass substrate 1701 by plasma CVD at a thickness of 100 nm. Then, a base film 1702 is formed. Note that the glass substrate 1701 used here includes quartz glass, barium borosilicate glass, aluminoborosilicate glass, or the like. Next, after an amorphous silicon film having a thickness of 55 nm was deposited on the base film 1702 (1702a and 1702b) by a plasma CVD method, a nickel-containing solution was held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (5
After heat crystallization (at 550 ° C. for 4 hours), a polycrystalline silicon film was formed by laser annealing. Next, the polycrystalline silicon film was patterned by a photolithography step and an etching step to form semiconductor layers 1703 to 1707. At this time, after the formation of the semiconductor layers 1703 to 1707, an impurity element (boron or phosphorus) for controlling Vth of the TFT is used.
May be performed. Next, the semiconductor layer 17
03-1707 by plasma-enhanced CVD so as to cover
A gate insulating film 1708 made of a silicon oxynitride film having a thickness of 10 nm is formed, and a gate insulating film 1708 is formed on the gate insulating film 1708.
A gate electrode film 1709 made of a TaN film having a thickness of 0 nm was deposited by a sputtering method (FIG. 13-A).

Next, a photomask or a reticle provided with a diffraction grating pattern composed of lines and spaces having a function of reducing the light intensity of exposure light or an auxiliary pattern composed of a semi-permeable film is used for photolithography for forming a gate electrode. Applying to the process, the resist pattern 171 after development
0a to 1713a are formed (FIG. 13-B). Further, the resist patterns 1714a and 1715a are formed using a photomask or a reticle in which an auxiliary pattern is not provided.

At this time, the area of the drive circuit 1806 is GOL
D corresponds to the D structure formation region, and the pixel T in the pixel region 1807
Since the region of the FT 1804 corresponds to the LDD structure forming region, an auxiliary pattern having a light intensity reducing function is provided in a corresponding mask pattern in the gate electrode forming photomask or reticle to be applied. Further, in the pixel region 1807, the auxiliary pattern is not required to be provided in the mask pattern corresponding to the electrode pattern functioning simply as an electrode, so that the auxiliary pattern is not provided. As a result, G
Post-development resist pattern 1710 in OLD structure forming region
In the post-development resist pattern 1713a in the regions a to 1712a and the LDD structure forming region, a tapered region in which the resist film thickness gradually decreases as approaching the end is formed.
The resist pattern 1 after development in the GOLD structure forming region
The dimensions of the tapered region in the post-development resist pattern 1713a in the 710a to 1712a and the LDD structure forming region are determined by the GOLD structure and L
The lightly doped region (n-
By adjusting the size of the auxiliary pattern region of the mask pattern in consideration of the size of the region, the mask pattern is formed to have an appropriate length. In this embodiment, the post-development resist pattern 17 in the LDD structure formation region is compared with the post-development resist pattern 1710a to 1712a in the GOLD structure formation region.
The case where the dimension of the tapered region in 13a is small is illustrated. One of the developed resist patterns 1
Since 714a to 1715a are resist patterns for simply forming electrodes, the tapered region does not exist and a rectangular resist pattern is formed (FIG. 13).
-B).

Next, the post-development resist pattern 1710
A first dry etching process is performed using masks a to 1715a. The resist pattern 1 after development in the GOLD structure forming region is obtained by the dry etching process for the predetermined time.
As a result of etching using the resist pattern 1713a after development of the regions 710a to 1712a and the LDD structure forming region as a mask, the gate electrodes 1717 to 1720 having a tapered region having a structure in which the gate electrode becomes thinner toward the end of the gate electrode are formed. It is formed. At this time, the remaining film thickness of the tapered region of the gate electrodes 1717 to 1720 is about 5 to 30% of the initial film thickness of 400 nm (preferably 7 to 8%).
%, About 30 nm). One rectangular post-development resist pattern 1714
As a result of dry etching using a to 1715a as a mask, rectangular electrodes 1721 to 1722 are formed.
The shape of the resist pattern in the dry etching process is determined by the post-development resist patterns 1710a to 1715a.
a after dry etching resist pattern 1710b
~ 1515b. Further, the gate insulating film 1708 made of the silicon oxynitride film in a region exposed from the gate electrodes 1717 to 1720 and the electrodes 1721 to 1722 has been changed to a gate insulating film 1716 thinned by dry etching (FIG. 14-). A).

Next, the gate electrodes 1717 to 1720 and
First ion implantation using electrodes 1721 to 1722 as a mask
A high concentration ion implantation of an n-type impurity, which is a process, is performed. Semiconduct
In the body layers 1703 to 1705, the GOLD structure formation region
Region corresponding to the region outside the gate electrodes 1717 to 1719
High-concentration impurity regions that become source and drain regions in the region
(N + region) 1723 to 1725 are formed, and
In a region corresponding to the tapered region having a very small thickness
Are low-concentration impurity regions (n-regions) 1728 to 1730
Is formed. In the semiconductor layer 1706, LD
Corresponding to the outside of the gate electrode 1720 in the D structure formation region
High-concentration impurity regions that serve as source and drain regions
(N + region) 1726 is formed, and the gate electrode is thin.
Area corresponding to the tapered area,
A pure region (n-region) 1731 is formed. On the other hand,
In the semiconductor layer 1707 which is a region of the capacitance 1805
Therefore, the region corresponding to the outside of the electrode 1721 has a high impurity concentration.
Only the object region (n + region) 1727 is formed. this
At this time, phosphorus (P) is used as an ion implantation condition as an n-type impurity.
The dose is 5 × 10¹⁴~ 5 × 10^Fifteenatoms / cm^Twoas well as
The processing was performed under the conditions of an acceleration voltage of 60 to 100 kV. Also note
The actual impurity concentration to be introduced is a high concentration impurity region (n +
1 × 10 in 1723-1726²⁰~ 1 × 10^{twenty two}at
oms / cm^ThreeDegree, low concentration impurity region (n-region) 1728
1 × 10 for ~ 1731¹⁸~ 1 × 10¹⁹atoms / cm ^ThreeAbout
(FIG. 14-A).

Next, a second dry etching process is performed. By the dry etching process for this predetermined time, GO
Gate electrodes 1717 to 171 in LD structure forming region
The tapered region at the end of No. 9 is etched, the remaining film thickness of the tapered region is further reduced, the end of the tapered region is receded, and the gate electrodes 1732 to 1732 are removed.
1734 is formed. The low-concentration impurity regions (n-regions) 1728 to 1730 are connected to the gate electrode 173.
Lov region 172 overlapping with 2-1734
8a to 1730a are divided into Loff areas 1728b to 1730b which do not overlap with each other. The tapered region of the gate electrode 1720 in the LDD structure forming region is also dry-etched as in the case of the GOLD structure forming region, and a gate electrode 1735 having a tapered region that is an etching remaining film is formed. Similarly, dry etching is performed on the rectangular electrodes 1721 to 1722 to form the electrodes 1736 to 1737, but no significant change in the shape of the electrodes is observed. After this,
Gate electrodes 1732 to 1735 and electrodes 1736 to 17
Unnecessary resist patterns which are the 37 dry etching masks are removed (FIG. 14-B). Of course, an unnecessary resist pattern may be removed before the high-concentration ion implantation.

Next, since the tapered region which is the remaining film of the etching of the gate electrode 1735 in the LDD structure forming region remains, it is necessary to selectively remove the tapered region. Therefore, a new resist pattern 1739 to 1739 is formed so as to open only the LDD structure forming region.
1742 is formed (FIG. 15-A).

Next, a third dry etching process is performed. By the dry etching process for this predetermined time, LD
The tapered region of the gate electrode 1735 in the D structure formation region is selectively etched away to form a rectangular gate electrode 1743. As a result, the low concentration impurity region (n-region) formed in the semiconductor layer 1706
1731 and the gate electrode 1743 do not overlap each other, and an LDD transistor is formed. Thereafter, the resist patterns 1739 to 1742 which are dry etching masks are removed (FIG. 15-).
B).

Next, a new photolithography process for opening a resist in the region of the p-channel type TFT 1802 in the driving circuit 1806 and the region of the storage capacitor 1805 in the pixel region 1807 is performed to form resist patterns 1744 to 1746. It is formed (FIG. 16-A).

The resist patterns 1744 to 1746
Is used as a mask, high-concentration ion implantation of p-type impurities as a second ion implantation process is performed. At this time, a p-channel TFT
In a region 1802, boron (B) or the like, which is a p-type impurity of an impurity element imparting a conductivity type opposite to the one conductivity type, is ion-implanted using the gate electrode 1733 as a mask. Then, in the semiconductor layer 1704, a high-concentration impurity region (p + region) 1747 serving as a source and a drain region is formed in a region corresponding to the outside of the gate electrode 1733, and the gate electrode film at the end of the gate electrode 1733 is thin. The low concentration impurity region (p-
A region 1748 is formed. Although phosphorus (P) as an n-type impurity has already been ion-implanted into the second ion-implanted region by the first ion implantation, the concentration of boron (B) as a p-type impurity is 2 × 10 ^20. ~ 2 × 10 ²¹ atoms /
Since ions are implanted at a high concentration so as to become cm ³ , it can function as the source and drain regions of the p-channel TFT 1802. Note that also in the semiconductor layer 1707 where the storage capacitor 1805 is formed, the high-concentration impurity region (p + region) 17 is formed in a region corresponding to the outside of the electrode 1736.
49 are formed, and the p of a single drain structure is structurally formed.
Although a structure similar to that of the channel-type polycrystalline silicon TFT is formed, it is not a single-drain polycrystalline silicon TFT because the region functions as a storage capacitor 1805 (FIG. 16A).

Next, the resist patterns 1744 to 1744
After removing 46, 150 nm by plasma CVD method.
First interlayer insulating film 17 made of a thick silicon oxynitride film
Deposit 50. Further, the semiconductor layers 1703 to 1707
In order to thermally activate the impurity elements (n-type impurities and p-type impurities) implanted into the semiconductor substrate, thermal annealing is performed at 550 ° C. for 4 hours. Note that in this embodiment, at the same time as the thermal activation treatment of the impurity element, nickel (a catalyst used when crystallizing the semiconductor layers 1703 to 1707 for the purpose of lowering the off-current value and improving the field-effect mobility) was used. Ni) in the impurity region 1
Gettering is performed with a high concentration of phosphorus (P) contained in 723 to 1727. With this gettering process,
Nickel (Ni) in a semiconductor layer to be a channel formation region
A reduction in concentration has been achieved. A polycrystalline silicon TFT having a channel formation region manufactured by this method has good crystallinity, has high field-effect mobility, and can exhibit good electric characteristics such as a decrease in off-current value. The thermal activation treatment may be performed before depositing the first interlayer insulating film 1750, but the gate electrodes 1732 to 1734, 1
When the heat resistance of the wiring material of the electrode 743 and the electrodes 1736 to 1737 is weak, it is preferable to perform the thermal activation treatment after depositing the interlayer insulating film as in this embodiment. Then 3% hydrogen
Dangling bonds of the semiconductor layers 1703 to 1707 are terminated by performing hydrogenation treatment at 410 ° C. for 1 hour in a nitrogen atmosphere containing the dangling bonds (FIG. 16-B).

Next, a second interlayer insulating film 1751 made of an organic insulating material made of an acrylic resin film having a thickness of 1.6 μm is formed on the first interlayer insulating film 1750 made of a silicon oxynitride film. After that, a contact hole is formed in the second interlayer insulating film 1751 by photolithography and dry etching. At this time, the contact hole is formed between the electrode 1737 functioning as a source wiring and the impurity regions 1723, 1725, 1726, 1747, 174.
9 (FIG. 17-A).

Next, the impurity region 17 of the driving circuit 1806
23, 1725, and 1747 are formed with metal wirings 1752 to 1775 for electrical connection. The connection electrodes 1758, 1760, and 1761 of the pixel area 1807 and the gate wiring 175 are simultaneously formed at the same time as the metal wirings 1752-1775.
9 is formed. The metal wiring material is a 50 nm thick Ti.
It is composed of a laminated film of a film and a 500 nm thick Al-Ti alloy film. The connection electrode 1758 is formed to electrically connect the electrode 1737 functioning as a source wiring to the pixel TFT 1804 through the impurity region 1726. The connection electrode 1760 is electrically connected to the impurity region 1726 of the pixel TFT 1804.
Reference numeral 61 is electrically connected to the impurity region 1749 of the storage capacitor 1805. The gate wiring 1759 is a pixel TFT
It is formed to electrically connect a plurality of gate electrodes 1743 of 1804. Next, ITO (Indium-Ti-Oxid
e) A transparent conductive film such as e) is deposited to a thickness of 80 to 120 nm, and is subjected to a photolithography process and an etching process.
A pixel electrode 1762 is formed. The pixel electrode 1762 is electrically connected to an impurity region 1726 which is a source / drain region of the pixel TFT 1804 via a connection electrode 1760, and is electrically connected to an impurity region 1749 of the storage capacitor 1805 via the connection electrode 1761. (FIG. 17-B).

Through the above manufacturing steps, the n-channel type TF
A driver circuit 1806 including a T1801, a p-channel TFT 1802, and an n-channel TFT 1803;
A liquid crystal display including a pixel region 1807 including a pixel TFT 1804 and a storage capacitor 1805 can be manufactured.

(Embodiment 3) By applying the present invention, various electro-optical devices (active matrix liquid crystal display device, active matrix light emitting device, active matrix EC display device) can be manufactured. That is, the invention can be applied to various electronic apparatuses in which these electro-optical devices are incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head-mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). Examples of these are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which includes a main body 3001, an image input section 3002, and a display section 30.
03, a keyboard 3004 and the like. Display unit 3 of the present invention
003 can be applied.

FIG. 18B shows a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, and an image receiving portion 310.
6 and so on. The present invention can be applied to the display portion 3102.

FIG. 18C shows a mobile computer (mobile computer), which includes a main body 3201, a camera section 3202, an image receiving section 3203, operation switches 3204, a display section 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 18D shows a goggle type display, which includes a main body 3301, a display section 3302, and an arm section 330.
3 and so on. The present invention can be applied to the display portion 3302.

FIG. 18E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, and a speaker portion 340.
3, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3402.

FIG. 18F shows a digital camera, which includes a main body 3501, a display section 3502, an eyepiece section 3503, operation switches 3504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 3502.

FIG. 19A shows a front type projector, which includes a projection device 3601, a screen 3602, and the like. The present invention can be applied to the liquid crystal display device 3808 forming a part of the projection device 3601 and other driving circuits.

FIG. 19B shows a rear projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3, including a screen 3704 and the like. The present invention provides a projection device 3
The present invention can be applied to a liquid crystal display device 3808 which constitutes a part of the LCD 702 and other driving circuits.

FIG. 19C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 19A and 19B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In this embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 19D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 19C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 19D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 19, a case where a transmissive electro-optical device is used is shown, and an application example of a reflective electro-optical device and a light emitting device is not shown.

FIG. 20A shows a mobile phone, and the main body 39 is provided.
01, audio output unit 3902, audio input unit 3903, display unit 3904, operation switch 3905, antenna 3906
And so on. The present invention can be applied to the display portion 3904.

FIG. 20B shows a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, and an antenna 4006.
And so on. The present invention can be applied to the display portions 4002 and 4003.

FIG. 20C shows a display, which includes a main body 4101, a support 4102, a display portion 4103, and the like.
The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus of this embodiment can be realized by using any combination of the first to fifth embodiments and the first and second embodiments.

[0167]

According to the present invention, a photomask or a reticle for forming a gate electrode, in which an auxiliary pattern having a light intensity reducing function is provided in a mask pattern, is applied to a photolithography process. In this case, a semiconductor device comprising a GOLD structure transistor can be manufactured, which is extremely effective for improving the performance of the semiconductor device and reducing the manufacturing cost.

In the manufacture of the GOLD structure transistor, the size of the auxiliary pattern having the light intensity reducing function provided on the mask pattern can be set to an arbitrary length. The region in the channel direction can be formed to have an arbitrary length, which is extremely effective for improving the performance of the GOLD structure transistor.

In the manufacture of a semiconductor device using the photomask or reticle for forming a gate electrode,
By changing the process from the ion implantation step, an LDD structure having a large effect of suppressing an off-current value, a GOLD structure transistor having a large effect against hot carriers, and a transistor having a single drain structure can be formed separately for each circuit. This is extremely effective in reducing the cost and improving the performance.

In the manufacture of a semiconductor device using the photomask or reticle for forming a gate electrode,
By providing an auxiliary pattern having a light intensity reducing function on an arbitrary mask pattern, a transistor having a single drain structure, a GOLD structure, and a transistor having an LDD structure can be separately formed for each circuit of the semiconductor device. It is extremely effective for improvement.

[Brief description of the drawings]

FIG. 1 shows a mask pattern configuration of a gate electrode forming photomask or reticle provided with a diffraction grating pattern or an auxiliary pattern having a light intensity reducing function formed of a semi-permeable film.

FIG. 2 shows a method of forming a GOLD structure polycrystalline silicon TFT using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

FIG. 3 shows a method of forming a GOLD structure, an LDD structure, and a single drain structure polycrystalline silicon TFT using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

FIG. 4 is a circuit configuration of the entire liquid crystal display.

FIG. 5 shows a liquid crystal display manufacturing method (1) using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

FIG. 6 shows a liquid crystal display manufacturing method (2) using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

FIG. 7 shows a method of manufacturing a liquid crystal display using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (3).

FIG. 8 shows a method of manufacturing a liquid crystal display using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (4).

FIG. 9 shows a mask pattern configuration of a gate electrode forming photomask or a reticle provided with an auxiliary pattern having a light intensity reducing function.

FIG. 10 illustrates a method for forming a GOLD structure polycrystalline silicon TFT using a photomask or reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

FIG. 11 shows a method of forming a GOLD structure, an LDD structure, and a single drain structure polycrystalline silicon TFT using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

FIG. 12 shows a method of forming a GOLD structure, an LDD structure, and a single-drain structure polycrystalline silicon TFT using a photomask or reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (simple process).

FIG. 13 shows a method of manufacturing a liquid crystal display using a photomask or reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (1).

FIG. 14 shows a method of manufacturing a liquid crystal display using a photomask or reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (2).

FIG. 15 shows a method of manufacturing a liquid crystal display using a photomask or reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (3).

FIG. 16 shows a method of manufacturing a liquid crystal display using a photomask or reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function (4).

FIG. 17 shows a liquid crystal display manufacturing method (5) in which a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function is applied.

FIG. 18 illustrates an example of a semiconductor device.

FIG. 19 illustrates an example of a semiconductor device.

FIG. 20 illustrates an example of a semiconductor device.

FIG. 21 shows a method of forming a GOLD structure, an LDD structure, and a single drain structure polycrystalline silicon TFT using a photomask or a reticle for forming a gate electrode provided with an auxiliary pattern having a light intensity reducing function.

[Explanation of symbols]

101: Photomask or reticle for forming gate electrode 102: Shielding part 103: Slit part (diffraction grating pattern) 104: Transparent part 105: Photomask or reticle for forming gate electrode 106: Shielding part 107: Slit part (diffraction grating pattern) 108: light transmitting portion 109: light intensity distribution 110: photomask or reticle for forming a gate electrode 111: light shielding portion 112: semi-light transmitting portion (semi-transmitting film) 113: light transmitting portion 114: light intensity distribution 201: glass substrate 202: Polycrystalline silicon film 203a: Gate insulating film (silicon oxynitride film) 203b: Gate insulating film (silicon oxynitride film) 204a: Gate electrode film 204b: Gate electrode 205a: Resist pattern after development 205b: Resist pattern after dry etching 206: high concentration impurity region (n + region) 207: low concentration impurity region (n− region) 301: glass substrate 302: polycrystalline silicon film 303: gate insulation Film (silicon oxynitride film) 304: gate electrode film 305: resist pattern after development 306: resist pattern after development 307: resist pattern after dry etching 308: gate electrode 309: gate insulating film (silicon oxynitride film) 310: dry etching Post-resist pattern 311: gate electrode 312: gate insulating film (silicon oxynitride film) 313: low-concentration impurity region (n-region) 314: low-concentration impurity region (n-region) 315: resist pattern 316: high-concentration impurity region (N + region) 317: low concentration impurity region (n− region) 318: high concentration impurity region (n + region) 319: low concentration impurity region (n− region) 320: high concentration impurity region (n + region) 401: GOLD structure Forming region 402: LDD structure forming region 403: Single drain structure forming region 501: Pixel region 502: Shift register circuit 503: Lucifer circuit 504: Buffer circuit 505: Sampling circuit 506: Shift register circuit 507: Level shifter circuit 508: Buffer circuit 601: Glass substrate 602: Base film 602a: First-layer silicon oxynitride film 602b: Second-layer oxidation Silicon nitride films 603 to 607: semiconductor layer 608: gate insulating film (silicon oxynitride film) 609: gate electrode film (TaN film) 610a to 615a: resist pattern after development 610b to 615b: resist pattern after dry etching 616: gate insulation Films 617-622: Gate electrodes 623-627: Low concentration impurity region (n-region) 628: Resist pattern 629-633: High concentration impurity region (n + region) 634-637: Low concentration impurity region (n-region) 638 640: resist pattern 641 to 642: high concentration impurity region (n + region) 643 to 644: low concentration impurity region (n− region) 645: first interlayer insulating film 646: Second interlayer insulating film (acrylic resin film) 647 to 652: Metal wiring 653: Connection electrode 654: Gate wiring 655 to 656: Connection electrode 657: Pixel electrode (ITO, etc.) 701: N channel Type TFT 702: p-channel type TFT 703: n-channel type TFT 704: pixel TFT 705: storage capacitor 706: drive circuit 707: pixel area 901: photomask or reticle for forming gate electrode 902: light shielding portion 903: slit portion (diffraction portion) Grating pattern) 904: Light transmitting portion 905: Photomask or reticle for forming gate electrode 906: Light shielding portion 907: Slit portion (diffraction grating pattern) 908: Light transmitting portion 909: Light intensity distribution 910: Photomask for forming gate electrode or Reticle 911: Shielding part 912: Semi-transmissive part (semi-transmissive film) 913: Translucent part 914: Light intensity distribution 1001: Glass substrate 1002: Polycrystalline silicon film 1003: Gate insulating film 1004: gate electrode film 1005: resist pattern after development 1006: resist pattern after dry etching 1007: gate electrode (after first dry etching) 1008: gate insulating film (after first dry etching) 1009: high concentration impurity Region (n + region) 1010: low concentration impurity region (n− region) 1010a: Lov region 1010b: Loff region 1011: gate electrode (after the second dry etching process) 1012: gate insulating film (after the second dry etching process) 1101: glass substrate 1102: polycrystalline silicon film 1103: gate insulating film 1104: gate electrode film 1105 to 1107: resist pattern after development 1108 to 1110: resist pattern after dry etching 1111 to 1113: gate electrode (first dry etching) 1114 to 1116: gate insulating film (after first dry etching) 1117: high concentration impurity region (n + 1118: Low concentration impurity region (n− region) 1118a: Lov region 1118b: Loff region 1119: High concentration impurity region (n + region) 1120: Low concentration impurity region (n− region) 1121: High concentration impurity region (n + region) Region) 1122 to 1124: Gate electrode (after second dry etching) 1125 to 1127: Resist pattern 1128: Gate electrode (after third dry etching) 1201: Glass substrate 1202: Polycrystalline silicon film 1203: Gate insulation Film 1204: Gate electrode film 1205 to 1207: Resist pattern after development 1208 to 1210: Resist pattern after dry etching 1211 to 1213: Gate electrode (after first dry etching) 1214 to 1216: Gate insulating film (First dry film) 1217: High concentration impurity region (n + region) 1218: Low concentration impurity region (n− region) 1218a: Lov region 1218b: Loff region 1219: High Concentration impurity region (n + region) 1220: Low concentration impurity region (n− region) 1221: High concentration impurity region (n + region) 1222 to 1224: Gate electrode (after second dry etching process) 1301: Glass substrate 1302: Many Crystal silicon film 1303: Gate insulating film (silicon oxynitride film) 1304: Gate electrode film 1305: Resist pattern after development 1306: Resist pattern after development 1307: Resist pattern after dry etching 1308: Gate electrode 1309: Gate insulating film (oxynitride nitride) 1310: resist pattern after dry etching 1311: gate electrode 1312: gate insulating film (silicon oxynitride film) 1313: low concentration impurity region (n-region) 1314: low concentration impurity region (n-region) 1315: resist Pattern 1316: High concentration impurity region (n + region) 1317: Low concentration impurity region (n− region) 1318: High concentration impurity Region (n + region) 1319: Low concentration impurity region (n− region) 1320: High concentration impurity region (n + region) 1401: GOLD structure formation region 1402: LDD structure formation region 1403: Single drain structure formation region 1501: GOLD structure formation Region 1502: LDD structure formation region 1503: Single drain structure formation region 1701: Glass substrate 1702: Base film 1702a: First layer of silicon oxynitride film 1702b: Second layer of silicon oxynitride film 1703 to 1707: Semiconductor layer (Polycrystalline silicon film) 1708: Gate insulating film (silicon oxynitride film) 1709: Gate electrode film (TaN film) 1710a to 1715a: Post-development resist pattern 1710b to 1715b: Dry etching resist pattern 1716: Gate insulating film (first 1717-1720: Gate electrode (after the first dry etching process) 1721-1722: Electrode (after the first etching process) 1723 to 1727: High-concentration impurity region (n + region) 1728 to 1731: Low-concentration impurity region (n- region) 1728a to 1730a: Lov region 1728b to 1730b: Loff region 1732 to 1735: Gate electrode (No. 2) 1736 to 1737: electrode (after the second dry etching) 1738: gate insulating film (after the second dry etching) 1739 to 1742: resist pattern 1743: gate electrode (the third dry) 1744 to 1746: resist pattern 1747: high concentration impurity region (p + region) 1748: low concentration impurity region (p− region) 1749: high concentration impurity region (p + region) 1750: first interlayer insulating film (after etching) 1751: Second interlayer insulating film (acrylic resin film) 1752 to 1757: Metal wiring 1758: Connection electrode 1759: Gate wiring 1760 to 1761: Connection electrode 1762: Pixel electrode (ITO, etc.) 1801: n-channel type TFT 1802: p-channel type TFT 1803: n-channel type TFT 1804: pixel TFT 1805: storage capacitor 1806: drive circuit 1807: a pixel region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 H01L 29/78 301L 5F140 29/786 301G 21/30 502P 502G F-term (Reference) 2H095 BB02 BC09 2H097 BB01 JA02 JA03 LA12 LA13 4M104 AA09 BB32 CC05 DD37 DD65 DD71 DD91 FF08 GG20 HH20 5F046 AA25 5F110 AA16 BB02 BB04 CC02 DD02 DD03 DD15 DD17 EE01 EE22 EE23 EE28 EE44 FF13 J04 FF12 GG13 GG12 GG12 HM15 NN03 NN04 NN22 NN27 NN35 NN73 NN78 PP01 PP03 PP10 PP29 PP34 PP35 QQ02 QQ04 QQ11 QQ24 QQ28 5F140 AA40 BA01 BB15 BD09 BE10 BF01 BF10 BF42 BG30 BG38 BH15 BJ07 BJ11 CC13 BK13 CC01 BK13 CC01

Claims (24)

[Claims] A first step of forming a conductive film on a semiconductor layer with an insulating film interposed therebetween; and a step of forming a conductive film on the conductive film from a central portion to an end portion by using a photomask or a reticle having a diffraction grating pattern. A second step of forming a resist pattern having a region with a small thickness, a third step of performing etching to form a gate electrode having a region with a small thickness at an end portion from a central portion, and Forming a first impurity region outside the gate electrode and a second impurity region overlapping a thin film region of the gate electrode by implanting an impurity element into the semiconductor layer using the mask as a mask. Process and
A method for manufacturing a semiconductor device, comprising: 2. A first step of forming a conductive film on a semiconductor substrate with an insulating film interposed therebetween, and using a photomask or a reticle having a diffraction grating pattern on the conductive film to move from a central portion to an end portion. A second step of forming a resist pattern having a region with a small thickness, a third step of performing etching to form a gate electrode having a region with a small thickness at an end portion from a central portion, and Forming a first impurity region outside the gate electrode and a second impurity region overlapping a thin film region of the gate electrode by implanting an impurity element into the semiconductor substrate using the mask as a mask. And a method of manufacturing a semiconductor device. 3. A first step of forming a conductive film on a first semiconductor layer and a second semiconductor layer with an insulating film interposed therebetween, and forming a rectangular shape on the conductive film above the first semiconductor layer. Forming a resist pattern, and using a photomask or a reticle having a diffraction grating pattern on the conductive film above the second semiconductor layer, using a photomask or reticle having a thinner region at an end portion than at a central portion. A second step of forming a pattern and dry etching to form a rectangular first gate electrode above the first semiconductor layer, and a central portion above the second semiconductor layer. A third step of forming a second gate electrode having a thinner region at the end,
Using the first gate electrode and the second gate electrode as a mask, an impurity element is implanted into the first semiconductor layer and the second semiconductor layer, and a first element is formed outside the first gate electrode. A fourth step of forming an impurity region and forming a second impurity region outside the second gate electrode and a third impurity region overlapping a thin region of the second gate electrode; A method for manufacturing a semiconductor device, comprising: 4. A first step of forming a conductive film on a semiconductor substrate via an insulating film, and using a photomask or reticle having a rectangular resist pattern and a diffraction grating pattern on the conductive film. A second step of forming a resist pattern having a region with a smaller thickness at the end than the center and dry etching to form a rectangular first gate electrode and a thinner film at the end than the center; Forming a second gate electrode having a region, and implanting an impurity element into the semiconductor substrate using the first gate electrode and the second gate electrode as a mask; Forming a first impurity region outside a gate electrode;
A fourth step of forming a second impurity region outside the gate electrode and a third impurity region overlapping the thin region of the second gate electrode. Manufacturing method. 5. A first step of forming a conductive film on a first semiconductor layer and a second semiconductor layer with an insulating film interposed therebetween, and forming a rectangular shape on the conductive film above the first semiconductor layer. Forming a resist pattern, and using a photomask or a reticle having a diffraction grating pattern on the conductive film above the second semiconductor layer, using a photomask or reticle having a thinner region at an end portion than at a central portion. A second step of forming a pattern and dry etching to form a rectangular first gate electrode above the first semiconductor layer, and a central portion above the second semiconductor layer. A third step of forming a second gate electrode having a thinner region at the end,
Using the first gate electrode and the second gate electrode as a mask, an impurity element is implanted into the first semiconductor layer and the second semiconductor layer, and a first element is formed outside the first gate electrode. A fourth step of forming an impurity region and forming a second impurity region outside the second gate electrode; and forming the rectangular resist pattern and a thinner region at an end portion than at the central portion. A fifth step of removing the resist pattern having: a sixth step of forming a resist pattern covering the first gate electrode; and the first step of using the resist pattern and the second gate electrode as a mask. Implanting the impurity element into the first semiconductor layer and the second semiconductor layer;
And forming a fourth impurity region outside the second gate electrode and a fifth impurity region overlapping the thin region of the second gate electrode.
And a step of manufacturing the semiconductor device. 6. A first step of forming a conductive film on a semiconductor substrate via an insulating film, and using a photomask or reticle having a rectangular resist pattern and a diffraction grating pattern on the conductive film. A second step of forming a resist pattern having a region with a smaller thickness at the end than the center, and dry etching to form a rectangular first gate electrode and a thinner gate at the end than the center; Second with thin areas
A third step of forming a gate electrode, and implanting an impurity element into the semiconductor substrate using the first gate electrode and the second gate electrode as a mask, and forming an impurity element outside the first gate electrode. A fourth step of forming a first impurity region and forming a second impurity region outside the second gate electrode; and forming a film on the rectangular resist pattern and a film on the edge from the center. A fifth step of removing a resist pattern having a thin region of a thickness, a sixth step of forming a resist pattern covering the first gate electrode, and masking the resist pattern and the second gate electrode. Implanting the impurity element into the semiconductor substrate to form a third impurity region outside the resist pattern, and a fourth impurity region and the second gate outside the second gate electrode. The method of manufacturing a semiconductor device, characterized in that it comprises a seventh step of forming a fifth impurity region overlapped with the film thickness of the thin region of the gate electrode, the. 7. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of slits are used as the diffraction grating pattern. 8. A first step of forming a conductive film over a semiconductor layer with an insulating film interposed therebetween, and using a photomask or a reticle having a semi-permeable film on the conductive film to move from a central portion to an end portion. A second step of forming a resist pattern having a region with a small thickness, a third step of performing etching to form a gate electrode having a region with a small thickness at an end portion from a central portion, and Forming a first impurity region outside the gate electrode and a second impurity region overlapping a thin film region of the gate electrode by implanting an impurity element into the semiconductor layer using the mask as a mask. And a method of manufacturing a semiconductor device. 9. A first step of forming a conductive film on a semiconductor substrate with an insulating film interposed therebetween, and using a photomask or a reticle having a semi-permeable film on the conductive film to move from a central portion to an end portion. A second step of forming a resist pattern having a region with a small thickness, a third step of performing etching to form a gate electrode having a region with a small thickness at an end portion from a central portion, and Forming a first impurity region outside the gate electrode and a second impurity region overlapping a thin film region of the gate electrode by implanting an impurity element into the semiconductor substrate using the mask as a mask. And a method of manufacturing a semiconductor device. 10. A first step of forming a conductive film on a first semiconductor layer and a second semiconductor layer with an insulating film interposed therebetween, and forming a rectangular conductive film on the conductive film above the first semiconductor layer. A resist pattern is formed, and using a photomask or reticle having a semi-permeable film on the conductive film above the second semiconductor layer, a resist pattern having a thinner region at an end portion than at a center portion is formed. Performing a second step of forming and dry etching to form a rectangular first layer above the first semiconductor layer;
A third step of forming a second gate electrode having a thinner region at an end portion than at a central portion above the second semiconductor layer; and forming the first gate electrode over the second semiconductor layer. An impurity element is implanted into the first semiconductor layer and the second semiconductor layer using the electrode and the second gate electrode as a mask to form a first impurity region outside the first gate electrode. And a fourth step of forming a second impurity region outside the second gate electrode and a third impurity region overlapping with a thin region of the second gate electrode. A method for manufacturing a semiconductor device, comprising: 11. A first step of forming a conductive film on a semiconductor substrate via an insulating film, and using a photomask or reticle having a rectangular resist pattern and a semi-permeable film on the conductive film. A second step of forming a resist pattern having a region with a smaller thickness at the end than the center and dry etching to form a rectangular first gate electrode and a thinner film at the end than the center; Forming a second gate electrode having a region, and implanting an impurity element into the semiconductor substrate using the first gate electrode and the second gate electrode as a mask; A first impurity region formed outside the gate electrode, and a third impurity region outside the second gate electrode overlapping the second impurity region and the thin region of the second gate electrode And a fourth step of forming A method of manufacturing a semiconductor device. 12. A first step of forming a conductive film on a first semiconductor layer and a second semiconductor layer with an insulating film interposed therebetween, and forming a rectangular shape on the conductive film above the first semiconductor layer. Using a photomask or a reticle having a semi-permeable film on the conductive film above the second semiconductor layer, the resist pattern having a thinner region at the end than at the center. A second step of forming a pattern and dry etching to form a rectangular first gate electrode above the first semiconductor layer, and a central portion above the second semiconductor layer. A third step of forming a second gate electrode having a thinner region at an end portion, and using the first gate electrode and the second gate electrode as masks to form the first semiconductor layer and the second gate electrode. Implanting an impurity element into the second semiconductor layer, The first gate electrode is provided outside the first gate electrode.
Forming a second impurity region outside the second gate electrode and forming a second impurity region outside the second gate electrode; Fifth step of removing the resist pattern having the region
And a sixth step of forming a resist pattern covering the first gate electrode, and the first semiconductor layer and the second semiconductor layer using the resist pattern and the second gate electrode as a mask. Implanting the impurity element to form a third impurity region outside the resist pattern; and forming a fourth impurity region outside the second gate electrode.
A seventh step of forming a fifth impurity region overlapping the impurity region of the second gate electrode and the thin region of the second gate electrode;
A method for manufacturing a semiconductor device, comprising: 13. A first step of forming a conductive film on a semiconductor substrate via an insulating film, and using a photomask or reticle having a rectangular resist pattern and a semi-permeable film on the conductive film. A second step of forming a resist pattern having a region with a smaller thickness at the end than the center, and dry etching to form a rectangular first gate electrode and a thinner gate at the end than the center; A third step of forming a second gate electrode having a thin region; and implanting an impurity element into the semiconductor substrate using the first gate electrode and the second gate electrode as masks, Forming a first impurity region outside the gate electrode and forming a second impurity region outside the second gate electrode; the rectangular resist pattern and the central portion; A thinner area at the end A fifth step of removing the resist pattern, a sixth step of forming a resist pattern covering the second gate electrode, and the semiconductor substrate using the resist pattern and the first gate electrode as a mask. Implanting the impurity element to form a third impurity region outside the resist pattern; and
A seventh step of forming a fourth impurity region outside the second gate electrode and a fifth impurity region overlapping a region where the thickness of the second gate electrode is small. Semiconductor device manufacturing method. 14. The method of manufacturing a semiconductor device according to claim 8, wherein the phase of the exposure light is shifted by one wavelength by transmitting through the semi-permeable film. 15. A first step of forming a conductive film on a semiconductor layer via an insulating film, and using a photomask or a reticle having a light intensity reducing means on the conductive film, from the center to the end. A second step of forming a resist pattern having a region with a small thickness on the other side, and a third step of performing a first etching to form a gate electrode having a region with a small thickness on the edge from the center. Implanting an impurity element into the semiconductor layer using the gate electrode as a mask to form a first impurity region outside the gate electrode and a second impurity region overlapping a thin region of the gate electrode. A method of manufacturing a semiconductor device, comprising: a fourth step; and a fifth step of performing a second etching to retract an end of the gate electrode. 16. A first step of forming a conductive film on a semiconductor substrate via an insulating film, and using a photomask or a reticle having a light intensity reducing means on the conductive film to form an end portion from a center portion to an end portion. A second step of forming a resist pattern having a region with a small film thickness and a first etching,
A third step of forming a gate electrode having a region with a smaller thickness at an end portion than at a center portion, and implanting an impurity element into the semiconductor substrate using the gate electrode as a mask; A fourth step of forming an impurity region and a second impurity region overlapping with a thin region of the gate electrode, and a fifth step of performing a second etching to recede an end of the gate electrode A method for manufacturing a semiconductor device, comprising: 17. A first step of forming a conductive film on a first semiconductor layer and a second semiconductor layer via an insulating film, and forming a rectangular shape on the conductive film above the first semiconductor layer. Forming a resist pattern, and using a photomask or a reticle having a light intensity reduction means on the conductive film above the second semiconductor layer, using a photomask or reticle having a thinner region at the end than at the center. A second step of forming a resist pattern and a first dry etching are performed to form a rectangular first gate electrode above the first semiconductor layer and a central portion above the second semiconductor layer. A third step of forming a second gate electrode having a thinner region at an end portion, and using the first gate electrode and the second gate electrode as masks to form the first semiconductor layer and the second gate electrode. Implanting an impurity element into the second semiconductor layer Forming a first impurity region outside the first gate electrode, and a second impurity region overlapping a thin film region of the second gate electrode; and a second impurity region outside the second gate electrode. A fourth step of forming a third impurity region, a fifth step of performing a second dry etching to recede an end of the second gate electrode,
A method for manufacturing a semiconductor device, comprising: 18. A first step of forming a conductive film on a semiconductor substrate via an insulating film, using a rectangular resist pattern on the conductive film, and a photomask or reticle having a light intensity reducing means. A second step of forming a resist pattern having a region with a smaller film thickness at the end portion than at the center portion,
A third step of performing a first dry etching to form a first gate electrode having a rectangular shape and a second gate electrode having a thinner region at an end portion than at a center portion; An impurity element is implanted into the semiconductor substrate using the gate electrode and the second gate electrode as masks to form a first impurity region outside the first gate electrode, and the second gate electrode A fourth step of forming a second impurity region overlapping the region with a small film thickness of the third layer and a third impurity region outside the second gate electrode; and performing a second dry etching to form the second impurity region. A fifth step of retreating the end of the second gate electrode. 2. A method of manufacturing a semiconductor device, comprising: 19. A first step of forming a conductive film on a first semiconductor layer and a second semiconductor layer via an insulating film, and using a photomask or a reticle having light intensity reducing means. Forming a first resist pattern having a thin region having a first width at an end portion on the conductive film above the first semiconductor layer, and forming a first resist pattern on the conductive film above the second semiconductor layer; A second step of forming a second resist pattern having a region having a second width with a small thickness at the end, and performing a first dry etching to form a second resist pattern with a first width at the end. Forming a first gate electrode having a thin region and a second gate electrode having a thin region having a second width at an end portion;
And the first resist pattern and the second resist pattern.
A fourth step of removing the resist pattern;
An impurity element is implanted into the first semiconductor layer and the second semiconductor layer using the gate electrode and the second gate electrode as masks, and a first element is formed outside the first gate electrode.
Forming an impurity region and a second impurity region overlapping a thin region of the first gate electrode;
A fifth step of forming a third impurity region outside the gate electrode and a fourth impurity region overlapping the thin region of the second gate electrode, and performing a second dry etching; A sixth step of retreating the ends of the first gate electrode and the second gate electrode, and a seventh step of forming a resist pattern using the second gate electrode as an opening region.
And the third dry etching is performed to obtain the second
An eighth step of retreating the end of the gate electrode described above. 20. A first step of forming a conductive film on a semiconductor substrate with an insulating film interposed therebetween, and a first rectangular step formed on the conductive film.
A second step of forming a second resist pattern having a region with a smaller thickness at the end than at the center using a photomask or a reticle having a light intensity reducing means; A third step of performing dry etching to form a rectangular first gate electrode and a second gate electrode having a region with a smaller thickness at an end portion than at a center portion; A fourth step of removing the second resist pattern; and implanting an impurity element into the semiconductor substrate using the first gate electrode and the second gate electrode as a mask, thereby forming an outer portion of the first gate electrode. Forming a first impurity region, and a second impurity region outside the second gate electrode;
A fifth step of forming a third impurity region overlapping a thin region of the gate electrode, and a sixth step of performing an end of the second gate electrode by performing a second dry etching. And a method of manufacturing a semiconductor device. 21. The method for manufacturing a semiconductor device according to claim 19, wherein the first width and the second width are the same. 22. The semiconductor device according to claim 15, wherein said light intensity reducing means is disposed at an end of the mask pattern, and the transmittance increases as approaching the end of the mask pattern. Manufacturing method. 23. The method of manufacturing a semiconductor device according to claim 15, wherein a diffraction grating pattern having a plurality of slits or a semi-permeable film is used as the light intensity reducing means. 24. A semiconductor device according to claim 1, wherein dry etching is applied as the etching. Method.