JP2007069341A - Method of manufacturing micro electromechanical system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a cantilever-type and other cubic structures in a simple way while using thin films formed on an insulated surface, and manufacturing micro electromechanical systems, based on said method. <P>SOLUTION: When etching is carried out through a mask whose thickness is partially different, a portion with a thin mask is etched first, so that it is possible to obtain a cubic structure having a form meeting the film thickness. When a cantilever is taken up as an example, a sacrificial layer 101 and a structural layer that performs the function of a cantilever are formed on an insulation substrate 100, and on these layers a mask 103 with different thickness is formed. When etching is implemented subsequently, the portion with a thin mask is etched first, and eventually a structural layer matching the mask thickness is constituted. Finally when the sacrificial layer is removed, a cantilever with partially different thickness can be obtained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a method for manufacturing a microelectromechanical device formed over an insulating substrate.

In recent years, research on micromechanical systems called MEMS (Micro Electro Mechanical Systems) has been actively promoted. MEMS is an abbreviation for a microelectromechanical system, and is sometimes simply called a micromachine. A micromachine generally refers to a microdevice in which “a microstructure having a three-dimensional structure and a movable microstructure” and “an electronic circuit having a semiconductor element” are integrated using a semiconductor microfabrication technique. Unlike the semiconductor element, the microstructure has a three-dimensional structure and has a movable portion.

One such micromachine is the cantilever. The cantilever is used as an air gap type piezoelectric thin film resonant element (see Patent Document 1).

Patent Document 1 provides a method for manufacturing a cantilever type FBRA (Film Bulk Acoustic Resonator) using a more simplified process. Therefore, the sacrificial layer is etched to form an air gap. It is described that the supporting portion and the protruding portion are connected in a cantilever shape.

In a semiconductor device having a display portion, it is known that a photomask or a reticle provided with an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film is applied to a photolithography process for forming a gate electrode. (For example, refer to Patent Document 2).

According to Patent Document 2, an LDD (Lightly Doped Drain) structure, a GOLD (Gate-drain Overlapped LDD) structure, and a single circuit are used for each circuit by using an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern or a semi-transmissive film. It is described that a transistor having a drain structure can be easily formed.
JP 2004-328745 A JP 2002-151523 A

In the conventional cantilever manufacturing method, the manufacturing method is complicated and the number of processes is increased. This is partly because the process of producing a unique shape such as a three-dimensional structure in which the cantilever has an uneven portion is complicated.

In the method described in Patent Document 1, an upper electrode is formed in a region serving as a weight in a cantilever-shaped structure layer, and materials having different unique three-dimensional shapes are laminated. Patent Document 1 describes only a process of manufacturing a cantilever using a silicon wafer. Since silicon wafers are expensive and have a circular shape, when a plurality of elements are formed, the number of wafers is limited and there is a limit to cost reduction.

Therefore, the present invention provides a method for easily forming a three-dimensional structure typified by a cantilever type formed on an insulating surface by a method different from the above-mentioned literature, and a microelectromechanical device manufactured by the method. This is the issue.

In view of the above problems, the present invention is characterized in that a three-dimensional structure typified by a cantilever is formed using masks having different film thicknesses.

The specific configuration of the present invention is shown below.

According to one embodiment of the present invention, a sacrificial layer is formed, a first layer is formed over the sacrificial layer, a mask having a first thickness and a second thickness is formed over the first layer, and the mask Is used to etch the first layer to form a structural layer and to remove the sacrificial layer.

In another embodiment of the present invention, a sacrificial layer is formed, a first layer is formed on the sacrificial layer, a mask having a first thickness and a second thickness is formed on the first layer, and the mask The first layer is etched to form a structural layer, and the sacrificial layer is removed. The structural layer has a thickness of a portion provided under the second film thickness mask. A method of manufacturing a microelectromechanical device characterized in that the thickness is smaller than the thickness of a portion provided under a mask having a thickness of 1.

In another embodiment of the present invention, a sacrificial layer is formed, a first layer is formed on the sacrificial layer, a mask having a first thickness and a second thickness is formed on the first layer, and the mask Is used to etch the first layer, form the structural layer, and remove the sacrificial layer. The structural layer has a thickness of a portion provided under the mask having the second thickness, The three-dimensional structure is formed by being thinner than the thickness of the portion provided under the first film thickness mask, and the portion provided under the first film thickness mask is used as the weight in the three-dimensional structure. It is a manufacturing method of the featured micro electro mechanical device.

According to another embodiment of the present invention, a sacrificial layer is formed, an amorphous silicon layer is formed on the sacrificial layer, and the amorphous silicon layer is converted into a polycrystalline silicon layer by crystallization using a metal. Forming a mask having a first film thickness and a second film thickness thereon, etching the polycrystalline silicon layer using the mask to form a structural layer, and removing the sacrificial layer; This is a method for manufacturing an electromechanical device.

According to another embodiment of the present invention, a sacrificial layer is formed, an amorphous silicon layer is formed on the sacrificial layer, and the amorphous silicon layer is converted into a polycrystalline silicon layer by crystallization using a metal. A method in which a mask having a first film thickness and a second film thickness is formed thereon, a polycrystalline silicon layer is etched using the mask, a structural layer is formed, and a sacrificial layer is removed. In the microelectromechanical device, the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. This is a manufacturing method.

According to another embodiment of the present invention, a sacrificial layer is formed, an amorphous silicon layer is formed on the sacrificial layer, and the amorphous silicon layer is converted into a polycrystalline silicon layer by crystallization using a metal. A method in which a mask having a first film thickness and a second film thickness is formed thereon, a polycrystalline silicon layer is etched using the mask, a structural layer is formed, and a sacrificial layer is removed. The layer forms a three-dimensional structure when the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. In the structure, a method of manufacturing a micro electro mechanical device is characterized in that a portion provided under a mask having a first thickness is a weight.

In the present invention, an amorphous silicon layer can be used as the sacrificial layer.

In another embodiment of the present invention, a semiconductor layer to be a semiconductor element is formed in a first region over an insulating substrate, a sacrificial layer is formed in a second region, a conductive layer is formed on the semiconductor layer and the sacrificial layer, and conductive A first mask and a second mask having a first film thickness and a second film thickness are formed over the layer, the conductive layer is etched using the first mask and the second mask, and a sacrificial layer The conductive layer provided under the first mask having the second film thickness is thinner than the thickness of the conductive layer provided under the first mask having the first film thickness. The conductive layer provided under the second mask having the second thickness is thinner than the conductive layer provided under the second mask having the first thickness. This is a method for manufacturing a mechanical device.

In another embodiment of the present invention, a semiconductor layer to be a semiconductor element is formed in a first region over an insulating substrate, a sacrificial layer is formed in a second region, a conductive layer is formed on the semiconductor layer and the sacrificial layer, and conductive A mask material is applied over the layer, a first mask and a second mask having a first thickness and a second thickness are formed from the mask material, and the first mask and the second mask are used. The method of etching the conductive layer and removing the sacrificial layer, wherein the conductive layer provided under the first mask with the second thickness is provided under the first mask with the first thickness. The thickness of the conductive layer provided below the second mask having the second film thickness is smaller than the thickness of the conductive layer provided, and the thickness of the conductive layer provided below the second mask having the first film thickness. A method for manufacturing a microelectromechanical device, which is characterized by being thinner.

In another embodiment of the present invention, a semiconductor layer to be a semiconductor element is formed in a first region over an insulating substrate, a sacrificial layer is formed in a second region, a conductive layer is formed on the semiconductor layer and the sacrificial layer, and conductive A first mask and a second mask having a first film thickness and a second film thickness are formed over the layer, and the conductive layer is etched using the first mask and the second mask to sacrifice the layer. In this method, the conductive layer provided under the first mask having the second film thickness is larger than the thickness of the conductive layer provided under the first mask having the first film thickness. The thin conductive layer provided under the second mask having the second film thickness is thinner than the conductive layer provided under the second mask having the first film thickness. In the three-dimensional structure, the portion provided under the mask having the first film thickness is a weight. Which is a manufacturing method.

In another embodiment of the present invention, a semiconductor layer to be a semiconductor element is formed in a first region over an insulating substrate, a sacrificial layer is formed in a second region, a conductive layer is formed on the semiconductor layer and the sacrificial layer, and conductive A first mask and a second mask having a first thickness and a second thickness are formed over the layer, and the conductive layer is etched using the first mask and the second mask. A gate electrode of a semiconductor element is formed in one region, a structural layer is formed in a second region, an impurity region is formed in the semiconductor layer using the gate electrode, and the impurity region and the structural layer are connected to each other. The conductive layer provided under the first mask with the second film thickness is provided under the first mask with the first film thickness. The conductive layer provided under the second mask having the second film thickness which is thinner than the conductive layer having the first film thickness is Thinner than the thickness of the provided though conductive layer under the second mask is a method for manufacturing a micro-electro-mechanical device according to claim.

In the present invention, the thickness of the second film thickness mask is smaller than the thickness of the first film thickness mask.

In the present invention, the second film thickness of the mask is produced using a photomask or reticle having an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film.

In the present invention, the first film thickness of the mask is manufactured using a photomask or a reticle having a mask pattern in which the film thickness is not intentionally different, and the second film thickness of the mask is the photomask or reticle. And a photomask or a reticle having a mask pattern in which the film thickness is intentionally different.

Furthermore, the present invention is a microelectromechanical device manufactured as described above.

In the present invention, a microstructure can be manufactured over an insulating substrate by applying a mask having a different thickness to a thin film typified by a silicon layer. As a result, a microstructure having a three-dimensional structure can be easily produced.

The microstructure of the present invention can be formed over the insulating substrate integrally with a semiconductor element that controls the microstructure. As a result, poor connection between the microstructure and the semiconductor element can be reduced, and mass productivity can be improved.

The microstructure of the present invention can be applied to a switch. Such a switch can be made thinner and less expensive than a switch made of a silicon wafer.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a method for manufacturing a microstructure formed using masks having different thicknesses will be described. In this embodiment mode, in the photolithography method, a mask is processed using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern or a semi-transmissive film.

As shown in FIG. 1A, a substrate (referred to as an insulating substrate) 100 having an insulating surface is prepared. Note that FIG. 1B is a cross-sectional view taken along a line AB.

As the insulating substrate 100, a glass substrate, a quartz substrate, a plastic substrate, or the like can be used. For example, by forming a microstructure on a plastic substrate, a device having a highly flexible and thin microstructure can be formed. In addition, a thin device can be formed by thinning the glass substrate by polishing or the like. Furthermore, the microstructure of the present invention can be formed over a conductive substrate such as a metal or a substrate in which an insulating layer is formed over a semiconductor substrate such as silicon.

A sacrificial layer 101 is formed over the insulating substrate 100. Note that the sacrificial layer refers to a layer that is selectively removed in a later step. Therefore, the sacrificial layer may be removed and may be a conductive layer or an insulating layer. By removing such a sacrificial layer, a space is created. That is, a structure having a predetermined shape can be formed in the space. The sacrificial layer 101 can be formed using a material having a metal such as titanium (Ti), aluminum (Al), molybdenum (Mo), or tungsten (W), and includes a semiconductor layer including silicon (also referred to as a silicon layer), silicon It can also be formed by a material having an oxide (silicon oxide) or silicon nitride (silicon nitride). The sacrificial layer 101 may be formed using a metal compound that is a compound of the above metal and silicon. Further, the sacrificial layer 101 may have a single layer structure or a laminated structure. In the case of a stacked structure, a material selected from the above materials may be stacked.

The sacrificial layer 101 can be formed using a sputtering method, a CVD method, or the like. The sacrificial layer 101 can be processed by forming a resist mask using a photolithography method and performing a dry etching method. It can also be formed by a droplet discharge method typified by an ink jet method. In the case of using a droplet discharging method, the sacrificial layer 101 can be selectively formed by dropping a solvent mixed with the above-described metal. Therefore, the photolithography process and the patterning process of the sacrificial layer 101 can be omitted. As a result, waste of resist material and process time can be saved.

If the thickness of the sacrificial layer 101 is too thin, the etching agent does not diffuse and the sacrificial layer 101 is not etched, or the structure layer buckles (the microstructure is attached to the lower surface) after etching. On the other hand, in the case where the microstructure is electrostatically driven through the space generated when the sacrificial layer is removed, if the sacrificial layer 101 is too thick, the distance of the space becomes large and it is difficult to drive the microstructure. Therefore, when the microstructure is used as a switching element by electrostatic driving, the thickness of the sacrificial layer 101 is preferably 0.5 μm to 4 μm. Of course, it is necessary to consider the material of the sacrificial layer 101. The thickness of the sacrificial layer 101 can be the height of the space.

In this embodiment mode, a silicon layer is used for the sacrificial layer 101 and is formed by a CVD method. After that, a mask is formed using a photolithography method, and the sacrificial layer 101 is etched using the mask. In this embodiment mode, the sacrificial layer 101 is etched in a rectangular shape.

Next, as shown in FIG. 2A, a structural layer 102 is formed over the sacrifice layer 101 by a sputtering method, a CVD method, or the like. The structural layer 102 can be formed from a silicon layer. As a material of the silicon layer, there is silicon germanium having silicon and germanium in an amount of about 0.01 to 4.5 atomic%. The silicon layer can be used in an amorphous state or a crystalline state. The structural layer 102 can also be formed using silicon oxide or silicon nitride, and a metal material such as titanium (Ti), aluminum (Al), molybdenum (Mo), or tungsten (W) can be used. . The structural layer 102 may be formed using a metal compound that is a compound of the above metal and silicon. Further, the structural layer 102 may have a single layer structure or a stacked structure. In the case of a laminated structure, each material selected from the above materials may be laminated.

In the case where conductivity is necessary for the structural layer 102 formed from a silicon layer, an impurity element such as phosphorus, arsenic, or boron can be added. An impurity region may be formed by adding such an impurity element. The impurity region can be formed by forming a resist mask by photolithography and selectively adding an impurity element. The impurity element can be added by an ion doping method or an ion implantation method. Such a microstructure having conductivity is preferably controlled by electrostatic force (also referred to as electrostatic attraction) and is suitable for a cantilever switch. Of course, the microstructure may be controlled by electromagnetic force.

After the impurity region is formed, heat treatment may be performed to activate the impurity element.

Note that the sacrificial layer 101 and the structural layer 102 are not limited to the above-described materials, and may be any combination of materials that can selectively remove the sacrificial layer 101. Therefore, even if it is the same material, it may be a combination of a material that is selectively removed by a specific etching agent and a material that is not removed depending on the crystal state or the like.

Thus, by forming the structural layer by a thin film made of a silicon layer or the like, it can be formed very thin as compared with the case of using a wafer. Further, since such a structural layer can be formed over an insulating substrate, production cost can be reduced.

Next, as illustrated in FIG. 2A, a mask 103 is formed over the structural layer 102. Note that FIG. 2B is a cross-sectional view taken along line AB.

For the mask 103, a commercially available resist material containing a photosensitive agent may be used, and a positive resist or a negative resist can be used. A typical positive resist is a novolak resin and a naphthoquinone diazide compound that is a photosensitizer, such as a base resin that is a typical negative resist, diphenylsilanediol, and an acid generator. In addition, resin materials such as epoxy resin, acrylic resin, phenol resin, melamine resin, and urethane resin can be used. The mask 103 includes benzocyclobutene, parylene, fluorinated arylene ether, an organic material such as polyimide having transparency, a compound material made by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer. It can also be formed by a droplet discharge method using a composition material or the like.

Then, the mask 103 is exposed and developed to process it into a predetermined shape. In this embodiment mode, the mask 103 is shaped to cover most of the sacrificial layer 101. Further, as shown in FIG. 2B, the thickness of the mask 103 is different. In this embodiment, the mask 103 has a first thickness (d1) and a second thickness (d2). The film thickness of 2 is thinner than the first film thickness (d2 <d1).

In order to form the mask 103, an exposure mask provided with an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film is used. Examples of the exposure mask include a photomask or a reticle. Such an exposure mask will be described with reference to FIGS. 6 to 8, the widths of the light shielding portions for forming the mask for the first film thickness (d1) region are t1 and t3, and the mask for the second film thickness (d2) region is formed. The width of the portion where the auxiliary pattern is provided is denoted by t2.

FIG. 6A is a top view of an exposure mask 401 provided with a diffraction grating pattern portion 403 having a slit portion having lines and spaces below the resolution limit of the exposure apparatus, a light shielding portion 402, and a light transmitting portion 404. Indicates the part. The diffraction grating pattern portion 403 is a pattern in which at least one pattern such as a slit and a dot is arranged. When a plurality of patterns such as slits and dots are arranged, they may be arranged periodically or aperiodically. By using a fine pattern having a resolution limit or less, it is possible to modulate a substantial exposure amount and to adjust a film thickness of an exposed mask.

The slit direction of the diffraction grating pattern portion 403 may be parallel to the long axis direction of the light shielding portion 402 or may be perpendicular to the long axis direction of the light shielding portion 402 as shown in FIG. In addition, when applying a resist as a mask used in this photolithography process, since a negative resist is difficult to apply, a positive resist is assumed.

When the exposure mask 401 is irradiated with light, the light intensity of the light shielding portion 402 is zero, and the light intensity of the light transmitting portion 404 is 100%. On the other hand, the light intensity of the diffraction grating pattern portion 403 composed of lines and spaces below the resolution limit of the exposure apparatus can be adjusted in the range of 10 to 70%. An example of such light intensity is shown in a light intensity distribution 409 in FIG. The adjustment of the light intensity of the diffraction grating pattern unit 403 is realized by adjusting the slit pitch and slit width.

Further, as a specific example of the auxiliary pattern, FIG. 8A includes a semi-transmissive portion 407 made of a semi-permeable film having a function of reducing the light intensity of exposure, and the light shielding portion 402, as in FIGS. A part of a top view of an exposure mask 415 having a light transmitting portion 404 is shown. As the semipermeable membrane, silicide such as MoSiN, MoSi, MoSiO, MoSiON, CrSi can be used. An exposure method using an exposure mask provided with a semi-transmissive portion 407 is also called a halftone exposure method.

When such an exposure mask 415 is irradiated with light, the light intensity of the light-shielding portion 402 is zero, the light intensity of the light-transmitting portion 404 is 100%, and the light intensity of the semi-transmissive portion 407 made of a semi-transmissive film is Adjustment is possible within a range of 10 to 70%. That is, the light intensity can be continuously changed or changed in multiple steps over the semipermeable membrane and the light shielding portion. An example of the light intensity of the exposure mask is shown in a light intensity distribution 410 in FIG.

When exposed using the exposure masks 401 and 415, the mask has a first film thickness (d1) and a second film thickness (d2), and the second film thickness is smaller than the first film thickness. 103 can be obtained.

The structural layer 102 is etched using such a mask 103. In this embodiment mode, only one side of the structural layer 102 is provided beyond the end surface of the sacrificial layer 101, and the other side is shorter than the end surface of the sacrificial layer 101. It is processed into a rectangular shape so as to be narrower. That is, in the cross-sectional view illustrated in FIG. 2B, the structural layer 102 and the mask 103 have a step due to the sacrificial layer 101.

Thereafter, the structural layer 102 is processed using a mask 103 as shown in FIG. A wet etching method or a dry etching method can be applied to the processing. At this time, the structural layer 102 not covered with the mask 103 and the surface of the mask 103 are removed. Since the second film thickness (d2) is thin, the mask 103 is removed before the region of the first film thickness (d1), and the structural layer 102 under the mask 103 having the second film thickness is removed. As a result, the structural layer 102 is processed to have the third film thickness (d3) and the fourth film thickness (d4) by a single etching process without removing the mask 103 or forming it again. Can do. In other words, the portion having the third thickness in the structural layer 102 is formed under the mask 103 having the first thickness, and the portion having the fourth thickness is a mask having the second thickness. 103 is formed below. In the present embodiment, in the structural layer 102, the fourth film thickness is thinner than the third film thickness (d4 <d3).

In the case where the microstructure of the present invention is used as a switching element, the length of the movable portion of the structural layer is preferably 30 to 50 times the film thickness of the structural layer 102 having the fourth film thickness. At this time, it is preferable to consider the spring constant of the microstructure. The thickness of the structural layer 102 having the third thickness is determined in consideration of the density. When the structure layer having the third film thickness is low density, the contact with the lower electrode can be increased by increasing the film thickness.

Next, as shown in FIG. 4, the mask 103 is removed. A wet etching method or a dry etching method can be applied to the removal of the mask 103. For example, "Nagase Resist Strip N-300" stripping solution made by Nagase ChemteX, which has 2-aminoethanol and glycol ether as the main components, and Tokyo Ohka, which has o-dichlorobenzene, phenol, and alkylbenzene sulfonic acids as main components. A stripping solution such as “stripping solution 710” manufactured by Kogyo Co., Ltd. can be applied.

Then, as shown in FIG. 5, the sacrificial layer 101 is removed. A wet etching method or a dry etching method can be applied to the removal of the sacrificial layer.

For example, when tungsten (W) is used for the sacrificial layer 101, the sacrificial layer 101 can be removed by immersing it in a solution in which 28% ammonia and 31% hydrogen peroxide solution are mixed at 1: 2 for about 20 minutes. When silicon dioxide (SiO ₂ ) is used for the sacrificial layer 101, it can be removed by using buffered hydrofluoric acid in which ammonium fluoride is mixed in a ratio of 7 to the 49% aqueous solution 1 of hydrofluoric acid. In the case where a layer including silicon is used for the sacrificial layer 101, it can be removed using a hydroxide of an alkali metal element such as phosphoric acid, KOH, NaOH, or CsOH. Other sacrificial layer materials can be removed using NH ₄ OH, hydrazine, EPD (a mixture of ethylenediamine, pyrocatechol, water), TMAH, IPA, NMD3 solution, or the like. In addition, the layer having silicon is removed using halogen fluoride such as chlorine trifluoride (ClF ₃ ), nitrogen trifluoride (NF ₃ ), bromine trifluoride (BrF ₃ ), hydrogen fluoride (HF), or the like. You can also.

When drying after wet etching, in order to prevent the microstructure from buckling due to capillary phenomenon, rinse with a low-viscosity organic solvent (for example, cyclohexane), or dry under low temperature and low pressure conditions, or both It is good to perform combined processing.

The sacrificial layer 101 can be removed by dry etching using O ₂ , F ₂ , or XeF ₂ under a high pressure condition such as atmospheric pressure. In order to prevent buckling of the microstructure due to the capillary phenomenon described above, plasma treatment for imparting water repellency to the surface of the microstructure may be performed.

When the sacrificial layer 101 is removed in this way, a space 105 is generated. The structural layer 102 can be moved vertically and horizontally by the space 105. The structure layer 102 can operate as a switch by contact with the lower electrode at the tip at which the structural layer 102 is movable. A microstructure having such a shape is called a cantilever microstructure. When a cantilever microstructure is applied to a switch, low loss and low power operation can be performed.

The removal of the mask 103 and the removal of the sacrificial layer 101 can also be performed in the same step. In this case, the mask 103 and the sacrificial layer 101 are preferably formed from the same material or a material that can be removed by the same etchant.

Thus, according to the present invention, a cantilever microstructure can be manufactured over an insulating substrate with a thin film typified by a silicon layer. The cantilever microstructure of the present invention can be applied to a switch, and such a switch can be made thinner and less expensive than a switch made of a silicon wafer.

In addition, as shown in the following embodiments, the cantilever microstructure of the present invention can be formed over the same insulating substrate as the semiconductor element. As a result, connection failure between the cantilever microstructure and the semiconductor element can be reduced, and mass productivity can be improved.

The cantilever microstructure shown in this embodiment mode can be used as an AFM needle, an acceleration sensor (G sensor), or an angular velocity sensor in addition to a switch.

(Embodiment 2)
In the present invention, a silicon layer applied to a structural layer or a sacrificial layer can be a crystalline layer, an amorphous state, or the like. Therefore, in this embodiment, the case where a crystalline silicon layer is used as a sacrificial layer is described.

First, as shown in FIG. 13A, an amorphous silicon layer 161 is formed over an insulating substrate 100 which is a surface on which a sacrificial layer is formed. The amorphous silicon layer 161 can be manufactured by a CVD method using a source gas such as SH ₄ or Ar. The film thickness of the amorphous silicon layer 161 is the thickness of the sacrificial layer, which is the height of the space.

Then, the amorphous silicon layer is heat-treated to obtain a crystallized crystalline silicon layer. For the heat treatment, laser irradiation, a heating furnace, irradiation with light emitted from lamp light (hereinafter referred to as lamp annealing), or a combination thereof can be used.

In the case of using laser irradiation, a continuous wave laser beam (hereinafter referred to as a CW laser beam) or a pulsed laser beam (hereinafter referred to as a pulsed laser beam) can be used. As the laser beam, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor A laser or a gold vapor laser oscillated from one or a plurality of types can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser beam is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

The fundamental CW laser beam and the harmonic CW laser beam may be irradiated, or the fundamental CW laser beam and the harmonic pulse laser beam may be irradiated. Thus, energy can be supplemented by irradiating a plurality of laser beams.

It is also possible to use a pulsed laser beam that oscillates a laser at an oscillation frequency that allows irradiation of the next pulse of laser light after the silicon layer is melted by the laser light and solidifies. By oscillating the laser beam at such a frequency, crystal grains continuously grown in the scanning direction can be obtained. A specific oscillation frequency of the laser beam is 10 MHz or more, and a frequency band that is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used is used.

When a heating furnace is used as other heat treatment, the amorphous silicon layer is heated at 400 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 400 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating step of about 400 ° C., hydrogen and the like of the amorphous silicon layer are generated, so that film roughness during crystallization (including crystallization using the laser) can be reduced.

Furthermore, when crystallization is performed using a metal that promotes crystallization, the heating temperature can be lowered. For example, when nickel (Ni) is formed on an amorphous silicon layer and then heated, the heating temperature decreases. Such metals include iron (Fe), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), silver (Au ) Etc.

Further, in addition to the heat treatment, the crystalline silicon layer may be formed by irradiation using the laser as described above.

In this embodiment mode, as illustrated in FIG. 13B, a solution containing nickel is applied over the amorphous silicon layer 161, and then crystallization is performed using a heating furnace. The heating temperature is 500 to 550 degrees.

Then, as shown in FIG. 13C, a silicon layer (polycrystalline silicon layer) 163 crystallized using a metal can be obtained.

Thereafter, as shown in FIG. 13D, the polycrystalline silicon layer 163 can be processed into the sacrificial layer 101 having a predetermined shape. A polycrystalline silicon layer can be processed by forming a mask by photolithography and etching using the mask.

After that, as shown in FIG. 13E, a cantilever microstructure can be manufactured in the same manner as in Embodiment Mode 1.

Although the case where polycrystalline silicon crystallized using a metal is applied to the sacrificial layer 101 has been described above, the polycrystalline silicon layer may be applied to the structural layer 102. Polycrystalline silicon crystallized using such a metal can produce polycrystalline silicon having continuous grain boundaries by crystallization using a metal. Unlike polycrystalline silicon obtained by crystallization without using a metal, polycrystalline silicon in which crystal grain boundaries are continuous does not break a covalent bond at the crystal grain boundary. Therefore, the stress concentration caused by the crystal grain boundary does not occur, and as a result, the fracture stress is higher than that of polycrystalline silicon formed without using a metal. Such a crystalline structure of polycrystalline silicon is close to that of using a single crystal, and polycrystalline silicon having higher toughness than polycrystalline silicon produced by crystallization without using a metal can be obtained. Such polycrystalline silicon is suitable for the movable structural layer 102.

A polycrystalline silicon layer having continuous crystal grain boundaries is suitable for controlling the structural layer 102 with an electrostatic force because of its high electron mobility. Furthermore, conductivity can be imparted by allowing the metal that promotes crystallization to remain in the polycrystalline silicon layer. Such a polycrystalline silicon layer having conductivity is suitable for a microelectromechanical device that controls the structural layer 102 with an electrostatic force. Needless to say, a polycrystalline silicon layer crystallized using metal may be applied to the structural layer 102 when the microstructure is controlled by electromagnetic force.

When nickel is used as the metal, nickel silicide is formed in the silicon layer depending on the nickel concentration. Silicon alloys such as nickel silicide have high strength. Therefore, silicidation can be performed using a metal for crystallization, and the structural layer 102 that is harder and has higher conductivity can be manufactured.

Such a silicide can be formed of tungsten, titanium, molybdenum, tantalum, cobalt, or platinum in addition to nickel. A tungsten silicide layer, a titanium silicide layer, a molybdenum silicide layer, a tantalum silicide layer, a cobalt silicide layer, and a platinum silicide layer are formed. Among these, cobalt and platinum can be used as a metal for lowering the crystallization heating temperature.

The structural layer 102 can have a stacked structure, and a layer including nickel silicide (nickel silicide layer) and a polycrystalline silicon layer may be stacked. With such a stacked structure, a flexible structural layer 102 having excellent conductivity can be obtained. Further, by stacking an amorphous silicon layer and a nickel silicide layer on the structural layer 102, the structure layer 102 can be hardened while being excellent in conductivity.

As described above, when crystallization is performed using a metal, crystallization can be performed at a lower temperature than crystallization performed without using a metal. Therefore, the range of materials that can be used for the substrate over which the microstructure is formed is increased. For example, when a silicon layer is crystallized only by heating, it is necessary to perform heating for about 1 hour at a temperature of about 1000 ° C., and a glass substrate that is vulnerable to heat cannot be used. However, crystallization using a metal as in this embodiment makes it possible to use a glass substrate having a low distortion point.

This embodiment can be freely combined with the above embodiment.

(Embodiment 3)
When the microstructure of the present invention is moved by electrostatic force, a lower electrode used as a common electrode or a control electrode is formed under the structural layer. Thus, in this embodiment, a cantilever microstructure including a lower electrode is described.

As shown in FIG. 12, a conductive layer that functions as the lower electrode 150 is formed in the space 105 below the structural layer 102. The lower electrode 150 can be used as a common electrode, a control electrode, or the like. The lower electrode 150 can be formed by a sputtering method or the like using a metal such as tungsten or a conductive substance as a material, and is etched into a predetermined shape as necessary.

This embodiment can be freely combined with the above embodiment.

(Embodiment 4)
In this embodiment mode, types of cantilevers to which the microstructure of the present invention can be applied will be described.

As shown in FIG. 15A, a first electrode 502 and a second electrode 503 are provided below the structural layer 501. The first electrode 502 functions as a control, and the second electrode 503 functions as a contact. A selection signal indicating whether to select the structural layer 501 is input to the first electrode 502 functioning as a control. When a selection signal flows, a potential difference is generated between the structural layer 501 and the first electrode 502, and the structural layer 501 is lowered by static electricity due to the potential difference. Then, the tip of the structural layer 501 comes into contact with the second electrode 503 that functions as a contact, and a current flows.

A plurality of electrodes functioning as controls and electrodes functioning as contacts may be provided. For example, as shown in FIG. 15B, two first electrodes 502 and 504 functioning for control may be provided. The structural layer 501 can be moved up and down by static electricity generated in the control electrodes 502 and 504 and the structural layer 501. Therefore, by providing a plurality of control electrodes, the operation of the structural layer 501 can be accurately controlled even when the structural layer 501 is large and difficult to operate. The operation can also be accurately controlled by increasing the area of the control electrode. Similarly, a plurality of contact electrodes may be provided or the area may be increased. Contact resistance is lowered, and accurate contact can be made.

Further, the microstructures above the control and contact electrodes are provided to be thicker than the microstructures in other regions. As a result, since the weight of the structural layer 501 increases, it is particularly easy to control the descending operation of the structural layer 501. As a result, accurate contact can be made.

In this manner, the structural layer 501 can be selected and operated as a cantilever switch.

FIG. 15C illustrates a bridge-type switch, which is different from the cantilever type. In the bridge-type switch, both ends of the structural layer 501 are fixed, and other structures are the same as those in FIG. Such a bridge-type structural layer 501 can also be formed using masks having different thicknesses of the present invention.

In such a switch of the present invention, the structural layer 501 in contact with the electrode may be provided with a highly conductive film in order to reduce contact resistance. In addition, a highly conductive film may be provided on the electrode side. Such a film can not only reduce the contact resistance, but also reduce the wear of the microstructure and the electrodes.

FIG. 16A shows a top view of a switch having a microstructure. A cut wiring 507 is provided below the structural layer 501, and the structural layer 501 and the wiring 507 are arranged to overlap each other. As the structural layer 501, a cantilever type or a bridge type can be used.

When the switch shown in FIG. 16A is selected, the wiring 507 is turned on, and a current or a signal can flow. Thus, it can function as a switch. Such a switch is a series switch.

FIG. 16B is a top view of a switch different from that in FIG. A wiring 509 and a wiring 510 are provided in parallel, and are provided in the connection region in a T-shape therefrom. In the connection region, the structural layer 501 is disposed above the wirings 509 and 510. In the state where the structural layer 501 is off, a current flows from the point A which is one end of the wiring 509 to the GND 1 which is the other end. Similarly, when the structural layer 501 is off, a current flows from the point B which is one end of the wiring 510 to the GND 2. In such a form, when the structural layer 501 is selected and turned on, a signal flows from the point A to the point B. Such a switch is a shunt switch.

As described above, when the cantilever switch is turned on, a current flows, that is, a signal is transmitted. However, a signal may not be transmitted when the cantilever switch is turned on.

(Embodiment 5)
Microstructures are subject to air resistance because they perform up / down and left / right movements, as well as rotations. Therefore, in this embodiment, a form of a microstructure with reduced air resistance will be described.

FIG. 18A shows a top view of the structural layer 501. In the structural layer 501, the width (d6) of the movable part region is smaller than the width (d7) of the region where the weight is provided (hereinafter referred to as the weight region) (d6 <d7). By making the width of the movable region smaller than the width of the weight region, the operation of the movable portion can be performed smoothly.

At this time, the deterioration of the movable part due to the vertical movement or the like is taken into consideration. For example, the film thickness of the microstructure in the movable part region can be controlled to prevent the movable part from being deteriorated due to the operation.

FIG. 18B is a top view of a microstructure having a tapered boundary with the weight region in the movable portion region, unlike FIG. 18A. By making the boundary into a tapered shape, the operation of the movable part can be performed more smoothly.

18C, in addition to the microstructure in FIG. 18B, an opening 801 is provided in the microstructure in the movable portion region. One or more openings 801 may be provided. Further, when the number of openings is single, the diameter of the openings is increased, and when there are a plurality of openings, the diameter of the openings does not need to be increased so much. The opening 801 can reduce air resistance particularly when the microstructure performs an up-and-down operation.

A microstructure having such an opening can be formed using the masks having different thicknesses of the present invention.

Such a microstructure can be freely combined with any of the above embodiments.

(Embodiment 6)
A switch having a microstructure can output data to a large number of terminals. In this embodiment, a mode of a switch that enables multi-terminal output will be described.

In FIG. 19, a switch that has three output terminals (OUT1 to OUT3) for one input terminal (IN), and controls which signal is output to which output terminal by the microstructures 1 to 3. Indicates. For example, when the microstructure 1 is selected, a signal is output from IN to OUT1. When the microstructures 1 and 2 are selected, signals are output from IN to OUT1 and 2. The microstructures 1 to 3 are formed using masks having different film thicknesses of the present invention.

In this embodiment, the case of having three output terminals has been described, but the present invention is not limited to this. The switch having the microstructure of the present invention may have two output terminals or four or more output terminals.

(Embodiment 7)
In this embodiment, a method for forming the above microstructure and a semiconductor element for controlling the microstructure on the same surface will be described. In this embodiment, the case where a top-gate thin film transistor in which a gate electrode is provided above a semiconductor film is used as a semiconductor element is described.

As shown in FIG. 10A, a base layer 201 is formed over the insulating substrate 100. As the insulating substrate 100, a substrate similar to that in Embodiment Mode 1 can be used. As the base layer 201, an insulating layer containing silicon can be used. As the insulating layer containing silicon, silicon oxide or silicon nitride can be given, which is typically silicon oxide, silicon nitride, or silicon oxynitride. The base layer 201 can have a single-layer structure or a stacked structure using such a material.

In this embodiment, the case where a two-layer structure is used as the base layer 201 is described. As the first layer of the base layer 201, a silicon oxynitride layer having a thickness of 10 nm to 200 nm (preferably 50 nm to 100 nm) is formed. The silicon oxynitride layer can be formed using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as a reactive gas by a plasma CVD method. Next, a silicon oxynitride layer with a thickness of 50 nm to 200 nm (preferably 100 nm to 150 nm) is formed as the second layer of the base layer 201. The silicon oxynitride layer can be formed using SiH ₄ and N ₂ O as a reaction gas by a plasma CVD method.

A semiconductor layer is formed over the base layer 201. A silicon layer can be applied to the semiconductor layer. Embodiment 2 can be referred to for the method for manufacturing the polycrystalline silicon layer. In this embodiment mode, an amorphous silicon layer is formed, and a polycrystalline silicon layer crystallized using a metal is manufactured.

Such a polycrystalline silicon layer has high mobility and is suitable for a semiconductor element.

After that, in the first region 251 for forming a semiconductor element and the second region 252 for forming a microstructure, the polycrystalline silicon layer is processed to form silicon layers 202 and 204 having a predetermined shape. The first region 251 is processed so as to be an active layer of a semiconductor element. Note that the active layer includes a channel formation region, a source region, and a drain region. Further, the second region 252 is processed to have a rectangular shape as described in the above embodiment.

As shown in FIG. 10B, an insulating layer 206 functioning as a gate insulating layer is formed only in the first region 251. For the insulating layer 206, silicon oxide or silicon nitride can be used, which is typically silicon oxide, silicon nitride, silicon oxynitride, or the like. In order to selectively form the insulating layer 206 in the first region 251, the second region 252 is covered with a mask 205. For the mask 205, a commercially available resist material containing a photosensitive agent may be used, and a positive resist or a negative resist can be used. A typical positive resist is a novolak resin and a naphthoquinone diazide compound that is a photosensitizer, such as a base resin that is a typical negative resist, diphenylsilanediol, and an acid generator. In addition, resin materials such as epoxy resin, acrylic resin, phenol resin, melamine resin, and urethane resin can be used. The mask 205 includes an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, permeable polyimide, a compound material formed by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer. It can also be formed by a droplet discharge method using a composition material or the like. In addition, the insulating layer 206 may be formed over the first region 251 and the second region 252 and then the insulating layer 206 in the second region 252 may be removed.

Although the case where the insulating layer 206 is formed only in the first region 251 has been described, the insulating layer 206 may be formed in the second region 252. However, the silicon layer that becomes the sacrifice layer 204 can be removed.

As shown in FIG. 10C, after the mask 205 is removed, a conductive layer 208 that functions as a gate electrode is formed over the first region 251 and the second region 252. As the conductive layer 208, a film formed of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or silicon (Si) or an alloy film including these elements is used. Can do. The conductive layer 208 can have a single-layer structure or a stacked structure, and a stacked structure of tantalum nitride and tungsten can be used as the stacked structure. The conductive layer 208 can be manufactured by a sputtering method or a CVD method.

As shown in FIG. 11A, a mask 210 is formed over the conductive layer 208 in the first region 251 and the second region 252. The mask 210 can be formed by a photolithography method. In the photolithography method, a photomask or a reticle provided with an auxiliary pattern having a function of reducing light intensity made of a diffraction grating pattern or a semi-transmissive film is used. In a region where an auxiliary pattern having a light intensity reduction function composed of a diffraction grating pattern or a semi-transmissive film is provided, the light transmittance is reduced. As a result, the mask 210 having the first film thickness (d1) and the second film thickness (d2) thinner than d1 can be formed. The region where the light transmittance is reduced becomes the region of the second film thickness (d2) of the mask. Note that the mask 210 in the first region 251 is set so that d1 is inside and d2 is outside. The mask 210 in the second region 252 is set so that d2 is inside and d1 is outside. As described above, which region is thinned in the thickness of the mask can be determined by the pattern to be processed. After that, the conductive layer 208 is processed using a wet etching method or a dry etching method.

As shown in FIG. 11B, when etching is started, the conductive layer 208 not covered with the mask 210 and the surface of the mask 210 are gradually removed. In the mask 210, the region of the second film thickness (d2) is removed first, and the conductive layer 208 is exposed. As a result, as shown in FIG. 11C, a taper (dotted line region) is formed at an end portion of the conductive layer 208 in the first region 251, and a central portion of the conductive layer 208 is formed in the second region 252. A recess (dotted line region) is formed. In order to form the taper, the mask 210 may be exposed and developed using a photomask or a reticle having an auxiliary pattern with a narrow diffraction pattern width in order to gradually reduce the light transmittance toward the outside.

As shown in FIG. 11D, the mask 210 can be removed and the conductive layers 208 having different thicknesses can be formed. That is, the mask 210 can process conductive layers having different thicknesses in one etching process. Of course, even a layer other than the conductive layer may be processed using the mask of the present invention.

Then, an impurity element is added using the conductive layer 208 having a taper in the silicon layer in the first region 251. The semiconductor element 253 can be formed using phosphorus (P) as an impurity element imparting n-type conductivity, and the semiconductor element 254 can be formed using boron (B) as an impurity element imparting p-type conductivity. Note that a thin film transistor (TFT) is used as the semiconductor element. When an impurity element is added using the conductive layer 208 having a taper, high-concentration impurity regions 213 and 216 and low-concentration impurity regions 214 and 215 can be formed below the taper.

Silicide may be formed on the surface of the impurity region. By forming silicide, the resistance between the source and the drain can be lowered. Improvement in mobility is expected due to a decrease in resistance between the source and drain.

As shown in FIG. 11E, an insulating layer 218 functioning as an interlayer film is formed so as to cover the conductive layer 208, the insulating layer 206, and the silicon layer 202 in the first region 251. The insulating layer 218 can have a single-layer structure or a stacked structure, and can be formed using an insulating inorganic material, an organic material, or the like. As the inorganic material, silicon oxide or silicon nitride can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. When an inorganic material is used, entry of an impurity element can be prevented, and when an organic material is used, flatness can be improved.

Then, a wiring 219 connected to the impurity region is formed. The wiring 219 is called a source wiring when connected to the source region, and is called a drain wiring when connected to the drain region. For the wiring 219, a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or silicon (Si) or an alloy film containing these elements is used. it can. The wiring 219 can have a single layer structure or a stacked structure. For example, a tungsten film, a tungsten nitride film, or the like is used for the first layer, and an alloy of aluminum and silicon (Al—Si) film, aluminum and titanium is used for the second layer. A structure in which a titanium nitride film, a titanium film, and the like are sequentially stacked on the third layer can be applied. The wiring 219 can be manufactured by a CVD method or a sputtering method.

The wiring 219 can be connected to a cantilever microstructure. Specifically, the wiring 219 can be connected to the conductive layer 208 which is a structural layer.

As shown in FIG. 11F, the silicon layer to be the sacrificial layer 204 is removed. A wet etching method or a dry etching method can be applied to the removal of the sacrificial layer. For details, the above embodiment can be referred to.

Thereafter, packaging can be performed as required. For example, a protective film containing silicon nitride or silicon oxide can be formed in the first region 215 in order to prevent moisture and impurity elements from entering.

In this manner, the cantilever microstructure and the semiconductor element for controlling the microstructure can be formed on the same surface.

Since the cantilever microstructure of the present invention can be integrally formed with a semiconductor element formed over an insulating substrate, poor connection between the cantilever microstructure and the semiconductor element can be reduced, and mass productivity can be increased. .

The cantilever microstructure shown in this embodiment can be used as an AFM needle, G sensor / angular velocity sensor in addition to a switch.

This embodiment can be freely combined with the above embodiment.

(Embodiment 8)
In this embodiment, a structure for sealing a microstructure is described.

As shown in FIG. 17A, the semiconductor elements 253 and 254 are formed over the insulating substrate 100 in the first region 251 and the insulating substrate 100 is formed in the second region 252 as in FIG. Then, a sacrificial layer 204 and a structural layer 209 are formed.

As shown in FIG. 17B, an insulating layer 218 is formed in the first region 251, and an insulating layer 231 is formed in the second region 252. The insulating layer 231 can be manufactured using a material and a method similar to those of the insulating layer 218, but a material having a different etching ratio with respect to a specific etching agent is used. This is because only the insulating layer 231 is selectively removed. Next, a wiring 219 connected to the impurity region is formed across the first region 251 and the second region 252. In this manner, the insulating layer 231 and the wiring 219 are formed above the sacrificial layer 204 and the structural layer 209. At this time, the structural layer 209 and the semiconductor elements 253 and 254 can be electrically connected. For example, the structural layer 209 and the semiconductor elements 253 and 254 are electrically connected using the same material as the wiring 219.

Then, an opening 230 is formed in the wiring 219 in the second region 252. The opening 230 can be formed using a wet etching method or a dry etching method. At this time, an etchant that can selectively remove the wiring 219 is used.

As shown in FIG. 17C, an etchant is introduced from the opening 230 and the insulating layer 231 is removed. For the removal of the insulating layer 231, a wet etching method or a dry etching method can be used.

At this time, a mask 234 is preferably provided in the first region 251 in order to prevent the insulating layer 218 and the wiring 219 from being exposed to the etching agent. The mask 234 can be formed using a material and a method similar to those of the mask 103.

Then, as shown in FIG. 17D, the sacrificial layer 204 is removed. By removing the sacrificial layer 204, a space 236 is created. For the removal of the sacrificial layer 204, a wet etching method or a dry etching method can be used.

The insulating layer 231 and the sacrificial layer 204 may be removed in the same step. For example, by forming the insulating layer 231 and the sacrificial layer 204 from a material that reacts with the same etchant, the insulating layer 231 and the sacrificial layer 204 can be removed in the same step. By removing in the same process, time can be shortened and cost can be reduced.

As shown in FIG. 17E, a protective film 237 is formed. The protective film 237 can be manufactured using the same material and method as the insulating layer 218. The protective film 237 can be formed so as to enter the opening 230, but there is no risk of entering the spaces 233 and 236 by reducing the diameter of the opening 230. In order to fill the spaces 233 and 236 with an inert gas, a protective film 237 is formed in an inert gas atmosphere. There is nitrogen gas as an inert gas.

In this way, the microstructure and the semiconductor element can be integrally formed and further sealed. The sealed microstructure and semiconductor element can increase mechanical strength and can be easily carried. In addition, the sealed microstructure and semiconductor element are easy to handle when mounted on another device.

This embodiment can be freely combined with the above embodiment.

(Embodiment 9)
In the above embodiment mode, a manufacturing method in which a semiconductor element and a microstructure are formed over the same insulating substrate has been described; however, the semiconductor element and the microstructure may be stacked. Therefore, in this embodiment, a manufacturing method in the case where a microstructure is stacked over a semiconductor element will be described.

As shown in FIG. 20A, semiconductor elements 253 and 254 are formed over the insulating substrate 100 as in the first region 251 in FIG. Then, as in FIG. 17C, the insulating layer 235 is formed so as to cover the insulating layer 218.

As shown in FIG. 20B, a contact hole is formed in the insulating layer 235, and an electrode 240 connected to the wiring 219 is formed. The material and method of the electrode 240 are the same as those of the wiring 219. The electrode 240 can be used as an electrode for controlling the microstructure.

As shown in FIG. 20C, a sacrificial layer 241 is formed so as to cover the electrode 240. The sacrificial layer 241 can be manufactured using the same material and method as the sacrificial layer 101.

As shown in FIG. 20D, a microstructure 242 is formed so as to cover at least part of the sacrifice layer 241. The microstructure 242 can be manufactured using a material and a method similar to those of the structural layer 209.

As shown in FIG. 20E, the sacrificial layer 241 is removed. A wet etching method or a dry etching method can be applied to the removal of the sacrificial layer. As a result of removing the sacrificial layer 241, a space 243 is created.

In this manner, the semiconductor element and the microstructure can be stacked.

This embodiment can be freely combined with the above embodiment.

(Embodiment 10)
In this embodiment, a method for forming a semiconductor element and a microstructure over the same surface using a bottom-gate thin film transistor in which a gate electrode is provided below a semiconductor film in the semiconductor element will be described.

As in the above embodiment, an insulating substrate 100 is prepared and a conductive layer is formed. The conductive layer is processed into a predetermined shape, and a gate electrode is formed in the first region 251 and a sacrificial layer is formed in the second region 252.

Then, a silicon layer is formed so as to cover the gate electrode and the sacrificial layer. The silicon layer is processed into a predetermined shape, and a semiconductor layer is formed in the first region 251 and a structural layer is formed in the second region 252. The silicon layer can be formed in a manner similar to that in the above embodiment mode, and in order to impart conductivity, silicidation or addition of impurities may be performed. Similar to the above-described embodiment, the structural layer is provided with only one side beyond the end surface of the sacrificial layer and the other side is shorter than the end surface of the sacrificial layer. It is processed into a rectangular shape so as to be narrower.

After that, in the first region 251, a semiconductor layer having an impurity element, a source wiring, and a drain wiring are formed, and a protective film made of silicon oxide or silicon nitride is formed as necessary. The source wiring and the drain wiring can be formed in the same manner as in the above embodiment mode. At this time, the second region 252 is covered with a mask.

The mask in the second region 252 is removed, and the sacrificial layer is removed. At this time, in order to selectively remove the sacrificial layer, when the first region 251 is provided with a mask or covered with a protective film, a material having a selection ratio to the sacrificial layer is used for the mask or the protective film.

In this way, the bottom gate type and the microstructure can be formed on the same surface.

The materials of the sacrificial layer and the structural layer are not limited to the conductive layer and the silicon layer, respectively. For example, the lower electrode may be formed using a conductive layer serving as a gate electrode, the sacrificial layer may be formed using a silicon layer, and the structural layer may be formed using a conductive layer serving as a source wiring and a drain wiring.

Since the structural layer is formed using a conductive layer, it is suitable for application to a cantilever switch.

(Embodiment 11)
In this embodiment mode, a mode in which a cantilever microstructure and a semiconductor element are transferred to a resin substrate such as a plastic substrate will be described.

As shown in FIG. 14A, the insulating layer 218 is formed as in the above embodiment mode. In the second region 252, the mask 212 is provided. Then, the insulating substrate 100 is peeled off. As a means for peeling, there is a method in which a peeling layer is provided between the insulating substrate 100 and the base layer 201 and the peeling layer is physically or chemically removed.

In order to remove physically, the adhesion state with the insulating substrate 100 is weakened by controlling the crystal state of the peeling layer, and the insulating substrate 100 is peeled off by applying a force. Tungsten oxide or molybdenum oxide can be used for such a peeling layer, and the crystal state can be controlled by heat treatment.

In order to remove chemically, an opening penetrating the peeling layer is formed, an etching agent is introduced, the peeling layer is removed, and the insulating substrate 100 is peeled off. A silicon layer or a tungsten layer can be used as such a peeling layer, and chlorine trifluoride (ClF ₃ ), nitrogen trifluoride (NF ₃ ), bromine trifluoride (BrF ₃ ), fluorine, or the like is used as an etchant. A halogen fluoride such as hydrogen fluoride (HF) can be used.

Of course, a combination of physical means and chemical means may be applied.

As shown in FIG. 14B, a resin substrate 256 such as a plastic substrate is attached to the base layer 201 using an adhesive layer 255. For the adhesive layer 255, an ultraviolet curable resin, a thermosetting resin, or the like can be used.

As shown in FIG. 14C, the mask 212 is removed as in the above embodiment, a wiring 219 is formed, and the silicon layer which becomes the sacrificial layer 204 is removed.

In this manner, a cantilever microstructure and a semiconductor element that are transferred to a resin substrate can be formed. Further weight reduction and thickness reduction can be achieved by transferring the resin substrate.

This embodiment can be freely combined with the above embodiment.

(Embodiment 12)
Conventionally, when handling minute objects such as millimeters or less, first the structure of a minute object is expanded, and a human or computer obtains the information to determine information processing and operation, and then reduces the operation. It needed a process of communicating to minute objects.

However, the cantilever microstructure of the present invention can handle minute objects simply by a human or computer transmitting a superordinate conceptual command. That is, when a person or a computer determines a purpose and transmits a command, the cantilever microstructure can obtain information on the object using a sensor or the like, perform information processing, and take an action. Although it is assumed that the object is very small, for example, the object itself has a size in meters, but a minute signal (for example, a minute change in light or pressure) emitted from the object. ) Etc. are also included.

The cantilever microstructure of the present invention belongs to the field of micromachines, and can have a size from micrometer to millimeter. When manufactured to be incorporated as a part of a mechanical device, the cantilever microstructure may have a metric size for ease of handling during assembly.

In this embodiment, a structure example of the above-described cantilever microstructure is described with reference to a block diagram.

FIG. 9 shows a conceptual diagram of a microelectromechanical device having a cantilever microstructure. The microelectromechanical device 11 of the present invention includes an electric circuit portion 12 having a semiconductor element and a structure portion 13 having a microstructure. The electric circuit unit 12 includes a control circuit 14 that controls the microstructure, an interface 15 that communicates with the external control device 10, and the like. The structure body portion 13 includes a sensor 16, an actuator 17, a switch, and the like by a microstructure. An actuator means a component that converts a signal (mainly an electrical signal) into a physical quantity.

The electric circuit unit 12 may include a central processing unit for processing information obtained by the structure unit 13.

The external control device 10 transmits a signal for controlling the microelectromechanical device 11, receives information obtained by the microelectromechanical device 11, or supplies driving power to the microelectromechanical device 11. Perform the action.

The present invention is characterized in that a cantilever microstructure has an electric circuit for controlling the microstructure having a semiconductor element, and the microstructure, and the other configuration is not limited to FIG. .

(Embodiment 13)
In this embodiment, a device to which a switch including a microstructure is applied will be described. A phase shifter can be formed by combining the switch of the present invention and a conduction path. The phase shifter can be mounted on a mobile phone.

A resonator can also be manufactured using the cantilever microstructure of the present invention. FIG. 21 shows a circuit diagram of the resonator. In the resonator, a coil: L, a capacitor: C, and a resistor: R are connected in series, and a capacitive element Cs1 is provided therebetween. Capacitance elements Cs2 are also provided at both ends of the coil: L and the resistance: R.

The switch of the present invention can be applied to such a phase shifter and resonator.

It is a figure showing the manufacturing process of the microstructure of the present invention It is a figure showing the manufacturing process of the microstructure of the present invention It is a figure showing the manufacturing process of the microstructure of the present invention It is a figure showing the manufacturing process of the microstructure of the present invention It is a figure showing the manufacturing process of the microstructure of the present invention It is the figure which showed the mask of this invention It is the figure which showed the mask of this invention It is the figure which showed the mask of this invention It is the block diagram which showed the microelectromechanical apparatus of this invention It is a figure showing the manufacturing process of the microstructure of the present invention It is a figure showing the manufacturing process of the microstructure of the present invention It is the figure which showed the microstructure of this invention It is a figure showing the manufacturing process of the microstructure of the present invention It is a figure showing the manufacturing process of the microstructure of the present invention It is the figure which showed the microstructure of this invention It is the figure which showed the microstructure of this invention It is a figure showing the manufacturing process of the microstructure of the present invention It is the figure which showed the microstructure of this invention It is the figure which showed the switch which applies the microstructure of this invention It is a figure showing the manufacturing process of the microstructure of the present invention It is a circuit diagram showing a resonator to which a microstructure of the present invention is applied.

Claims (14)

Forming a sacrificial layer,
Forming a first layer on the sacrificial layer;
Forming a mask having a first thickness and a second thickness on the first layer;
Using the mask, the first layer is etched to form a structural layer;
Removing the sacrificial layer provided below the structural layer;
In the structure layer, the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. A method for manufacturing a mechanical device. Forming a sacrificial layer,
Forming a first layer on the sacrificial layer;
Forming a mask having a first thickness and a second thickness on the first layer;
Using the mask, the first layer is etched to form a structural layer;
Removing the sacrificial layer provided below the structural layer;
The structural layer forms a three-dimensional structure when the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. And
The three-dimensional structure is a method of manufacturing a microelectromechanical device, wherein a portion provided under the first film thickness mask is a weight. Forming a sacrificial layer,
Forming an amorphous silicon layer on the sacrificial layer;
By crystallization using metal, the amorphous silicon layer is changed to a polycrystalline silicon layer,
Forming a mask having a first film thickness and a second film thickness on the polycrystalline silicon layer;
Using the mask, the polycrystalline silicon layer is etched to form a structural layer,
Removing the sacrificial layer provided below the structural layer;
In the structure layer, the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. A method for manufacturing a mechanical device. Forming a sacrificial layer,
Forming an amorphous silicon layer on the sacrificial layer;
By crystallization using metal, the amorphous silicon layer is changed to a polycrystalline silicon layer,
Forming a mask having a first film thickness and a second film thickness on the polycrystalline silicon layer;
Using the mask, the polycrystalline silicon layer is etched to form a structural layer,
Removing the sacrificial layer provided below the structural layer;
The structural layer forms a three-dimensional structure when the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. And
The three-dimensional structure is a method of manufacturing a microelectromechanical device, wherein a portion provided under the first film thickness mask is a weight. Forming an amorphous silicon layer;
By crystallization using a metal, a sacrificial layer having the amorphous silicon layer as a polycrystalline silicon layer is formed,
Forming a first layer on the sacrificial layer;
Forming a mask having a first thickness and a second thickness on the first layer;
Using the mask, the first layer is etched to form a structural layer;
Removing the sacrificial layer provided below the structural layer;
In the structure layer, the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. A method for manufacturing a mechanical device. Forming an amorphous silicon layer;
By crystallization using a metal, a sacrificial layer having the amorphous silicon layer as a polycrystalline silicon layer is formed,
Forming a first layer on the sacrificial layer;
Forming a mask having a first thickness and a second thickness on the first layer;
Using the mask, the first layer is etched to form a structural layer;
Removing the sacrificial layer provided below the structural layer;
The structural layer forms a three-dimensional structure when the thickness of the portion provided under the second film thickness mask is smaller than the thickness of the portion provided under the first film thickness mask. And
The three-dimensional structure is a method of manufacturing a microelectromechanical device, wherein a portion provided under the first film thickness mask is a weight. In any one of Claims 1 thru | or 6,
The method of manufacturing a microelectromechanical device, wherein the thickness of the second film thickness mask is smaller than the thickness of the first film thickness mask. In any one of Claims 1 thru | or 7,
The second film thickness of the mask is produced by using a photomask or a reticle having an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film. Manufacturing method. In any one of Claims 1 thru | or 8,
The first film thickness of the mask is formed using a photomask or reticle having a mask pattern that does not intentionally vary the film thickness,
The second film thickness of the mask is formed by using a photomask or a reticle having a mask pattern in which the film thickness is intentionally changed with a photomask or a reticle. Method. Forming a semiconductor layer to be a semiconductor element in a first region on an insulating substrate and a sacrificial layer in a second region;
Forming a conductive layer on the semiconductor layer and the sacrificial layer;
Forming a first mask and a second mask having a first film thickness and a second film thickness on the conductive layer;
The conductive layer is etched using the first mask and the second mask to form a gate electrode of a semiconductor element in the first region, and a structural layer is formed in the second region. Forming,
Forming an impurity region in the semiconductor layer using the gate electrode;
Forming a wiring connected to the impurity region and the structural layer;
Removing the sacrificial layer provided below the conductive layer in the second region;
The structural layer formed in the second region has the thickness of the conductive layer provided under the second film thickness mask of the conductive layer provided under the first film thickness mask. A method for manufacturing a microelectromechanical device, characterized by being made thinner than a thickness. Forming a semiconductor layer to be a semiconductor element in a first region on an insulating substrate and a sacrificial layer in a second region;
Forming a conductive layer on the semiconductor layer and the sacrificial layer;
Forming a first mask and a second mask having a first film thickness and a second film thickness on the conductive layer;
The conductive layer is etched using the first mask and the second mask to form a gate electrode of a semiconductor element in the first region, and a structural layer is formed in the second region. Forming,
Forming an impurity region in the semiconductor layer using the gate electrode;
Forming a wiring connected to the impurity region and the structural layer;
Removing the sacrificial layer provided below the conductive layer in the second region;
The structural layer formed in the second region has the thickness of the conductive layer provided under the second film thickness mask of the conductive layer provided under the first film thickness mask. A method for manufacturing a microelectromechanical device, characterized in that a three-dimensional structure is formed with a structure layer provided under a mask having the first film thickness as a weight, the thickness being smaller than the thickness. In claim 10 or claim 11,
The second film thickness of the first mask is thinner than the first film thickness of the first mask,
The method for manufacturing a micro electro mechanical device, wherein the second film thickness of the second mask is smaller than the first film thickness of the second mask. In any one of Claims 10 to 12,
The second film thickness of the first mask and the second mask is formed using a photomask or a reticle having an auxiliary pattern having a light intensity reducing function made of a diffraction grating pattern or a semi-transmissive film. A method for manufacturing a microelectromechanical device. In any one of Claims 10 thru | or 13,
The first film thickness of the first mask and the second mask is formed using a photomask or a reticle having a mask pattern in which the film thickness is not intentionally different,
The second film thickness of the first mask and the second mask is formed by using a photomask or a reticle having a mask pattern in which the film thickness is intentionally changed by a photomask or a reticle. A method for manufacturing a microelectromechanical device.

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