JP4587320B2 - Microstructure, micromachine, and manufacturing method thereof - Google Patents

Description

The present invention relates to a microstructure, a micromachine including the microstructure, an organic transistor including the microstructure, and an electronic device including the organic transistor. Furthermore, the present invention relates to these manufacturing methods.

In recent years, research on micro mechanical systems called MEMS has been actively conducted. MEMS (Micro Electro Mechanical System) is an abbreviation for a microelectromechanical system, and is sometimes simply called a micromachine. A micromachine generally refers to a microdevice in which “a microstructure having a three-dimensional structure and a movable microstructure” and “an electronic circuit having a semiconductor element” are integrated using a semiconductor microfabrication technique. Unlike the semiconductor element, the microstructure has a three-dimensional structure and has a movable portion.

In addition, there has been proposed a technology for micromechanical devices provided on a semiconductor substrate, in which various devices are simultaneously formed in the same substrate (for example, see Patent Document 1).

A configuration using a thin film has been proposed for such a micromachine (see, for example, Patent Document 2).
JP 2002-355798 A Japanese Patent Application Laid-Open No. 2004-1201

As in Patent Document 1, a micromachine is generally formed using a semiconductor substrate such as a silicon wafer.

Patent Document 1 discloses a form in which a micropump and its drive circuit are mounted on the same substrate. However, forming on the same substrate by the same process is not disclosed. Further, Patent Document 1 discloses that a diaphragm pump is integrally formed on the same substrate as a sample or a pump in a micromixer or the like, and the structure can be formed by the same process. It is disclosed that it is easy to create simultaneously in a substrate. However, forming a semiconductor element for controlling a device such as a micromixer on the same substrate by the same process is not described.

Patent Document 2 describes the structure of a thin-film crystallized micromachine. However, there is no description of a semiconductor element for controlling the micromachine, and of course there is no description of a device in which the semiconductor element is integrally formed.

In view of the above problems, an object of the present invention is to provide a microstructure having a new structure having a frame shape. Furthermore, the present invention provides a microstructure with a new structure, a micromachine having the microstructure, an organic transistor having the microstructure, and a method for manufacturing an electronic device having the microstructure.

Furthermore, the present invention provides a method for integrally forming a microstructure and a semiconductor element that controls the microstructure on the same insulating surface in the same process.

The specific configuration of the present invention is shown below.

One embodiment of the present invention includes a first layer and a second layer provided on an insulating surface, and the first layer is a pair of wall surfaces, and the second layer is a wall surface. It is a micro structure characterized by being a bridge body bridged between. Such a second layer can be movable.

Another embodiment of the present invention includes a first layer and a second layer provided on the edge surface. The first layer has a frame shape, and the second layer is a frame. A microstructure is provided over the top, and a space below the second layer is provided in the frame. Such a second layer can be movable.

Another embodiment of the present invention includes a first layer and a second layer provided on an insulating surface, the first layer has a frame shape, and the second layer is a frame layer. A microstructure provided above from one side to the other side opposite to the one side, and having a space provided in the frame below the second layer and in contact with a side surface of the frame It is. Such a second layer can be movable.

Another embodiment of the present invention is a micromachine including a plurality of microstructures each including a first layer and a second layer provided on an insulating surface, and the first layer is a pair of wall surfaces. The second layer is a micromachine characterized in that a bridge body is bridged between wall surface bodies. Such a second layer can be movable.

Another embodiment of the present invention is a micromachine including a plurality of microstructures each including a first layer and a second layer provided over an insulating surface, and the first layer has a frame shape. The micromachine is characterized in that the second layer is provided over the frame, and the second layer has a space provided in the frame under the second layer. Such a second layer can be movable.

Another embodiment of the present invention is a micromachine including a plurality of microstructures each including a first layer and a second layer provided over an insulating surface, and the first layer has a frame shape. The second layer is provided above the frame from one side to the other side opposite to the one side, and below the second layer has a space provided in the frame, and the side surface of the frame. It is a micromachine characterized by contact. Such a second layer can be movable.

Another embodiment of the present invention is a micromachine including a plurality of microstructures each including a conductive layer provided on an insulating surface, a first layer, and a second layer, and the first machine is provided above the conductive layer. The first layer has a frame shape, the second layer is provided over the frame, and the second layer is provided in the frame below the second layer. It is a micromachine characterized by having a space. Such a second layer can be movable.

The micromachine of the present invention includes a semiconductor element formed over the insulating surface in the same process as the microstructure.

Another embodiment of the present invention includes a first layer and a second layer provided on an insulating surface, the first layer is a pair of wall surfaces, and the second layer is a wall surface. It is a bridge body bridged between bodies, and is an organic transistor characterized by having an organic semiconductor layer provided inside the wall surface body and below the bridge body.

Another embodiment of the present invention includes a first layer provided on the insulating surface, a second layer, and a conductive layer provided below the first layer. It has a frame shape, the second layer is provided over the frame, the lower part of the second layer has a space provided in the frame, and an organic semiconductor layer provided in the space This is an organic transistor.

Another embodiment of the present invention includes a first layer provided on the insulating surface, a second layer, and a conductive layer provided below the first layer. It has a frame shape, the second layer is provided over the frame, and the second layer has a space provided in the frame, and has an organic semiconductor layer provided in the space. The second layer is an organic transistor made of a conductive material.

Another embodiment of the present invention includes a conductive layer provided on an insulating surface, a first layer provided above the conductive layer, and a second layer, and the first layer has a frame shape. The second layer is provided over the frame, the second layer has a space provided in the frame, an organic semiconductor layer provided in the space, The second layer is an organic transistor characterized by being made of a conductive material.

Another embodiment of the present invention includes a first layer and a second layer provided on an insulating surface, the first layer is a pair of wall surfaces, and the second layer is a wall surface. An electronic apparatus comprising an organic transistor having an organic semiconductor layer that is a bridge body that is bridged between bodies and that is inside a wall body and is provided below the bridge body. For example, in an electronic device, the organic transistor can be used as a switching element of a display portion.

Another embodiment of the present invention includes a first layer and a second layer provided on an insulating surface, the first layer has a frame shape, and the second layer is a frame layer. An electronic device including an organic transistor having an organic semiconductor layer provided in an upper portion of the frame and having a space provided in a frame below the second layer. For example, in an electronic device, the organic transistor can be used as a switching element of a display portion.

Another embodiment of the present invention includes a first layer provided on the insulating surface, a second layer, and a conductive layer provided below the first layer. It has a frame shape, the second layer is provided over the frame, and the second layer has a space provided in the frame, and has an organic semiconductor layer provided in the space. The second layer is an electronic device having an organic transistor made of a conductive material. For example, in an electronic device, the organic transistor can be used as a switching element of a display portion.

Another embodiment of the present invention includes a conductive layer provided on an insulating surface, a first layer provided above the conductive layer, and a second layer, and the first layer has a frame shape. The second layer is provided over the frame, the second layer has a space provided in the frame, an organic semiconductor layer provided in the space, The second layer is an electronic device having an organic transistor made of a conductive material. For example, in an electronic device, the organic transistor can be used as a switching element of a display portion.

A microstructure having a shape of a frame provided on the edge surface can be provided. Since the microstructure of the present invention has a frame shape, the translucency is high. Therefore, by applying this as a switch element of the display portion, a display portion with a high aperture ratio can be provided.

According to the present invention in which a microstructure and a semiconductor element that controls the microstructure are integrally formed on the same surface in the same process, a micromachine that can be manufactured at low cost can be provided.

Further, it is not necessary to provide a connection region between the microstructure and a semiconductor element that controls the microstructure, and it is possible to achieve downsizing of a sensor device or the like equipped with a micromachine.

Further, by integrally forming on the same surface, microstructures can be arrayed, and a device integrated on a large scale can be provided.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structure of a microstructure is described.

As shown in FIG. 1, the microstructure of the present invention includes a first layer 102 provided in the shape of a frame on an insulating surface 101. In other words, the frame formed of the first layer 102 can be expressed as two pairs of wall surfaces. Note that since the space 105 may be formed below the second layer 102, the frame that supports the second layer 102 only needs to have at least two opposing sides. That is, it is sufficient that at least one pair of wall surfaces is formed.

A space is provided in the frame formed of the first layer 102. It can also be expressed that the space is provided so as to be surrounded by a frame. The insulating surface is a surface of a glass substrate, a quartz substrate, a plastic substrate, or the like. By forming a microstructure on a plastic substrate, a highly flexible and thin device can be formed. For example, the glass substrate may be thinned by polishing or the like. By polishing in this way, a thin device can be formed. Furthermore, the microstructure of the present invention can be formed over a conductive substrate such as a metal or a substrate in which an insulating layer (insulating layer) is formed over a semiconductor substrate such as silicon.

The first layer 102 can be formed from an insulator including silicon. For example, it can be formed from an oxide containing silicon (silicon oxide) or a nitride containing silicon (silicon nitride), and can have a single-layer structure or a stacked structure.

A second layer 103 is provided over the first layer 102 having such a frame shape. In other words, the second layer 103 can be expressed as a bridge body, that is, a bridge body bridged between a pair of wall surfaces. The second layer 103 can be formed using an insulator containing silicon or a conductor, and can have a single-layer structure or a stacked structure. A material used for the electrode is suitable for the conductor. For example, a metal material such as titanium (Ti) aluminum (Al), molybdenum (Mo), tungsten (W), or a compound of the metal material (metal oxide or metal) Nitride). An element such as neodymium (Nd) or scandium (Sc) is preferably added to a material having low heat resistance such as aluminum (Al) in order to prevent hillocks due to heating or the like. Note that neodymium is preferable as an additive material because it does not increase the resistivity of aluminum as compared with scandium.

A method for manufacturing such a microstructure will be described with reference to FIGS.

First, as shown in FIG. 2A, a sacrificial layer 104 is formed on an insulating surface and patterned into a predetermined shape. Note that the sacrificial layer refers to a layer that is removed in a later step. By removing such a sacrificial layer, a space for moving the structural layer is provided. Therefore, the sacrificial layer only needs to be removed, and may be a conductive layer or an insulating layer as long as it is a material that can have an etching selectivity with other materials.

Thereafter, as shown in FIG. 2B, a first layer 106 made of silicon oxide, silicon nitride, or the like is formed over the sacrificial layer 104. Silicon oxide, silicon nitride, or the like can be formed by a CVD method, a sputtering method, a droplet discharge method (typically, an inkjet method), or a spin coating method. The droplet discharge method and the spin coating method can be used when the starting material is an organic material.

At this time, unevenness may be formed on the surface of the first layer 106 along the shape of the sacrificial layer 104. However, when an organic material is used as a starting material for the first layer 106, unevenness is hardly formed, and flatness can be improved.

Then, as shown in FIG. 2C, etching is performed so that the first layer remains only on the side surface of the sacrificial layer 104 and has a frame shape. As the etching, dry etching or wet etching can be applied. In the case of dry etching, an etching gas containing CHF ₃ , ClF ₃ , NH ₃ , CF _4, or the like can be used. In the case of wet etching, an etchant containing hydrogen peroxide solution or an etchant containing buffered hydrofluoric acid can be used. For the etching, anisotropic etching is preferably used.

As described above, the first layer remaining only on the side surface exists around the sacrificial layer 104 and has a frame shape. This can be called a sidewall structure, and the frame is narrowed toward the tip thereof, and the lower surface side is thick. Therefore, the strength of the frame can be increased. Note that in the first layer 102 having a sidewall structure, the thickness and height of the sidewall portion can be determined by the etching conditions depending on the thickness of the first layer when it is formed.

Next, a second layer 103 is formed so as to cover the first layer 102 and the sacrificial layer 104, and is patterned into a predetermined shape. In this embodiment mode, as shown in FIG. 1, the second layer 103 is patterned into an elongated rectangular shape that extends over the first layer 102 and the sacrificial layer 104. That is, the second layer 103 is a bridge body that is selectively formed above the first layer 102 and the sacrificial layer 104. In the present embodiment, the second layer 103, that is, the bridge body, extends to the outside of the first layer 102 having a frame shape. By extending to the outside, the strength of the second layer 102 can be increased.

Since the second layer 103 is selectively formed, the sacrificial layer 104 has an exposed region. The exposed sacrificial layer 104 can be removed by etching. That is, it is desirable that the second layer 103 be formed so as to have a region where the sacrificial layer 104 is exposed.

Thereafter, the sacrificial layer 104 is removed as shown in FIG. Dry etching or wet etching can be applied to the removal of the sacrificial layer 104. Further, only the sacrificial layer 104 may be selectively removed, and the materials of the first layer 102, the second layer 103, and the sacrificial layer 104 may be satisfied. Also, the etching conditions should satisfy this. That is, the first layer 102 and the second layer 103 are made of materials that can have a selectivity with respect to the sacrificial layer 104 with respect to a specific etching agent.

By removing the sacrificial layer 104, a space 105 is created. In other words, the space 105 is provided inside the first layer 102 provided in the shape of a frame. The shape of this frame can be expressed as two pairs of wall surfaces. Note that since the space 105 may be formed below the second layer 102, the frame that supports the second layer 102 only needs to have at least two opposing sides. That is, it is sufficient that at least one pair of wall surfaces is formed. Therefore, it is not necessary to etch away all the sacrificial layer 104 inside the frame, and the sacrificial layer 104 may remain on the bottom side of the frame. In other words, it is sufficient that a space can be formed by etching the sacrificial layer 104.

In this way, the first layer includes the first layer having the shape of a frame, the second layer having the shape of a bridge body provided over the frame, and the lower portion of the second layer. And the microstructure which has the space provided in the frame can be formed. The second layer provided in the space can be moved by, for example, an electric signal or static electricity generated by applying a voltage to the second layer. The second layer can move (or vibrate) up and down, for example.

Such a frame can be used as a mold for pouring and baking a material that is difficult to process. For example, ZnO, which is difficult to etch, or an organic material that is weak against heat can be poured in and provided as a new device.

It is also possible to make a mirror surface by electroplating the frame. Such an apparatus can be used as an optical device.

Further, such a frame made of the first layer enables finer processing than patterning by normal etching.

A micromachine integrated with a large scale by providing a plurality of such microstructures can be provided. A micromachine having a specific function can be provided by a large-scale integrated device.

(Embodiment 2)
In this embodiment, a structure of a measurement element such as a sensor element or a detection element using the microstructure is described.

As shown in FIG. 3, in the microstructure as described above, a conductor (which will be referred to as a lower electrode hereinafter, because it functions as a lower electrode) 110 is formed below the sacrificial layer, and patterned into a predetermined shape. . The lower electrode 110 can be formed from a metal material such as titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), or a compound (metal oxide or metal nitride) of the metal material. . An element such as neodymium (Nd) or scandium (Sc) is preferably added to a material having low heat resistance such as aluminum (Al) in order to prevent hillocks due to heating or the like. Neodymium is preferable as an additive material without increasing the resistivity of aluminum as compared with scandium.

Then, a sacrificial layer is formed on the lower electrode 110 in the same manner as in the above embodiment, and is patterned into a predetermined shape.

Next, a first layer is formed over the sacrificial layer in the same manner as in the above embodiment, and etching is performed to form a sidewall structure.

Further, a second layer is formed over the first layer and the sacrificial layer. In this embodiment, the conductive layer 112 is used as the second layer. For the conductive layer 112, a metal material such as titanium (Ti), aluminum (Al), molybdenum (Mo), or tungsten (W), or a compound of the metal material (metal oxide or metal nitride) can be used. . An element such as neodymium (Nd) or scandium (Sc) is preferably added to a material having low heat resistance such as aluminum (Al) in order to prevent hillocks due to heating or the like. Neodymium is preferable as an additive material without increasing the resistivity of aluminum as compared with scandium.

In this structure, an insulating layer may be provided below the conductive layer. As the insulating layer, silicon oxide, silicon nitride, or the like is used, and the conductive layer 112 is patterned in the same manner as the above embodiment. At this time, patterning may be performed so as to form a region where the sacrificial layer is exposed.

After that, as in the above embodiment mode, the sacrificial layer is removed, and the first layer 102 having a sidewall structure and the conductive layer 112 are provided thereabove. Since the sacrificial layer is removed, a space is provided in the first layer 102. That is, the lower electrode 110 and the conductive layer 112 form a capacitance with the space interposed therebetween. Since the conductive layer 112 can move, specifically, the conductive layer 112 in the space can move up and down, the value of the capacitance varies.

By reading this fluctuating value, it can function as a measuring element. That is, such a microstructure is an element capable of measuring a variable capacitance. A sensor device provided with a sensor circuit for forming a plurality of such measurement elements and detecting a variable capacitance can be provided.

The microstructure of the present invention can be manufactured at a lower cost than when a silicon wafer is used. Further, as shown in the following embodiment mode, it can be formed over the same substrate as the semiconductor element that controls the microstructure. Such a microstructure of the present invention can reduce the cost of the measuring element and the sensor device.

A plurality of such measuring elements can be provided, and a micromachine integrated on a large scale can be provided. A micromachine having a specific function can be provided by a large-scale integrated device.

(Embodiment 3)
In this embodiment, a structure of an element which is different from that in the above embodiment is described.

In the microstructure shown in FIG. 1, the second layer 103 is used as a filament (also referred to as a fuse), and the microstructure of the present invention can be applied to a protection circuit. When an excessive voltage is applied to the second layer 103, the second layer 103 is disconnected, so that it can be applied as a protection circuit. Even if not cut, if a difference occurs in the physical characteristics of the second layer 103 due to the current flowing in the second layer 103, it can be applied as a protection circuit by using this characteristic change. In addition, a nonvolatile memory can be formed by using a filament (fuse) for a memory element.

In the case of application as such a protection circuit, the second layer 103 is preferably formed using a conductor.
(Embodiment 4)
In this embodiment, a structure of a measurement element different from that in the above embodiment will be described.

As shown in FIG. 14A, the first layer 102 having a sidewall structure on the insulating surface 101, the needle 150 provided in the space, and the stacked second layer 103 (lower layer 103a, upper layer 103b). ). The lower layer 103a and the upper layer 103b of the second layer are stacked using materials having different thermal conductivities.

At a certain ambient temperature, the tip of the needle 150 is in contact with the lower layer 103a of the second layer.

Next, at another ambient temperature, as shown in FIG. 14B, the tip of the needle 150 is separated from the lower layer 103a of the second layer. This is because the second layer is warped because the lower layer 103a of the second layer and the upper layer 103b have different thermal conductivities. In addition, since a space is provided below the second layer, the second layer can be warped.

Such a property can be used as a switching element.

(Embodiment 5)
In this embodiment mode, a manufacturing process of a semiconductor device including the measurement element and a semiconductor element that controls the measurement element will be described. In this embodiment, the case where a thin film transistor (TFT) is used as a semiconductor element will be described.

As shown in FIG. 4A, the lower electrode 110 is formed over the insulating surface 101. The above embodiment mode can be referred to for a manufacturing method, a material, and the like of the lower electrode 110. In this embodiment mode, the lower electrode 110 is formed over a first region where a microstructure is formed and a second region where a semiconductor element is formed. In the first region and the second region, the lower electrode 110 is processed, that is, patterned into a predetermined shape, and functions as a lower electrode of the measurement element and a lower electrode of the semiconductor element, respectively. By providing the lower electrode of the semiconductor element, it is possible to reduce the leakage current accompanying the miniaturization of the semiconductor element.

Next, a base film 114 is formed on the lower electrode 110. As the base film 114, an insulating layer such as an oxide including silicon or a nitride including silicon, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer can be formed with a single layer or a stacked structure. The stacked structure includes, for example, a silicon oxynitride layer formed using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as a reaction gas, and a silicon oxynitride layer formed using SiH ₄ and N ₂ O as a reaction gas in this order. The formed structure can be applied. Such a base film 114 can prevent contamination from the insulating surface 101 and the like. In addition, a stacked structure is preferable because the layer with high contamination prevention and a layer with high adhesion to the lower electrode 110 and a semiconductor layer to be formed later can be stacked.

Then, the semiconductor layer 113 is formed only in the second region and patterned into a predetermined shape. The semiconductor layer can be formed from a material containing silicon. Examples of the material containing silicon include a material made of silicon and a silicon germanium material having germanium in an amount of about 0.01 to 4.5 atomic%. As the semiconductor layer 113, a semiconductor layer having a crystalline state or an amorphous state can be used. In this embodiment mode, an amorphous silicon layer is formed and a polycrystalline silicon layer crystallized by heat treatment using a metal is used. For the heat treatment, a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof can be used.

In the case of using laser irradiation as the heat treatment, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. As the laser beam, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor A laser or a gold vapor laser oscillated from one or a plurality of types can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

The continuous wave fundamental laser beam and the continuous wave harmonic laser beam may be irradiated, or the continuous wave fundamental laser beam and the pulsed harmonic laser beam may be irradiated. You may do it. By irradiating a plurality of laser beams, energy can be supplemented with each other.

It is also possible to use a pulse oscillation type laser beam that oscillates the laser at an oscillation frequency that allows irradiation of the next pulse of laser light after the semiconductor layer is melted by the laser light and solidifies. it can. By oscillating the laser beam at such a frequency, crystal grains continuously grown in the scanning direction can be obtained. A specific oscillation frequency of the laser beam is 10 MHz or more, and a frequency band that is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used is used.

When a heating furnace is used as another heat treatment, the amorphous semiconductor layer is heated at 400 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 400 to 550 ° C. so that the temperature gradually increases. In the first heating process at about 400 ° C., hydrogen and the like of the amorphous semiconductor layer are generated, so that film roughness during crystallization can be reduced. Furthermore, it is preferable to form a metal that promotes crystallization, such as nickel (Ni), on the amorphous semiconductor layer because the heating temperature can be reduced. As metals, iron (Fe), rutinium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), cobalt A metal such as (Co) can also be used.

Further, in addition to the heating furnace, the polycrystalline silicon layer may be formed by performing laser irradiation as described above.

The polycrystalline silicon formed in this way is heat-treated using a metal, so that the crystal structure is almost the same as when a single crystal is used. High toughness and high mobility. This is because polycrystalline silicon with continuous grain boundaries can be produced by heat treatment using a metal. Unlike polycrystalline silicon obtained by heat treatment that does not use metal, polycrystalline silicon in which crystal grain boundaries are continuous does not break covalent bonds at the crystal grain boundaries. Therefore, the stress concentration caused by the crystal grain boundary does not occur, and as a result, the fracture stress is higher than that of polycrystalline silicon formed without using a metal. Furthermore, since the mobility of electrons is large due to continuous crystal grain boundaries, it is suitable as an element for controlling a microstructure.

Note that since the metal used for crystallization becomes a contamination source, it is desirable to remove it after crystallization. In this case, after heat treatment using a metal, a layer serving as a gettering sink is formed over the silicon layer and heated, whereby the metal can be removed or reduced. This is because the metal moves to the gettering sink by the heat treatment. A polycrystalline semiconductor layer or an amorphous semiconductor layer can be used for the gettering sink. For example, a polycrystalline semiconductor layer to which an inert element such as argon is added can be formed and used as a gettering sink. By adding an inert element, the polycrystalline semiconductor layer can be strained, and the metal can be efficiently captured by the strain. In addition, a metal can be captured by forming a semiconductor layer to which an element such as phosphorus is added.

As shown in FIG. 4B, an insulating layer 115 is formed so as to cover the semiconductor layer 113 over the first region and the second region. The insulating layer 115 functions as a gate insulating layer in the second region. Further, the insulating layer 115 in the first region may be removed. Such an insulating layer 115 can be formed of silicon oxide, silicon nitride, or the like, like the base film 114, and can have a single-layer structure or a stacked structure.

After that, a conductive layer is formed over the insulating layer 115 in the first region and the second region. The conductive layer functions as the sacrificial layer 104a in the first region and functions as the gate electrode 104b in the second region. Such a conductive layer may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. An element such as neodymium (Nd) or scandium (Sc) is preferably added to a material having low heat resistance such as aluminum (Al) in order to prevent hillocks due to heating or the like. Note that neodymium is preferable as an additive material because it does not increase the resistivity of aluminum as compared with scandium. Alternatively, a semiconductor layer typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the conductive layer functioning as the sacrificial layer 104a and the gate electrode 104b. The conductive layer can have a single layer structure or a laminated structure.

As shown in FIG. 4C, an impurity element is added to the semiconductor layer in a self-aligning manner using the gate electrode 104b. In the case of forming an n-type semiconductor element, impurity regions 117 and a channel formation region 119 are formed by adding phosphorus (P) or arsenic (As). In the case of forming a p-type semiconductor element, the impurity region 120 and the channel formation region 121 are formed by adding boron or the like. Note that the impurity region can be referred to as a source region or a drain region depending on a direction in which current flows.

At this time, the mask 116 is selectively formed so that the impurity element is not added in the first region. The mask can be formed from an inorganic material or an organic material.

Next, as shown in FIG. 4D, the mask 116 is removed, and an insulating layer 122 is formed so as to cover the sacrifice layer 104a, the gate electrode 104b, and the like. The insulating layer 122 is etched to be the first layer 102 having a sidewall structure, and the above embodiment mode can be referred to for the material and the like. That is, an inorganic material or an organic material can be used for the insulating layer 122.

As shown in FIG. 4E, the insulating layer 122 is etched to form a sidewall structure. In the first region, the first layer 102a having a sidewall structure is formed around the sacrificial layer 104a so as to have a frame shape, and in the second region, the sidewall 102b is formed around the gate electrode 104b. Is done.

In this state, an impurity element may be further added to the semiconductor layer 113. By adding an impurity element using the sidewall 102b, a low-concentration impurity region can be formed. The low-concentration impurity region can prevent the short channel effect and hot electron degradation that occur as the gate length of the semiconductor element is shortened. Such a structure is referred to as an LDD (Lightly Doped Drain) structure, and a structure in which a low concentration impurity region overlaps with a gate electrode is particularly referred to as a GOLD (Gate Overlapped Drain) structure. A p-channel thin film transistor is less likely to be deteriorated by hot carriers or has a short channel effect, and thus can have a single drain structure without a low-concentration impurity region. Therefore, as shown in FIG. 4E, the low concentration impurity region 123 is formed only in the n-type semiconductor element. At this time, the first region and the p-type semiconductor layer are provided with a mask so that an impurity element is not added.

Next, as illustrated in FIG. 5A, an insulating layer 125 is formed in the second region. The insulating layer 125 functions as an interlayer insulating layer. The insulating layer 125 can be formed using a material and a manufacturing method similar to those of the insulating layer 122. In the case where flatness is desired, an organic material is preferably used for the insulating layer 125. The insulating layer 125 functioning as an interlayer insulating layer can have a single-layer structure or a stacked structure. In the case of a stacked structure, for example, an insulating layer made of an inorganic material can be formed in the lower layer, and an insulating layer made of an organic material can be formed in the upper layer. As a result, impurity contamination can be reduced and flatness can be ensured.

As shown in FIG. 5B, a second layer 103 including a conductive layer is formed in the first region and the second region, and patterned into a predetermined shape. The first region functions as the conductive layer 103a, and the second region functions as the electrode 103b connected to the impurity region. Such an electrode can be referred to as a source electrode connected to the source region and a drain electrode connected to the drain region. The conductive layer 103a is patterned into an elongated rectangular shape over the first layer 102a and the sacrificial layer 104a as shown in the above embodiment mode.

As shown in FIG. 5C, the sacrificial layer 104a is removed in the first region. Since part of the sacrifice layer 104a is exposed by patterning the conductive layer 103a, the sacrifice layer 104a can be removed without forming an opening. Needless to say, when the sacrificial layer 104a is not exposed in the patterning of the conductive layer 103a, an opening may be formed at a predetermined position. Then, the space 105 can be formed by etching away the sacrificial layer 104a as in the above embodiment mode. A capacitor is formed by the lower electrode 110 and the conductive layer 103a through the space 105, and functions as a measurement element. In addition, the measurement element can be controlled using a semiconductor element formed over the same substrate.

In this manner, the measurement element and the semiconductor element that controls the measurement element can be manufactured on the same surface using the same process. By forming them integrally, manufacturing cost can be reduced. Further, mass productivity can be improved as compared with a structure in which an electric circuit is separately formed and electrically connected to a microstructure as in the conventional case. In addition, the connection region between the measurement element and the semiconductor element that controls the measurement element is not necessary, and the semiconductor device can be downsized.

This embodiment mode describes a manufacturing process of a semiconductor device including a measurement element and a semiconductor element that controls the measurement element. The form of the measurement element can be freely combined with any of Embodiment Modes 1 to 4 described above. it can.

(Embodiment 6)
In this embodiment, a measurement element having a structure different from that of the above embodiment and a semiconductor element that controls the measurement element will be described.

As shown in FIG. 6, the lower electrode 110 is selectively provided in the first region. That is, the lower electrode is not provided in the second region. As described above, the semiconductor element may have a structure having no lower electrode.

In addition to the top gate structure in which the gate electrode is provided above the semiconductor layer, the bottom gate structure in which the gate electrode is provided below can be applied to the configuration of the semiconductor element. When the bottom gate structure is used, the lower electrode in the first region and the lower gate electrode provided in the second region can be manufactured in the same process. For the subsequent steps, the above embodiment can be referred to.

As described above, the present invention is not limited to the structure of the semiconductor element, and it is sufficient that the measurement element and the semiconductor element can be integrally formed on the same surface.

Further, the measurement element and the semiconductor element formed on the insulating surface may be transferred to another substrate. For example, a measurement element and a semiconductor element formed using a glass substrate may be transferred to a plus chip substrate. In this case, the measurement element and the semiconductor element may be formed on the peeling layer, the peeling layer may be physically or chemically removed to peel the glass substrate, and the measurement element and the semiconductor element may be fixed on the plus chip substrate. As a result, a very light and thin device can be formed.

This embodiment mode describes a manufacturing process of a semiconductor device including a measurement element and a semiconductor element that controls the measurement element. The form of the measurement element can be freely combined with any of Embodiment Modes 1 to 4 described above. it can.

(Embodiment 7)
In this embodiment mode, a structure of an organic transistor using the above microstructure is described. In particular, in this embodiment, a top contact organic transistor in which a gate electrode is provided below a semiconductor layer and a source electrode and a drain electrode are provided above the semiconductor layer will be described. .

FIG. 7 is a perspective view of a bottom gate type organic transistor. 8A shows a top view of the organic transistor, FIG. 8B shows a cross-sectional view taken along OP, and FIG. 8C shows a cross-sectional view taken along QR. The organic transistor has a lower electrode 210 functioning as a gate electrode on an insulating surface, a first layer 202 having a side wall structure having a frame shape provided on the lower electrode 210, and a first layer 202 includes an organic semiconductor layer 215 provided in 202, and a second layer 213 that overlaps with the lower electrode 210 and functions as a source electrode and a drain electrode provided on the organic semiconductor layer 215. Since the second layer 213 functions as a source electrode and a drain electrode, the second layer 213 is separated above the lower electrode. The first layer 202 has a frame shape by forming a space by removing the sacrificial layer. In order to maintain the state of the second layer 213 from the formation of the space to the formation of the organic semiconductor layer 215, a reinforcing material may be formed. The reinforcing material can be provided below or above the second layer 213 and is preferably formed so as to have silicon oxide, silicon nitride, or the like. This is because silicon oxide, silicon nitride, and the like have higher strength than the conductive material.

An organic molecular crystal or an organic polymer compound may be used for the organic semiconductor layer 215. Specific organic molecular crystals include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, charge transfer complexes, and the like. For example, anthracene, tetracene, pentacene, hexathiophene (6T), tetracyanoquinodimethane (TCNQ), perylenetetracarboxylic dianhydride (perylenetetracarboxylic dianhydride, PTCDA), naphthalenetetracarboxylic dianhydride (naphthalenetetra) Carboxylic dianhydride, NTCDA) and the like can be used. Specific examples of the organic polymer compound include π-conjugated polymers, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, polyacetylene, polyaniline, polypyrrole, polyethylene, polythiophene derivatives, poly (3-alkylthiophene), polyparaphenylene derivatives, or polyparaphenylene vinylene derivatives, which are π-conjugated polymers whose skeleton is composed of conjugated double bonds, are used. be able to. Some of these organic semiconductor materials exhibit n-type or p-type polarity.

Such an organic semiconductor layer is manufactured using a vacuum deposition method, a spin coating method, a spray method, a droplet discharge method (typically an ink jet method), a sol-gel method, a screen method, a casting method, or a pulling method. Can do. When a dry film formation method such as a vacuum evaporation method or a vapor phase film formation method is used, it is preferable to perform a treatment for making only the region where the organic semiconductor layer is formed hydrophobic. On the other hand, when using a wet film formation method such as a spin coating method, a spray method, a droplet discharge method (typically an ink jet method), a sol-gel method, a screen method, a cast method, or a pulling method, the organic semiconductor layer is formed. It is preferable to perform a treatment in which the region other than the region to be formed becomes hydrophobic. In this manner, the organic semiconductor layer 215 can be formed only in the first layer 202 having a frame shape.

The organic semiconductor layer 215 formed using a wet film formation method is dried over a predetermined temperature and time. Then, by using a capillary phenomenon when the organic semiconductor layer 215 is dried, the organic semiconductor layer 215 can be brought into contact with the second layer 212 functioning as a source electrode and a drain electrode. In other words, before the organic semiconductor layer 215 is dried, the organic semiconductor layer 215 may not be in contact with the second layer 212 functioning as a source electrode and a drain electrode.

The organic semiconductor layer 215 formed in this manner does not require heat treatment for crystallization. Therefore, an organic transistor can be formed even with a substrate having low heat resistance such as a plus chip substrate.

Such an organic semiconductor layer 215 is provided in the first layer 202 having a frame shape, and thus does not require patterning. Therefore, the present invention is suitable because it can be used as a mold for pouring and baking a material that is difficult to pattern (for example, ZnO that is difficult to etch or an organic material that is weak against heat).

In addition, although it demonstrated using the top contact type organic transistor, the bottom contact type organic transistor in which a source electrode and a drain electrode are below a semiconductor layer may be sufficient. In this case, a lower electrode 210 that functions as a gate electrode is formed, an insulating layer that functions as a gate insulating layer is formed so as to cover the lower electrode 210, and an electrode that functions as a source electrode and a drain electrode is formed. A first layer 202 having a sacrificial layer and a sidewall structure and having a frame shape is formed. Then, after removing the sacrificial layer, an organic semiconductor layer is provided in the frame. As described above, the first layer having a frame shape which is a feature of the present invention can also be applied to a bottom contact type organic transistor.

This embodiment mode describes the form of a semiconductor element. The form of a measurement element can be freely combined with any of Embodiment Modes 1 to 4, and the manufacturing steps of Embodiment Modes 5 and 6 are referred to. Thus, the semiconductor element and the measurement element can be formed on the same substrate.

(Embodiment 8)
In this embodiment mode, a structure of a top-gate organic transistor is described unlike the above embodiment mode.

FIG. 9 is a perspective view of a top gate type organic transistor. 10A shows a top view of the organic transistor, FIG. 10B shows a cross-sectional view taken along OP, and FIG. 10C shows a cross-sectional view taken along QR. The organic transistor includes a lower electrode 310 functioning as a source electrode and a drain electrode, a frame shape provided on the lower electrode 310, a first layer 302 having a sidewall structure, and a first layer 302 An organic semiconductor layer 315 provided therein and a lower electrode 310, an insulating layer 312 functioning as a gate insulating layer provided on the organic semiconductor layer 315, and a first electrode functioning as a gate electrode provided on the insulating layer 312. 2 layers 313. The lower electrode 310 that functions as a source electrode and a drain electrode is divided below the organic semiconductor layer 315. The first layer 302 can have a frame shape by forming a space by removing the sacrificial layer. In order to maintain the state of the second layer 313 from the formation of the space to the formation of the organic semiconductor layer 315, a reinforcing material may be formed. The reinforcing material can be provided below or above the second layer 313 and is preferably formed so as to include silicon oxide, silicon nitride, or the like. This is because silicon oxide, silicon nitride, and the like have higher strength than the conductive material.

For the material and the manufacturing method of the organic semiconductor layer 315, the above embodiment mode can be referred to.

The organic semiconductor layer 315 formed using a wet film formation method is dried over a predetermined temperature and time. Then, contact between the organic semiconductor layer 315 and the second layer 313 functioning as a gate electrode can be achieved by using a capillary phenomenon when the organic semiconductor layer 315 is dried. In other words, before the organic semiconductor layer 315 is dried, the organic semiconductor layer 315 may not be in contact with the second layer 313 functioning as a gate electrode.

The organic semiconductor layer 315 thus formed does not require heat treatment for crystallization. Therefore, an organic transistor can be formed even with a substrate having low heat resistance such as a plus chip substrate.

Such an organic semiconductor layer 315 is provided in the first layer 302 having a frame shape, and thus does not require patterning. Therefore, the present invention is suitable because it can be used as a mold for pouring and baking a material that is difficult to pattern (for example, ZnO that is difficult to etch or an organic material that is weak against heat).

This embodiment mode describes the form of a semiconductor element. The form of a measurement element can be freely combined with any of Embodiment Modes 1 to 4, and the manufacturing steps of Embodiment Modes 5 and 6 are referred to. Thus, the semiconductor element and the measurement element can be formed on the same substrate.

(Embodiment 9)
In this embodiment, electronic devices using the organic transistors described in the above embodiments will be described.

As shown in FIG. 11, the organic transistor can be used as a switching element of a display portion mounted on an electronic device such as flexible electronic paper, a mobile phone, and a television receiver. Moreover, you may mount in the card | curd which has a function which manages personal information like an ID card.

FIG. 11A illustrates an electronic paper manufactured by applying the present invention. A main body 710 includes a display portion 711, a receiving device 712, a driver circuit 713, a film battery 714, and the like.

The display portion 711 is provided with the organic transistor of the present invention as a switching element. The display method may be a liquid crystal display method, an EL display method having a self-luminous element, or a microcapsule electrophoresis method. The display portion 711 includes an organic transistor for each pixel, and the organic transistor includes a first layer having the frame shape described in the above embodiment mode. Thus, translucency can be improved by the space in the 1st layer which has the shape of a frame. By providing such a light-transmitting switching element in the display portion, electronic paper with a high aperture ratio can be provided. A driving circuit 713 for driving the receiving device 712 and the switching element is formed on or mounted on the same substrate as the organic transistor. Since the organic transistor of the present invention can be manufactured on a flexible substrate such as a plastic substrate, it is very effective to apply it to electronic paper. And an electronic paper with a high aperture ratio can be produced by the organic transistor of the present invention.

FIG. 11B illustrates a card manufactured by applying the present invention, which includes a support 720, a display portion 721, an integrated circuit chip 722 incorporated in the support 720, and the like. Note that integrated circuits 723 and 724 for driving elements provided in the display portion 721 are also incorporated in the support body 720.

The display portion 721 is provided with the organic transistor of the present invention as a switching element. The display method may be a liquid crystal display method or an EL display method having a self-luminous element. The display portion 721 includes an organic transistor for each pixel, and the organic transistor includes a first layer having the frame shape described in the above embodiment mode. Thus, translucency can be improved by the space in the 1st layer which has the shape of a frame. By providing such a highly light-transmitting switching element in the display portion, a card having a display portion with a high aperture ratio can be provided. Further, the integrated circuits 723 and 724 for driving the display portion 721 are formed on or mounted on the same substrate as the organic transistor. Since the organic transistor of the present invention can be manufactured on a flexible substrate such as a plastic substrate, it is very effective to be applied to a display portion of a card. And the card | curd which has a display part with a high aperture ratio can be produced with the organic transistor of this invention. In such a display unit 721, information input / output in the integrated circuit chip 722 can be displayed, and the user can check what information is input / output.

FIG. 11C illustrates a television set manufactured by applying the present invention, which includes a display portion 730, a housing 731, a speaker 732, and the like.

In the display portion 730, the organic transistor of the present invention is provided as a switching element. The display method may be a liquid crystal display method or an EL display method having a self-luminous element. The display portion 730 includes an organic transistor for each pixel, and the organic transistor includes a first layer having the frame shape described in the above embodiment mode. Thus, translucency can be improved by the space in the 1st layer which has the shape of a frame. By providing such a high light-transmitting switching element in the display portion, a television receiver with a high aperture ratio can be provided. An integrated circuit for driving the display portion 730 is formed on or mounted on the same substrate as the organic transistor. Since the organic transistor of the present invention can be manufactured on a flexible substrate such as a plastic substrate, it is very effective to be applied to a display portion of a card. A television receiver with a high aperture ratio can be manufactured using the organic transistor of the present invention.

FIG. 11D is a diagram of a cellular phone. The main body 740 includes a display portion 741, an audio output portion 743, an audio input portion 744, operation switches 745 and 746, an antenna 747, and the like.

The display portion 741 is provided with the organic transistor of the present invention as a switching element. The display method may be a liquid crystal display method or an EL display method having a self-luminous element. The display portion 741 includes an organic transistor for each pixel, and the organic transistor includes a first layer having the frame shape described in the above embodiment mode. Thus, translucency can be improved by the space in the 1st layer which has the shape of a frame. By providing such a highly light-transmitting switching element in the display portion, a mobile phone having a display portion with a high aperture ratio can be provided. An integrated circuit for driving the display portion 741 is formed on or mounted on the same substrate as the organic transistor. Since the organic transistor of the present invention can be manufactured on a flexible substrate such as a plastic substrate, it is very effective to be applied to a display portion of a card. A mobile phone having a display portion with a high aperture ratio can be manufactured using the organic transistor of the present invention.

Moreover, although the case where the organic transistor to which the present invention is applied is provided in the electronic device has been described, the measuring element having the structure of the present invention may be provided in the electronic device.

As described above, the application range of the present invention is extremely wide and can be used for display devices in various fields.

In this example, an SEM (scanning electron microscope) photograph of a structure having a sidewall structure of the present invention will be described.

The sacrificial layer was patterned into a rectangular shape using tungsten. For patterning the sacrificial layer, dry etching is used, a pressure of 13.5 Pa (13.5 / 133 Torr), a voltage applied to the upper electrode (corresponding to the ICP electrode) is applied to 500 W, and a lower electrode (corresponding to the bias electrode) is applied. The voltage was 10 W, the etching agents Cl ₂ , CF ₄ , and O ₂ , and the respective flow rates were 50.4 sccm, 50.4 sccm, and 20.4 sccm, and 30% overetching was performed from the time of the end point at which the sacrificial layer disappeared. At this time, the first film thickness was 1000 nm.

Thereafter, the first layer was laminated on the removed sacrificial layer, and was patterned so as to remain only on the side surface of the sacrificial layer, that is, in a sidewall shape. At this time, the second film thickness was set to 900 nm. The first layer is patterned by dry etching. In the first step, the pressure is 5.5 Pa (5.5 / 133 Torr), the voltage applied to the upper electrode (corresponding to the ICP electrode) is 475 W, the lower electrode ( Etching was performed for 3 seconds with a voltage applied to a bias electrode of 300 W and etching agents CHF ₃ and He at respective flow rates of 50 sccm and 150 sccm. In the second step, the pressure is 5.5 Pa (5.5 / 133 Torr), the voltage applied to the upper electrode (corresponding to the ICP electrode) is 475 W, the voltage applied to the lower electrode (corresponding to the bias electrode) is 300 W, the etching agent CHF ₃ and He were etched at a flow rate of 7.5 sccm and 142.5 sccm for 60 seconds. In the third step, the pressure is 5.5 Pa (5.5 / 133 Torr), the voltage applied to the upper electrode (corresponding to the ICP electrode) is 50 W, the voltage applied to the lower electrode (corresponding to the bias electrode) is 450 W, the etching agent CHF ₃ and He were flowed at 48 sccm and 152 sccm, respectively, and etched for 360 seconds.

Then, silicon oxide was used for the second layer and formed above the sacrificial layer and the first layer provided in a sidewall shape. The second layer was patterned into an elongated rectangular shape. That is, the second layer extends over the sacrificial layer and the first layer provided in a sidewall shape, in other words, the second layer is provided in the sacrificial layer and the sidewall shape. From one side to the other side opposite to the one side.

Next, an etching process was performed to remove the sacrificial layer. Wet etching was used for the etching treatment, and a mixture containing ammonia (28%): hydrogen peroxide (31%): water in a ratio of 2: 5: 2 was used as the etching agent.

The resulting structure is shown in FIG. 12, and an enlarged view thereof is shown in FIG. Only the sacrificial layer made of W was removed, and a space provided in the frame was formed. The first layer remained in a sidewall shape. Further, the second layer was not etched and had an elongated rectangular shape and was provided over the first layer. Such a second layer can move in space, for example, the second layer in space can move up and down.

It is the figure which showed the microstructure of this invention It is a figure showing the manufacturing process of the microstructure of the present invention It is the figure which showed the measuring element of this invention It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is a figure showing a manufacturing process of a semiconductor device of the present invention. It is sectional drawing which showed the semiconductor device of this invention It is the figure which showed the organic transistor of this invention It is the figure which showed the organic transistor of this invention It is the figure which showed the organic transistor of this invention It is the figure which showed the organic transistor of this invention It is the figure which showed the electronic device of this invention It is the SEM photograph which showed the microstructure of the present invention. It is the SEM photograph which showed the microstructure of the present invention. It is the figure which showed the measuring element of this invention

Claims (10)

An insulating substrate;
A first layer formed of a sidewall structure frame formed on a surface of the insulating substrate and having a cross-section narrowing toward a tip and a lower side being thicker than the tip;
A second layer along the outside of the sidewall structure , cross-linked to a part above the frame, and movable toward the surface of the insulating substrate;
A microstructure characterized by comprising: In claim 1,
The microstructure is characterized in that the first layer is made of an insulating layer, and the second layer is made of a conductive layer. An insulating substrate;
A first layer formed of a sidewall structure frame formed on the surface of the insulating substrate, with a cross section narrowing toward the tip and a lower side being thicker than the tip , and along the outside of the sidewall structure A microstructure having a second layer bridged to a portion above the frame and capable of moving toward the surface of the insulating substrate;
A semiconductor element having a gate electrode formed on a surface of the insulating substrate, and an insulating layer having a sidewall structure formed on a side surface of the gate electrode ;
I have a,
A micromachine according to claim 1, wherein the sidewall structure frame of the microstructure and the sidewall structure insulating layer of the semiconductor element are formed by patterning the same insulating layer on the insulating substrate . An insulating substrate;
A first layer formed of a sidewall structure frame formed on the surface of the insulating substrate and having a cross-section narrowing toward the tip and a lower side being thicker than the tip , and extends to the outside of the first layer. A microstructure having a second layer along the outside of the sidewall structure and bridged to a part above the frame and movable toward the surface of the insulating substrate, ,
A semiconductor element having a gate electrode formed on a surface of the insulating substrate, and an insulating layer having a sidewall structure formed on a side surface of the gate electrode ;
I have a,
A micromachine according to claim 1, wherein the sidewall structure frame of the microstructure and the sidewall structure insulating layer of the semiconductor element are formed by patterning the same insulating layer on the insulating substrate . In claim 3 or claim 4,
A micromachine comprising a conductive layer provided below the first layer. In any one of Claims 3 thru | or 5,
The micromachine according to claim 1, wherein the first layer is made of an insulating layer, and the second layer is made of a conductive layer. Forming a sacrificial layer on the surface of the insulating substrate;
On the side surface of the sacrificial layer, forming a first layer composed of a frame of a sidewall structure in which a cross section becomes narrower toward the tip and a lower side is thicker than the tip,
A second layer is formed on the sacrificial layer and the first layer along the outside of the sidewall structure and cross-linked to a part above the frame ,
A method for manufacturing a microstructure, wherein the sacrificial layer is etched so that the second layer can move toward the surface of the insulating substrate. Forming a sacrificial layer on the surface of the insulating substrate;
On the side surface of the sacrificial layer, forming a first layer composed of a frame of a sidewall structure in which a cross section becomes narrower toward the tip and a lower side is thicker than the tip,
A second layer that extends along the outside of the sidewall structure on the sacrificial layer and the first layer and extends to a part above the frame so as to extend to the outside of the first layer. Form the
A method for manufacturing a microstructure, wherein the sacrificial layer is etched so that the second layer can move toward the surface of the insulating substrate. Forming a semiconductor layer in a first region on the surface of the insulating substrate ;
Forming a gate electrode on the semiconductor layer in the first region and a sacrificial layer in the second region ;
A side wall of the sacrificial layer, a first layer comprising a sidewall structure frame with a cross section narrowing toward the tip and a lower side thicker than the tip, and an insulating layer having a sidewall structure on the side surface of the gate electrode Form the
A second layer that extends along the outside of the sidewall structure on the sacrificial layer and the first layer and is bridged to a part above the frame , and is electrically connected to an impurity region of the semiconductor layer and electrodes were formed,
A method of manufacturing a micromachine, wherein the microstructure is formed by etching the sacrificial layer so that the second layer can move toward the surface of the insulating substrate. Forming a semiconductor layer in a first region on the surface of the insulating substrate ;
Forming a gate electrode on the semiconductor layer in the first region and a sacrificial layer in the second region ;
A side wall of the sacrificial layer, a first layer comprising a sidewall structure frame with a cross section narrowing toward the tip and a lower side thicker than the tip, and an insulating layer having a sidewall structure on the side surface of the gate electrode Form the
The so as to extend to the outside of the first layer, along with along the outer side of the sidewall structure on the sacrificial layer and the first layer, the second layer is crosslinked to a part of the upper of the frame And an electrode electrically connected to the impurity region of the semiconductor layer ,
A method of manufacturing a micromachine, wherein the microstructure is formed by etching the sacrificial layer so that the second layer can move toward the surface of the insulating substrate.