JP2007069341A5 - - Google Patents
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- JP2007069341A5 JP2007069341A5 JP2006215373A JP2006215373A JP2007069341A5 JP 2007069341 A5 JP2007069341 A5 JP 2007069341A5 JP 2006215373 A JP2006215373 A JP 2006215373A JP 2006215373 A JP2006215373 A JP 2006215373A JP 2007069341 A5 JP2007069341 A5 JP 2007069341A5
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- layer
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- 239000004065 semiconductor Substances 0.000 claims 10
- 239000012535 impurity Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 5
- 238000005530 etching Methods 0.000 claims 3
Claims (5)
前記犠牲層上に、第1の層を形成し、
前記第1の層上に、第1の膜厚および前記第1の膜厚より薄い第2の膜厚を有するマスクを形成し、
前記マスクを用いて、前記第1の層をエッチングすることによって、構造層を形成し、
前記犠牲層を除去し、
前記構造層は、前記第2の膜厚のマスク下に設けられていた第2の部分の厚みが、前記第1の膜厚のマスク下に設けられていた第1の部分の厚みより薄いことを特徴とする微小電気機械式装置の作製方法。 Forming a sacrificial layer on the substrate;
Forming a first layer on the sacrificial layer;
Forming a mask having a first film thickness and a second film thickness smaller than the first film thickness on the first layer;
Using said mask, by etching said first layer to form a structure layer,
Removing the sacrificial layer;
In the structural layer, the thickness of the second portion provided under the second thickness mask is smaller than the thickness of the first portion provided under the first thickness mask. A manufacturing method of a micro electro mechanical device characterized by the above.
前記半導体層上に、絶縁層を形成し、
前記絶縁層および前記犠牲層上に、それぞれ導電層を形成し、
前記半導体層上方の前記導電層上および前記犠牲層上方の前記導電層上に、第1の膜厚および前記第1の膜厚より薄い第2の膜厚を有するマスクを形成し、
前記マスクを用いて、前記導電層をエッチングすることによって、前記第1の領域にはゲート電極を形成し、かつ、前記第2の領域には構造層を形成し、
前記ゲート電極をマスクとして前記半導体層に不純物元素を添加することによって、前記半導体層に不純物領域を形成し、
前記不純物領域および前記構造層に接続される配線を形成し、
前記犠牲層を除去し、
前記構造層は、前記第2の膜厚のマスク下に設けられていた第2の部分の厚みが、前記第1の膜厚のマスク下に設けられていた第1の部分の厚みより薄いことを特徴とする微小電気機械式装置の作製方法。 The semi-conductor layer is formed on the first region on the insulating substrate, and forming a sacrificial layer on the second region on the insulating substrate,
Forming an insulating layer on the semiconductor layer;
Forming a conductive layer on each of the insulating layer and the sacrificial layer;
Forming a mask having a first film thickness and a second film thickness smaller than the first film thickness on the conductive layer above the semiconductor layer and on the conductive layer above the sacrificial layer ;
Using said mask, by etching the conductive layer, wherein the first region forms a Gate electrode, and forming a structural layer on the second region,
An impurity region is formed in the semiconductor layer by adding an impurity element to the semiconductor layer using the gate electrode as a mask ,
Forming a wiring connected to the impurity region and the structural layer;
Removal of the previous Symbol sacrificial layer,
Before Ki構 concrete layer, a second portion of the thickness which provided the mask under the second film thickness, than the first portion of the thickness which provided the mask under the first thickness the method for manufacturing a micro-electro-mechanical device, characterized in that not thin.
前記半導体層上に、第1の絶縁層を形成し、Forming a first insulating layer on the semiconductor layer;
前記第1の絶縁層および前記犠牲層上に、それぞれ導電層を形成し、Forming a conductive layer on each of the first insulating layer and the sacrificial layer;
前記半導体層上方の前記導電層上および前記犠牲層上方の前記導電層上に、第1の膜厚および前記第1の膜厚より薄い第2の膜厚を有するマスクを形成し、Forming a mask having a first film thickness and a second film thickness smaller than the first film thickness on the conductive layer above the semiconductor layer and on the conductive layer above the sacrificial layer;
前記マスクを用いて、前記導電層をエッチングすることによって、前記第1の領域にはゲート電極を形成し、かつ、前記第2の領域には構造層を形成し、Etching the conductive layer using the mask forms a gate electrode in the first region, and forms a structural layer in the second region;
前記ゲート電極をマスクとして前記半導体層に不純物元素を添加することによって、前記半導体層に不純物領域を形成し、An impurity region is formed in the semiconductor layer by adding an impurity element to the semiconductor layer using the gate electrode as a mask,
前記第1の絶縁層、前記ゲート電極および前記構造層を覆う第2の絶縁層を形成し、Forming a second insulating layer covering the first insulating layer, the gate electrode and the structural layer;
前記第2の絶縁層上に、前記不純物領域に接続される配線を形成し、Forming a wiring connected to the impurity region on the second insulating layer;
前記第2の領域において、前記配線の一部を選択的に除去することによって、開口部を形成し、In the second region, an opening is formed by selectively removing a part of the wiring,
前記開口部からエッチング剤を導入することによって、前記第2の領域における前記第2の絶縁層および前記犠牲層を除去し、Removing the second insulating layer and the sacrificial layer in the second region by introducing an etchant from the opening;
前記構造層は、前記第2の膜厚のマスク下に設けられていた第2の部分の厚みが、前記第1の膜厚のマスク下に設けられていた第1の部分の厚みより薄いことを特徴とする微小電気機械式装置の作製方法。In the structural layer, the thickness of the second portion provided under the second thickness mask is smaller than the thickness of the first portion provided under the first thickness mask. A manufacturing method of a micro electro mechanical device characterized by the above.
前記構造層における前記第2の部分の幅は、前記第1の部分の幅より小さいことを特徴とする微小電気機械式装置の作製方法。The method of manufacturing a microelectromechanical device, wherein a width of the second portion in the structural layer is smaller than a width of the first portion.
前記構造層における前記第2の部分と、前記第1の部分との境界をテーパー形状とすることを特徴とする微小電気機械式装置の作製方法。A method for manufacturing a microelectromechanical device, wherein a boundary between the second portion and the first portion in the structural layer is tapered.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006215373A JP5127181B2 (en) | 2005-08-10 | 2006-08-08 | Method for manufacturing micro electromechanical device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2005232670 | 2005-08-10 | ||
JP2005232670 | 2005-08-10 | ||
JP2006215373A JP5127181B2 (en) | 2005-08-10 | 2006-08-08 | Method for manufacturing micro electromechanical device |
Publications (3)
Publication Number | Publication Date |
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JP2007069341A JP2007069341A (en) | 2007-03-22 |
JP2007069341A5 true JP2007069341A5 (en) | 2009-09-17 |
JP5127181B2 JP5127181B2 (en) | 2013-01-23 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006215373A Expired - Fee Related JP5127181B2 (en) | 2005-08-10 | 2006-08-08 | Method for manufacturing micro electromechanical device |
Country Status (1)
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JP (1) | JP5127181B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4607153B2 (en) | 2007-07-12 | 2011-01-05 | 株式会社日立製作所 | Method for manufacturing micro electromechanical system element |
JP2009086385A (en) * | 2007-09-29 | 2009-04-23 | Hoya Corp | Photomask and method for manufacturing the same, and pattern transfer method |
DE102012206732A1 (en) * | 2012-04-24 | 2013-10-24 | Robert Bosch Gmbh | Method for producing a hybrid integrated component |
JP2014204352A (en) * | 2013-04-08 | 2014-10-27 | セイコーエプソン株式会社 | Vibration element, vibrator, oscillator, manufacturing method of vibration element, electronic apparatus and mobile |
JP2014212409A (en) * | 2013-04-18 | 2014-11-13 | セイコーエプソン株式会社 | Mems vibrator, electronic apparatus and movable object |
JP2014212410A (en) * | 2013-04-18 | 2014-11-13 | セイコーエプソン株式会社 | Vibrator, oscillator, electronic apparatus, mobile body, and manufacturing method of vibrator |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2791858B2 (en) * | 1993-06-25 | 1998-08-27 | 株式会社半導体エネルギー研究所 | Semiconductor device manufacturing method |
JPH097946A (en) * | 1995-06-26 | 1997-01-10 | Toyota Motor Corp | Manufacture of polycrystal silicon film |
JPH11293486A (en) * | 1998-04-16 | 1999-10-26 | Canon Inc | Manufacture of microstructure |
JP3592535B2 (en) * | 1998-07-16 | 2004-11-24 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP2000188049A (en) * | 1998-12-22 | 2000-07-04 | Nec Corp | Micro machine switch and manufacture thereof |
FR2808919B1 (en) * | 2000-05-15 | 2002-07-19 | Memscap | ELECTRONIC MICROCOMPONENT OF THE VARIABLE CAPACITY OR MICROSWITCH TYPE, OR METHOD FOR MANUFACTURING SUCH A COMPONENT |
US6780570B2 (en) * | 2000-06-28 | 2004-08-24 | Institut National D'optique | Method of fabricating a suspended micro-structure with a sloped support |
JP4954401B2 (en) * | 2000-08-11 | 2012-06-13 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device |
AU2002211892A1 (en) * | 2000-10-10 | 2002-04-22 | Mems Optical, Inc. | Deep grayscale etching of silicon |
JP4571488B2 (en) * | 2004-12-22 | 2010-10-27 | 日本電信電話株式会社 | Fine structure |
JP4519804B2 (en) * | 2005-05-27 | 2010-08-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
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2006
- 2006-08-08 JP JP2006215373A patent/JP5127181B2/en not_active Expired - Fee Related
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