JP2007053253A - Design method of semiconductor integrated circuit - Google Patents

Design method of semiconductor integrated circuit Download PDF

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JP2007053253A
JP2007053253A JP2005237628A JP2005237628A JP2007053253A JP 2007053253 A JP2007053253 A JP 2007053253A JP 2005237628 A JP2005237628 A JP 2005237628A JP 2005237628 A JP2005237628 A JP 2005237628A JP 2007053253 A JP2007053253 A JP 2007053253A
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integrated circuit
software development
semiconductor integrated
pad
input
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JP4387338B2 (en
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Yukio Ogawa
幸生 小川
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To enable miniaturization and cost reduction in a semiconductor integrated circuit for mass production, while providing a large number of pads required for chip evaluation of the integrated circuit or software development. <P>SOLUTION: The pads of an integrated circuit are classified into a pad 202 for software development used only in software development using the integrated circuit, and the other usual pad 203. It is made for a region wherein the pad 202 for software development is arranged to serve in the outside of the region wherein usually the pad 203 is arranged. A process for designing the integrated circuit as a semiconductor integrated circuit 102 for software development, and a process for designing a semiconductor integrated circuit 106 for mass production by removing the pad 202 for software development from the layout data of the integrated circuit 102 for software development are carried out. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体集積回路の設計方法に係り、特に、半導体集積回路のチップ評価やソフトウェア開発のために必要な多数のパッドを提供しながら実装面積の削減を可能にする技術に関する。   The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a technique that enables a reduction in mounting area while providing a large number of pads necessary for chip evaluation and software development of a semiconductor integrated circuit.

半導体プロセスの微細化が進むにつれて、半導体集積回路を搭載するボードの実装面積削減や半導体集積回路のチップコスト低減のために、１つの半導体集積回路に多くの機能を搭載するようになってきた。このような微細プロセスを使用した多機能な半導体集積回路では、外部部品と接続するための多数のパッドに加えて、チップ評価やソフトウェア開発のためにも多数のパッドが必要になっている。このような背景で増加するパッドの必要数を確保するために、パッドを配置するパッド領域を確保しなければならない。そのために従来様々な手法が工夫されている。その配置方法の一つとして特許文献１に記載されているものがある。   As miniaturization of semiconductor processes progresses, many functions have been mounted on one semiconductor integrated circuit in order to reduce the mounting area of a board on which the semiconductor integrated circuit is mounted and the chip cost of the semiconductor integrated circuit. In a multifunctional semiconductor integrated circuit using such a fine process, in addition to a large number of pads for connecting to external components, a large number of pads are required for chip evaluation and software development. In order to secure the necessary number of pads that increase in such a background, a pad area in which the pads are arranged must be secured. For this purpose, various techniques have been devised. One of the arrangement methods is described in Patent Document 1.

図７はパッド数を増やす工夫がなされた従来の半導体集積回路の構成図である。図７において、７０４は半導体集積回路の内部セル領域、７０３は入出力セル領域、７０１は入出力セル領域７０３の外側に形成される外部パッド領域、７０２は内部セル領域７０４と入出力セル領域７０３の間に形成される内部パッド領域である。このように、通常はチップの周縁部に配置される外部パッド領域７０１に加えて、内部セル領域７０４と入出力セル領域７０３の間に内部パッド領域７０２を設けることで、入出力セル７０３の外側と内側にパッドを配置し、信頼性を保ちつつパッド数の増加を図っていた。
特開２０００−２３２１２０号公報 FIG. 7 is a configuration diagram of a conventional semiconductor integrated circuit in which a device for increasing the number of pads is devised. In FIG. 7, reference numeral 704 denotes an internal cell region of the semiconductor integrated circuit, 703 denotes an input / output cell region, 701 denotes an external pad region formed outside the input / output cell region 703, and 702 denotes an internal cell region 704 and an input / output cell region 703. It is an internal pad area | region formed between. As described above, by providing the internal pad region 702 between the internal cell region 704 and the input / output cell region 703 in addition to the external pad region 701 that is normally arranged at the peripheral edge of the chip, the outside of the input / output cell 703 is provided. And pads were arranged inside to increase the number of pads while maintaining reliability.
JP 2000-232120 A

しかしながら、この方法では、さらにプロセスの微細化が進み半導体集積回路の面積が小さくなり、かつ多機能化に伴い必要なパッド数が増加すると、パッド配置領域を確保するために半導体集積回路の面積が大きくなり、実装面積の小型化や面積削減による半導体集積回路の低コスト化が困難になるという問題があった。   However, in this method, when the process is further miniaturized and the area of the semiconductor integrated circuit is reduced and the number of necessary pads is increased along with the increase in functionality, the area of the semiconductor integrated circuit is reduced in order to secure a pad arrangement region. There has been a problem that it is difficult to reduce the cost of the semiconductor integrated circuit by reducing the mounting area and reducing the area.

本発明は、半導体集積回路のチップ評価やソフトウェア開発のために必要な多数のパッドを提供しながら、実装面積削減による小型化と低コスト化を可能にする半導体集積回路の設計方法を提供することを目的とする。   The present invention provides a method for designing a semiconductor integrated circuit that enables reduction in size and cost by reducing the mounting area while providing a large number of pads necessary for chip evaluation and software development of the semiconductor integrated circuit. With the goal.

本発明は、外部接続用の複数のパッドと、論理回路を形成する内部セルと前記パッドとの間で信号の受け渡しを行う入出力セルとを備える半導体集積回路の設計方法であって、前記パッドを前記半導体集積回路を用いたソフトウェア開発のみにおいて使用されるソフトウェア開発用パッドと前記ソフトウェア開発用パッド以外の通常パッドとに区分し、前記ソフトウェア開発用パッドの配置領域を前記通常パッドを配置する領域の外側にして前記半導体集積回路をソフトウェア開発用半導体集積回路として設計する工程と、前記ソフトウェア開発用半導体集積回路のレイアウトデータから前記ソフトウェア開発用パッドを取り除いて量産用半導体集積回路を設計する工程とを有する。   The present invention relates to a method for designing a semiconductor integrated circuit comprising a plurality of pads for external connection, an internal cell forming a logic circuit, and an input / output cell for transferring signals between the pads. Is divided into a software development pad used only in software development using the semiconductor integrated circuit and a normal pad other than the software development pad, and an area in which the software development pad is arranged is an area in which the normal pad is arranged A step of designing the semiconductor integrated circuit as a software development semiconductor integrated circuit on the outside, and a step of designing a mass production semiconductor integrated circuit by removing the software development pad from the layout data of the software development semiconductor integrated circuit; Have

上記構成によれば、ソフトウェア開発用半導体集積回路のレイアウトデータからソフトウェア開発用パッドを取り除いて量産用半導体集積回路を設計するため、チップ評価やソフトウェア開発のために多数のパッドが必要な場合にも、量産用半導体集積回路を容易に小型化し、低コスト化することができる。   According to the above configuration, since the software development pad is removed from the layout data of the software development semiconductor integrated circuit to design the mass production semiconductor integrated circuit, even when a large number of pads are required for chip evaluation and software development. The semiconductor integrated circuit for mass production can be easily downsized and reduced in cost.

本発明において、前記ソフトウェア開発用パッドを前記入出力セルを配置する領域の外側に配置し、前記通常パッドを前記入出力セルを配置する領域の内側に配置する。この構成によれば、入出力セルを配置する領域の外側にソフトウェア開発用パッドを配置するため、ソフトウェア開発用半導体集積回路からソフトウェア開発用パッドを容易に取り除くことができ、量産用半導体集積回路の設計が簡単になる。   In the present invention, the software development pad is arranged outside the area where the input / output cells are arranged, and the normal pad is arranged inside the area where the input / output cells are arranged. According to this configuration, since the software development pad is arranged outside the area where the input / output cells are arranged, the software development pad can be easily removed from the software development semiconductor integrated circuit. Design becomes simple.

また、本発明は、外部接続用の複数のパッドと、論理回路を形成する内部セルと前記パッドとの間で信号の受け渡しを行う入出力セルとを備える半導体集積回路の設計方法であって、前記パッドおよび前記入出力セルを、前記半導体集積回路を用いたソフトウェア開発のみにおいて使用されるソフトウェア開発用パッドおよび前記ソフトウェア開発用パッドに接続される入出力セルと、前記ソフトウェア開発用パッド以外の通常パッドおよび前記通常パッドに接続される入出力セルとに区分し、前記ソフトウェア開発用パッドおよび前記ソフトウェア開発用パッドに接続される入出力セルの配置領域を、前記通常パッドおよび前記通常パッドに接続される入出力セルを配置する領域の外側にして前記半導体集積回路をソフトウェア開発用半導体集積回路として設計する工程と、前記ソフトウェア開発用半導体集積回路のレイアウトデータから前記ソフトウェア開発用パッドおよび前記ソフトウェア開発用パッドに接続される入出力セルを取り除いて量産用半導体集積回路を設計する工程とを有する。   Further, the present invention is a method for designing a semiconductor integrated circuit comprising a plurality of pads for external connection, an internal cell forming a logic circuit, and an input / output cell for passing signals between the pads, The pad and the input / output cell are a software development pad used only in software development using the semiconductor integrated circuit, an input / output cell connected to the software development pad, and other than the software development pad. The software development pad and the input / output cell connection area connected to the software development pad are connected to the normal pad and the normal pad. The semiconductor integrated circuit is placed outside the area where the input / output cells are arranged, and the semiconductor for software development A step of designing as an integrated circuit, and a step of designing a mass production semiconductor integrated circuit by removing the software development pad and the input / output cells connected to the software development pad from the layout data of the software development semiconductor integrated circuit; Have

上記構成によれば、ソフトウェア開発用半導体集積回路のレイアウトデータからソフトウェア開発用パッドおよびこれに接続される入出力セルを取り除いて量産用半導体集積回路を設計するため、実装面積削減効果が大きく、チップ評価やソフトウェア開発のために多数のパッドが必要な場合にも、量産用半導体集積回路を容易に小型化し、低コスト化することができる。   According to the above configuration, since the software development pad and input / output cells connected to the software development pad and the input / output cells connected thereto are removed from the layout data of the software development semiconductor integrated circuit, the mass production semiconductor integrated circuit is greatly reduced. Even when a large number of pads are required for evaluation and software development, a semiconductor integrated circuit for mass production can be easily downsized and reduced in cost.

また、本発明の半導体集積回路の設計方法により前記ソフトウェア開発用半導体集積回路として製造したチップから物理的な切断により前記量産用半導体集積回路を製造する。この構成によれば、ソフトウェア開発用半導体集積回路のチップからソフトウェア開発用パッド領域を物理的に切断して小型の半導体集積回路を作成することができるため、必要な半導体集積回路が限定数量である場合などにおいて、ソフトウェア開発用半導体集積回路を小型化して実製品に有効に活用することができる。   Further, the semiconductor integrated circuit for mass production is manufactured by physical cutting from a chip manufactured as the semiconductor integrated circuit for software development by the semiconductor integrated circuit design method of the present invention. According to this configuration, since the software development pad area can be physically cut from the chip of the software development semiconductor integrated circuit, a small semiconductor integrated circuit can be created. Therefore, the required number of semiconductor integrated circuits is limited. In some cases, the software development semiconductor integrated circuit can be miniaturized and effectively used in actual products.

本発明によれば、チップ評価やソフトウェア開発には多数のパッドが用意されたソフトウェア開発用半導体集積回路を使用し、このソフトウェア開発用半導体集積回路のレイアウトデータからソフトウェア開発用パッドを取り除いて量産用半導体集積回路を設計することで、量産用半導体集積回路を容易に小型化し、低コスト化することができる。   According to the present invention, a semiconductor integrated circuit for software development having a large number of pads is used for chip evaluation and software development, and the software development pad is removed from the layout data of the software integrated semiconductor integrated circuit for mass production. By designing a semiconductor integrated circuit, a semiconductor integrated circuit for mass production can be easily downsized and reduced in cost.

（実施の形態１）
図１は本発明の実施の形態１に係る半導体集積回路の設計方法を示すフロー図である。図１において、まず、ソフトウェア開発用半導体集積回路設計工程１０１では、半導体集積回路のパッドをソフトウェア開発専用に使用するソフトウェア開発用パッドと半導体集積回路を通常に動作させるときに必要な通常パッドとに分け、ソフトウェア開発用パッドは半導体集積回路の外側に配置し、通常パッドはソフトウェア開発用パッドの内側に配置したソフトウェア開発用半導体集積回路１０２を設計する。このソフトウェア開発用パッドは後の工程で削除されるので、プルアップ抵抗もしくはプルダウン抵抗を付けておき、削除した際の貫通電流対策を施しておく。 (Embodiment 1)
FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit according to Embodiment 1 of the present invention. In FIG. 1, first, in a software development semiconductor integrated circuit design step 101, a software development pad that uses a pad of the semiconductor integrated circuit exclusively for software development and a normal pad that is necessary when the semiconductor integrated circuit is normally operated. The software development pad is arranged outside the semiconductor integrated circuit, and the software development semiconductor integrated circuit 102 is designed in which the normal pad is arranged inside the software development pad. Since this software development pad is deleted in a later process, a pull-up resistor or a pull-down resistor is attached, and a measure against through current at the time of deletion is taken.

次に、ソフトウェア開発工程１０３では、前工程で作成したソフトウェア開発用半導体集積回路１０２を用いてソフトウェア開発を行う。最後に、ソフトウェア開発用パッド削除工程１０５では、ソフトウェア開発用半導体集積回路１０２のレイアウトデータ１０４からソフトウェア開発用パッドを取り除くレイアウト修正を行い、量産用半導体集積回路１０６の設計データを出力する。   Next, in the software development process 103, software development is performed using the software development semiconductor integrated circuit 102 created in the previous process. Finally, in the software development pad deletion step 105, layout correction is performed to remove the software development pad from the layout data 104 of the software development semiconductor integrated circuit 102, and design data of the mass production semiconductor integrated circuit 106 is output.

図２は本実施の形態に係る半導体集積回路の設計方法の効果を説明する構成図であり、ソフトウェア開発用半導体集積回路１０２と量産用半導体集積回路１０６のレイアウトを示している。ソフトウェア開発用半導体集積回路１０２はソフトウェア開発用パッド２０２と通常パッド２０３と入出力セル２０１を搭載し、ソフトウェア開発用パッド２０２は入出力セル２０１の外側に配置されている。一方、量産用半導体集積回路１０６はソフトウェア開発用半導体集積回路１０２からソフトウェア開発用パッド２０２が削除されているため、通常パッド２０３と入出力パッド２０１のみを搭載し、ソフトウェア開発用パッドの領域分だけ半導体集積回路の小型化が可能となる。   FIG. 2 is a block diagram for explaining the effects of the semiconductor integrated circuit design method according to the present embodiment, and shows the layout of the software development semiconductor integrated circuit 102 and the mass production semiconductor integrated circuit 106. The software development semiconductor integrated circuit 102 includes a software development pad 202, a normal pad 203, and an input / output cell 201. The software development pad 202 is arranged outside the input / output cell 201. On the other hand, since the software development pad 202 is deleted from the software development semiconductor integrated circuit 102 in the mass production semiconductor integrated circuit 106, only the normal pad 203 and the input / output pad 201 are mounted, and only for the area of the software development pad. A semiconductor integrated circuit can be miniaturized.

このように、本実施の形態の半導体集積回路の設計方法によれば、ソフトウェア開発用半導体集積回路のレイアウトからソフトウェア開発用パッドを取り除いて量産用半導体集積回路を設計するため、半導体集積回路を小型にすることができる。   As described above, according to the semiconductor integrated circuit design method of the present embodiment, a semiconductor integrated circuit for mass production is designed by removing the software development pad from the layout of the semiconductor integrated circuit for software development. Can be.

（実施の形態２）
図３は本発明の実施の形態２に係る半導体集積回路の設計方法を示すフロー図である。図３において、まず、ソフトウェア開発用半導体集積回路設計工程３０１では、半導体集積回路のパッドをソフトウェア開発専用に使用するソフトウェア開発用パッドと半導体集積回路を通常に動作させるときに必要な通常パッドとに分け、ソフトウェア開発用パッドとその入出力セルは半導体集積回路の外側に配置し、通常パッドとその入出力セルはソフトウェア開発用パッドとその入出力セルの内側に配置したソフトウェア開発用半導体集積回路３０２を設計する。このソフトウェア開発用パッドとその入出力セルは後の工程で削除されるので、プルアップ抵抗もしくはプルダウン抵抗を付けておき、削除した際の貫通電流対策を施しておく。 (Embodiment 2)
FIG. 3 is a flowchart showing a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 3, first, in the software development semiconductor integrated circuit design step 301, the pads for the semiconductor integrated circuit are used for software development only, and the normal pads necessary for normal operation of the semiconductor integrated circuit are used. The software development pad and its input / output cell are arranged outside the semiconductor integrated circuit, and the normal pad and its input / output cell are arranged inside the software development pad and its input / output cell. To design. Since this software development pad and its input / output cell will be deleted in a later process, a pull-up resistor or pull-down resistor is attached, and a measure against through current when it is deleted is taken.

次に、ソフトウェア開発工程１０３では、前工程で作成したソフトウェア開発用半導体集積回路３０２を用いてソフトウェア開発を行う。最後に、ソフトウェア開発用パッドおよび入出力セル削除工程３０５では、ソフトウェア開発用半導体集積回路３０２のレイアウトデータ３０４からソフトウェア開発用パッドとその入出力セルを取り除くレイアウト修正を行い、量産用半導体集積回路３０６の設計データを出力する。   Next, in the software development process 103, software development is performed using the software development semiconductor integrated circuit 302 created in the previous process. Finally, in the software development pad and input / output cell deletion step 305, the layout correction 304 is performed to remove the software development pad and its input / output cells from the layout data 304 of the software development semiconductor integrated circuit 302, and the semiconductor integrated circuit 306 for mass production. Output design data.

図４は本実施の形態に係る半導体集積回路の設計方法の効果を説明する構成図であり、ソフトウェア開発用半導体集積回路３０２と量産用半導体集積回路３０６のレイアウトを示している。ソフトウェア開発用半導体集積回路３０２はソフトウェア開発用パッド４０２およびソフトウェア開発パッド用入出力セル４０１と通常パッド４０４および通常パッド用入出力セル４０３を搭載し、ソフトウェア開発用パッド４０２およびソフトウェア開発パッド用入出力セル４０１は通常パッド４０４および通常パッド用入出力セル４０３の外側に配置されている。   FIG. 4 is a configuration diagram for explaining the effect of the method for designing a semiconductor integrated circuit according to the present embodiment, and shows the layout of the semiconductor integrated circuit 302 for software development and the semiconductor integrated circuit 306 for mass production. The software development semiconductor integrated circuit 302 includes a software development pad 402, a software development pad input / output cell 401, a normal pad 404, and a normal pad input / output cell 403, and the software development pad 402 and the software development pad input / output. The cell 401 is disposed outside the normal pad 404 and the normal pad input / output cell 403.

一方、量産用半導体集積回路３０６はソフトウェア開発用半導体集積回路３０２からソフトウェア開発用パッド４０２およびソフトウェア開発パッド用入出力セル４０１が削除されているため、通常パッド４０４および通常パッド用入出力セル４０３のみを搭載し、ソフトウェア開発用パッドとソフトウェア開発パッド用入出力セルの領域分だけ半導体集積回路の小型化が可能となる。   On the other hand, since the software development pad 402 and the software development pad input / output cell 401 are deleted from the software development semiconductor integrated circuit 302 in the mass production semiconductor integrated circuit 306, only the normal pad 404 and the normal pad input / output cell 403 are present. The semiconductor integrated circuit can be reduced in size by the area of the software development pad and the software development pad input / output cell.

このように、本実施の形態の半導体集積回路の設計方法によれば、ソフトウェア開発用半導体集積回路のレイアウトからソフトウェア開発用パッドとソフトウェア開発パッド用入出力セルを取り除いて量産用半導体集積回路を設計するため、半導体集積回路を小型にすることができる。   As described above, according to the semiconductor integrated circuit design method of the present embodiment, the mass production semiconductor integrated circuit is designed by removing the software development pad and the software development pad input / output cell from the layout of the software integrated semiconductor integrated circuit. Therefore, the semiconductor integrated circuit can be reduced in size.

（実施の形態３）
図５は本発明の実施の形態３に係る半導体集積回路の作成方法を示すフロー図である。図５において、ソフトウェア開発用半導体集積回路設計工程１０１およびソフトウェア開発工程１０３は図１に示した実施の形態１の対応する工程と同じであり、設計されるソフトウェア開発用半導体集積回路１０２も実施の形態１と同じである。ソフトウェア開発用パッドの切断工程５０１においては、ソフトウェア開発用半導体集積回路１０２のチップからソフトウェア開発専用のパッド領域を切断し、小型基板用半導体集積回路５０２を作成する。 (Embodiment 3)
FIG. 5 is a flowchart showing a method for producing a semiconductor integrated circuit according to the third embodiment of the present invention. 5, the software development semiconductor integrated circuit design step 101 and the software development step 103 are the same as the corresponding steps of the first embodiment shown in FIG. 1, and the designed software development semiconductor integrated circuit 102 is also implemented. It is the same as Form 1. In the software development pad cutting step 501, a pad area dedicated to software development is cut from the chip of the software development semiconductor integrated circuit 102 to create a semiconductor integrated circuit 502 for a small substrate.

図６は本実施の形態に係る半導体集積回路の作成方法を説明する構成図であり、ソフトウェア開発用半導体集積回路１０２のレイアウトにおいて、ソフトウェア開発用パッドを切断線６０１で物理的に切断する様子を示している。このように、本実施の形態の半導体集積回路の作成方法によれば、ソフトウェア開発用半導体集積回路のチップからソフトウェア開発専用のパッド領域を切断することにより、半導体集積回路を小型にすることができる。この方法は、まずソフトウェア開発用半導体集積回路を製造するものであるため、半導体集積回路の低コスト化は望めず、量産には適しないが、必要な半導体集積回路が限定数量である場合などにおいて、ソフトウェア開発用半導体集積回路を小型化して実製品に有効に活用することができる。   FIG. 6 is a block diagram for explaining a method for producing a semiconductor integrated circuit according to the present embodiment. In the layout of the software development semiconductor integrated circuit 102, the state in which the software development pad is physically cut by the cutting line 601 is shown. Show. As described above, according to the method for producing a semiconductor integrated circuit of the present embodiment, the semiconductor integrated circuit can be reduced in size by cutting the pad area dedicated to software development from the chip of the semiconductor integrated circuit for software development. . In this method, first, a semiconductor integrated circuit for software development is manufactured. Therefore, it is not possible to reduce the cost of the semiconductor integrated circuit, and it is not suitable for mass production. However, in a case where the required number of semiconductor integrated circuits is limited. The semiconductor integrated circuit for software development can be miniaturized and effectively used in actual products.

本発明の半導体集積回路の設計方法は、チップ評価やソフトウェア開発には多数のパッドが用意されたソフトウェア開発用半導体集積回路を使用し、このソフトウェア開発用半導体集積回路のレイアウトデータからソフトウェア開発用パッドを取り除いて量産用半導体集積回路を設計することで、量産用半導体集積回路を容易に小型化し、低コスト化することができるという効果を有し、半導体集積回路のチップ評価やソフトウェア開発のために必要な多数のパッドを提供しながら実装面積の削減を可能にする技術等として有用である。   The semiconductor integrated circuit design method of the present invention uses a software development semiconductor integrated circuit in which a large number of pads are prepared for chip evaluation and software development. From the layout data of the software development semiconductor integrated circuit, the software development pad is used. Designing a mass-produced semiconductor integrated circuit by removing the chip has the effect of easily reducing the size and cost of the mass-produced semiconductor integrated circuit. For chip evaluation of semiconductor integrated circuits and software development This is useful as a technique that enables a reduction in mounting area while providing a large number of necessary pads.

本発明の実施の形態１に係る半導体集積回路の設計方法を示すフロー図。1 is a flowchart showing a method for designing a semiconductor integrated circuit according to a first embodiment of the present invention. 本発明の実施の形態１に係る半導体集積回路の構成図。1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. 本発明の実施の形態２に係る半導体集積回路の設計方法を示すフロー図。The flowchart which shows the design method of the semiconductor integrated circuit which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体集積回路の構成図。The block diagram of the semiconductor integrated circuit which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体集積回路の作成方法を示すフロー図。FIG. 9 is a flowchart showing a method for producing a semiconductor integrated circuit according to Embodiment 3 of the present invention. 本発明の実施の形態３に係る半導体集積回路の構成図。The block diagram of the semiconductor integrated circuit which concerns on Embodiment 3 of this invention. 従来の半導体集積回路の構成図。The block diagram of the conventional semiconductor integrated circuit.

符号の説明Explanation of symbols

１０１、３０１ ソフトウェア開発用半導体集積回路設計工程
１０２、３０２ ソフトウェア開発用半導体集積回路
１０３ ソフトウェア開発工程
１０４、３０４ レイアウトデータ
１０５ ソフトウェア開発用パッド削除工程
１０６、３０６ 量産用半導体集積回路
２０１ 入出力セル
２０２ ソフトウェア開発用パッド
２０３ 通常パッド
３０５ ソフトウェア開発用パッドおよび入出力セル削除工程
４０１ ソフトウェア開発パッド用入出力セル
４０２ ソフトウェア開発用パッド
４０３ 通常パッド用入出力セル
４０４ 通常パッド
５０１ ソフトウェア開発用パッドの切断工程
５０２ 小型基板用半導体集積回路
６０１ 切断線
７０１、７０２ パッド
７０３ 入出力セル
７０４ 内部セル領域 101, 301 Software development semiconductor integrated circuit design process 102, 302 Software development semiconductor integrated circuit 103 Software development process 104, 304 Layout data 105 Software development pad deletion process 106, 306 Mass production semiconductor integrated circuit 201 Input / output cell 202 Software Development pad 203 Normal pad 305 Software development pad and input / output cell deletion process 401 Software development pad input / output cell 402 Software development pad 403 Normal pad input / output cell 404 Normal pad 501 Software development pad cutting process 502 Compact Semiconductor integrated circuit for substrate 601 Cutting line 701, 702 Pad 703 Input / output cell 704 Internal cell region

Claims (4)

外部接続用の複数のパッドと、論理回路を形成する内部セルと前記パッドとの間で信号の受け渡しを行う入出力セルとを備える半導体集積回路の設計方法であって、
前記パッドを前記半導体集積回路を用いたソフトウェア開発のみにおいて使用されるソフトウェア開発用パッドと前記ソフトウェア開発用パッド以外の通常パッドとに区分し、前記ソフトウェア開発用パッドの配置領域を前記通常パッドを配置する領域の外側にして前記半導体集積回路をソフトウェア開発用半導体集積回路として設計する工程と、
前記ソフトウェア開発用半導体集積回路のレイアウトデータから前記ソフトウェア開発用パッドを取り除いて量産用半導体集積回路を設計する工程と、
を有する半導体集積回路の設計方法。 A method for designing a semiconductor integrated circuit comprising a plurality of pads for external connection, an internal cell forming a logic circuit, and an input / output cell for passing signals between the pads,
The pad is divided into a software development pad used only in software development using the semiconductor integrated circuit and a normal pad other than the software development pad, and the arrangement area of the software development pad is arranged in the normal pad. Designing the semiconductor integrated circuit as a software development semiconductor integrated circuit outside the area to be performed;
Removing the software development pad from the layout data of the software development semiconductor integrated circuit to design a mass production semiconductor integrated circuit;
A method for designing a semiconductor integrated circuit. 前記ソフトウェア開発用パッドを前記入出力セルを配置する領域の外側に配置し、前記通常パッドを前記入出力セルを配置する領域の内側に配置する請求項１記載の半導体集積回路の設計方法。   2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the software development pad is arranged outside a region where the input / output cells are arranged, and the normal pad is arranged inside a region where the input / output cells are arranged. 外部接続用の複数のパッドと、論理回路を形成する内部セルと前記パッドとの間で信号の受け渡しを行う入出力セルとを備える半導体集積回路の設計方法であって、
前記パッドおよび前記入出力セルを、前記半導体集積回路を用いたソフトウェア開発のみにおいて使用されるソフトウェア開発用パッドおよび前記ソフトウェア開発用パッドに接続される入出力セルと、前記ソフトウェア開発用パッド以外の通常パッドおよび前記通常パッドに接続される入出力セルとに区分し、前記ソフトウェア開発用パッドおよび前記ソフトウェア開発用パッドに接続される入出力セルの配置領域を、前記通常パッドおよび前記通常パッドに接続される入出力セルを配置する領域の外側にして前記半導体集積回路をソフトウェア開発用半導体集積回路として設計する工程と、
前記ソフトウェア開発用半導体集積回路のレイアウトデータから前記ソフトウェア開発用パッドおよび前記ソフトウェア開発用パッドに接続される入出力セルを取り除いて量産用半導体集積回路を設計する工程と、
を有する半導体集積回路の設計方法。 A method for designing a semiconductor integrated circuit comprising a plurality of pads for external connection, an internal cell forming a logic circuit, and an input / output cell for passing signals between the pads,
The pad and the input / output cell include a software development pad used only in software development using the semiconductor integrated circuit, an input / output cell connected to the software development pad, and other than the software development pad. The software development pad and the input / output cell connection area connected to the software development pad are connected to the normal pad and the normal pad. Designing the semiconductor integrated circuit as a software development semiconductor integrated circuit outside the region where the input / output cells are arranged; and
Designing a mass production semiconductor integrated circuit by removing the software development pad and the input / output cells connected to the software development pad from the layout data of the software development semiconductor integrated circuit;
A method for designing a semiconductor integrated circuit. 請求項１から３の何れか一項記載の半導体集積回路の設計方法により前記ソフトウェア開発用半導体集積回路として製造したチップから物理的な切断により前記量産用半導体集積回路を製造する方法。   4. A method for manufacturing the semiconductor integrated circuit for mass production by physical cutting from a chip manufactured as the semiconductor integrated circuit for software development by the method for designing a semiconductor integrated circuit according to any one of claims 1 to 3.
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WO2010119762A1 (en) * 2009-04-15 2010-10-21 オリンパスメディカルシステムズ株式会社 Semiconductor device and method for manufacturing semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010119762A1 (en) * 2009-04-15 2010-10-21 オリンパスメディカルシステムズ株式会社 Semiconductor device and method for manufacturing semiconductor device
CN102388455A (en) * 2009-04-15 2012-03-21 奥林巴斯医疗株式会社 Semiconductor device and method for manufacturing semiconductor device

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