JP2005093592A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has such a structure that chips are arranged on a carrier substrate and which can relieve defective devices caused by poor assembling of interconnections. <P>SOLUTION: In the semiconductor device 100, inner circuits 7 and 8 are connected to lands 6 on the carrier substrate 3 whereon chips 1 and 2 are stacked, through terminals 12 and 15 on the chips 1 and 2 whereon the inner circuits 7 and 8 are mounted. The semiconductor device 100 includes auxiliary terminals 13 and 16 on the chips 1 and 2 which are connected to the lands 6, terminal switching circuits 9 and 10 for switching the connection between the inner circuits 7 and 8 and the lands 6 through the terminals 12 and 15 into connection through the auxiliary terminals 13 and 16, and external terminals 11 and 14 for controlling the terminal switching circuits 9 and 10 from outside. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a chip and a carrier substrate are stacked, and particularly to a technique for relieving a defective device.

  In recent years, demands for smaller, lighter and more advanced functions such as mobile phones and videos have been increasing, and they are equipped with semiconductor integrated circuit chips used in these products and have the same size as semiconductor integrated circuit chips. Small packages are mass-produced. These semiconductor integrated circuit chips have a structure arranged on a substrate, and a mounting technique of this structure is expected as a technique for increasing the functionality of a system and increasing the capacity of a memory.

  FIG. 4 is a diagram showing a configuration of a conventional semiconductor device. As an example, a semiconductor device containing two chips is shown. The semiconductor device 400 mainly supports the chips 31 and 32, forms lands 36 necessary for mounting, and further carries a carrier substrate 33 provided with wiring for outputting signals from the chips 31 and 32 to the lands 36. The wiring pattern 34 formed on the carrier substrate 33, the wires 35 for connecting the chips 31 and 32 and the carrier substrate 33, and the like. The chips 31 and 32 include internal circuits 37 and 38, respectively. In the chip 31 or 32, the signal lines of the internal circuits 37 and 38 are input / output from the land 36 via the wire 35 and the wiring pattern 34.

  In the conventional configuration, defective devices caused by wire connection during assembly of semiconductor devices are an issue. However, if the number of terminals arranged on the chip, integration of devices, and miniaturization are advanced, wire assembly defects will occur. The rate will increase and the number of devices with poor assembly will increase. In addition, since a device having a defectively assembled wire cannot be partially corrected or removed, the product yield decreases when a defectively assembled wire is generated.

For this reason, for example, a semiconductor structure that utilizes the remaining devices by cutting a defective wire and invalidating a device portion connected to the wire has been conventionally proposed (for example, Patent Document 1). reference).
Japanese Patent Application Laid-Open No. 8-279588 (page 5, FIG. 1)

  However, the above-described conventional semiconductor structure uses only a normal device while disabling a device including a defective assembly of the wire. Therefore, although the probability that the product is discarded as a defective product is reduced, it does not contribute to the reduction in wire assembly failure, so that the yield as a complete product is not improved and there is a problem that the cost loss is large. Further, if the number of terminals on the chip increases, the occurrence rate of wiring assembly defects increases, and the cost loss increases.

  Therefore, the present invention has been made in view of the above-described conventional problems, and provides a semiconductor device capable of relieving a defective device due to a wiring assembly failure in a semiconductor device in which a chip is arranged on a carrier substrate. Objective.

  The semiconductor device according to the present invention is a semiconductor device in which the internal circuit is connected to a land on a carrier substrate on which the chip is stacked via a terminal on a chip on which the internal circuit is mounted, and the semiconductor device is connected to the land. A spare terminal on the chip, a terminal switching means for switching the connection between the internal circuit and the land from the terminal to the spare terminal, and an external terminal for controlling the terminal switching means from the outside, or the terminal And a non-volatile memory that holds a control signal for controlling the switching means.

  With this configuration, when an assembly failure between the internal circuit and the land is found, the connection between the internal circuit and the land is switched from the terminal to the spare terminal by external control or by control of the nonvolatile memory holding the control signal. As a result, it is possible to relieve the assembly failure of the wiring between the internal circuit and the carrier substrate. By switching by control from the outside, the circuit scale arranged on the chip can be reduced, and by switching by control of the nonvolatile memory, the fixed change on the mounting board due to the presence or absence of assembly failure can be eliminated. Furthermore, the chip connected to the wiring that is poorly assembled can be utilized without being invalidated, and the cost loss can be reduced.

  In the semiconductor device of the present invention, a plurality of chips on which an internal circuit is mounted are connected to each other via a first terminal on the chip, and the second circuit on the chip is connected to the internal circuit. In a semiconductor device in which at least one is connected to a land on a carrier substrate on which the chips are stacked, a spare terminal on the chip for connecting the chips to each other, and a connection between the chips from the first terminal to the spare terminal Terminal switching means for switching to the terminal, and an external terminal for controlling the terminal switching means from the outside, or a non-volatile memory holding a control signal for controlling the terminal switching means .

  With this configuration, when an assembly failure between each chip is found, each chip connection is switched from the terminal to the spare terminal by external control or by control of a nonvolatile memory that holds a control signal. It is possible to remedy an assembly failure of wiring in an assembly process between chips. By switching by control from the outside, the circuit scale arranged on the chip can be reduced, and by switching by control of the nonvolatile memory, the fixed change on the mounting board due to the presence or absence of assembly failure can be eliminated. Further, the chip connected to the assembly failure wiring can be utilized without being invalidated, and the cost loss can be reduced.

  According to the semiconductor device of the present invention, when an assembly failure between the internal circuit and the land is found, the assembly failure in the wiring between the internal circuit and the carrier substrate is performed by switching the connection between the internal circuit and the land from the terminal to the spare terminal. Can be remedied. In addition, the chip connected to the wiring that is defective in assembly can be utilized without being invalidated, and the cost loss can be reduced.

  Further, according to the semiconductor device of the present invention, when an assembly failure between the chips is found, the assembly failure in the wiring between the chips can be remedied by switching the connection between the chips from the terminal to the spare terminal. . In addition, the chip connected to the wiring that is defective in assembly can be utilized without being invalidated, and the cost loss can be reduced.

  Hereinafter, a semiconductor device of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device 100 mainly supports the chips 1 and 2, forms lands 6 necessary for mounting, and further has a carrier substrate 3 provided with wiring for outputting signals from the chips 1 and 2 to the lands 6. The wiring pattern 4 formed on the carrier substrate 3 and the wires 5 connecting the chips 1 and 2 and the carrier substrate 3 are formed. The chip 1 and the chip 2 include an internal circuit 7 and an internal circuit 8, respectively, and further include a terminal switching circuit 9 and a terminal switching circuit 10 connected to the internal circuit 7 and the internal circuit 8.

  Further, the chip 1 is formed with a control external terminal 11 for controlling the terminal switching circuit 9 from the outside, a normally used terminal 12, and a spare terminal 13 used when the terminal 12 is not assembled correctly. Similarly, the chip 2 includes a control external terminal 14 for controlling the terminal switching circuit 10 from the outside, a terminal 15 that is normally used, and a spare terminal 16 that is used when the terminal 15 is not assembled correctly. .

  Next, the terminal switching operation of the semiconductor device 100 configured as described above will be described.

  The terminal switching circuit 9 in the chip 1 sets the spare terminal 13 to high impedance when the input of the control external terminal 11 is “H”, and sets the terminal 12 to high impedance when “L”. Is set in advance to input / output signals. Similarly, the terminal switching circuit 10 in the chip 2 sets the spare terminal 16 to high impedance when the input of the control external terminal 14 is “H”, and sets the terminal 15 to high impedance when “L”. It is set in advance to input / output signals from the spare terminal 16.

  In the chip 1, when the connection between the internal circuit 7 and the land 6 is normal, by fixing the input of the external terminal 11 for control to “H” on the carrier substrate, the terminal switching circuit 9 allows the signal from the terminal 12 to be transmitted. Switch to input / output. On the other hand, when the assembly of the terminal 12 is defective and the connection of the spare terminal 13 is normal, the signal from the spare terminal 13 is fixed by fixing the input of the control external terminal 11 to “L” on the carrier board. Switch to input / output.

  In the chip 2, when the connection between the internal circuit 7 and the land 6 is normal, the terminal switching circuit 10 is connected to the terminal 15 by fixing the input of the control external terminal 14 to “H” on the carrier substrate. Switch to input / output signal. On the other hand, when the assembly of the terminal 15 is defective and the connection of the spare terminal 16 is normal, the signal from the spare terminal 16 is fixed by fixing the input of the control external terminal 14 to “L” on the carrier board. Switch to input / output.

  As described above, by changing the input to the control external terminal of each chip, if there is an assembly failure in the terminal, switching to the spare terminal and inputting / outputting the signal, the internal circuit and carrier Wiring assembly failures in the assembly process with the substrate can be remedied.

  FIG. 2 is a diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention. The semiconductor device 200 mainly supports the chips 1 and 2, forms lands 6 necessary for mounting, and further has a carrier substrate 3 provided with wiring for outputting signals from the chips 1 and 2 to the lands 6. The wiring pattern 4 formed on the carrier substrate 3, the wires 5 connecting the chips 1 and 2 and the carrier substrate 3, and the like. The chip 1 and the chip 2 include an internal circuit 7 and an internal circuit 8, respectively, and further include a terminal switching circuit 9 and a terminal switching circuit 10 connected to the internal circuit 7 and the internal circuit 8.

  The chip 1 also includes a nonvolatile memory 17 that holds a control signal for controlling the terminal switching circuit 9, a terminal 12 that is normally used, a spare terminal 13 that is used when the terminal 12 is not assembled correctly, and a control signal that is nonvolatile. A control external terminal 11 for writing to the volatile memory 17 is formed. Similarly, the chip 2 includes a nonvolatile memory 18 that holds a control signal for controlling the terminal switching circuit 10, a terminal 15 that is normally used, a spare terminal 16 that is used when the terminal 15 is not assembled correctly, and a control signal. A control external terminal 14 for writing in the nonvolatile memory 18 is formed.

  Next, the terminal switching operation of the semiconductor device 200 configured as described above will be described.

  In the chip 1, at the time of inspection, a control signal for setting the spare terminal 13 to high impedance when the connection between the internal circuit of the terminal 12 and the land 6 is normal and setting the terminal 12 to high impedance when the connection is defective is controlled. Write from the external terminal 11 to the nonvolatile memory 17. Similarly, in the chip 2, at the time of inspection, if the connection between the internal circuit of the terminal 15 and the land 6 is normal, the terminal of the spare terminal 16 is set to high impedance, and if it is defective, the terminal 15 is set to high impedance. The control signal to write is written from the control external terminal 14 to the nonvolatile memory 18.

  In the chip 1, when the connection between the internal circuit 7 and the land 6 is normal, the terminal switching circuit 9 switches so as to input / output a signal from the terminal 12 based on the control signal of the nonvolatile memory 17. On the other hand, when the assembly failure occurs in the terminal 12 and the connection of the spare terminal 13 is normal, the terminal switching circuit 9 inputs and outputs signals from the spare terminal 13 based on the control signal of the nonvolatile memory 17. Switch.

  In the chip 2, when the connection between the internal circuit 8 and the land 6 is normal, the terminal switching circuit 10 switches so as to input / output a signal from the terminal 15 based on the control signal of the nonvolatile memory 18. On the other hand, when the assembly failure occurs in the terminal 15 and the connection of the spare terminal 16 is normal, the terminal switching circuit 10 inputs and outputs signals from the spare terminal 16 based on the control signal of the nonvolatile memory 18. Switch.

  As described above, since the terminals can be switched by the terminal switching circuit based on the control signal stored in the nonvolatile memory, the fixing ("H" or "L") on the mounting board due to the presence or absence of assembly failure can be changed. It can be unnecessary. Further, when an assembly failure occurs in the terminal, the signal is input / output by switching to the spare terminal, so that the assembly failure of the wiring in the assembly process of the internal circuit and the carrier substrate can be eliminated.

  FIG. 3 is a diagram showing the configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device 300 mainly supports the chips 1 and 2, forms a land 6 necessary for mounting, and is further provided with wiring for outputting a signal from either the chip 1 or the chip 2 to the land 6. A carrier substrate 3, a wiring pattern 4 formed on the carrier substrate 3, a chip 1, a wire 5 for connecting the chip 2 to each other, and the like. The chip 1 and the chip 2 include an internal circuit 7 and an internal circuit 8, respectively, and further include a terminal switching circuit 9 and a terminal switching circuit 10 connected to the internal circuit 7 and the internal circuit 8.

  The chip 1 is formed with a normally used terminal 20 and a spare terminal 21 used when the terminal 20 is not assembled correctly. The chip 2 holds a control signal for controlling the terminal switching circuit 10. A nonvolatile memory 18, a terminal 20 that is normally used, a spare terminal 21 that is used when the terminal 20 is not assembled correctly, and a control external terminal 14 that writes a control signal to the nonvolatile memory 18 are formed. Further, a control terminal 19 for inputting / outputting a control signal from the nonvolatile memory 18 between the chip 1 and the chip 2 is formed between the terminal switching circuit 9 and the terminal switching circuit 10 of the chip 1 and the chip 2. Has been. In the first and second embodiments, the wire connecting the chip and the carrier substrate is replaced with a wire connecting the chips.

  Next, the terminal switching operation of the semiconductor device 300 configured as described above will be described.

  In the chip 1, at the time of inspection, if the connection between the chip 1 and the chip 2 of the terminal 20 is normal, the spare terminal 21 is set to high impedance, and if it is defective, the control signal is set to set the terminal 20 to high impedance. Write to the nonvolatile memory 18 from the external terminal 14.

  In the chip 1, when the connection between the chip 1 and the chip 2 is normal, the terminal switching circuit 9 inputs and outputs signals from the terminal 20 based on the control signal of the nonvolatile memory 18 input via the control terminal 19. Switch to do. On the other hand, when the assembly failure occurs in the terminal 20 and the connection of the spare terminal 21 is normal, the terminal switching circuit 9 is set to the spare terminal based on the control signal of the nonvolatile memory 18 input through the control terminal 19. 21 so as to input / output signals.

  Further, in the chip 2, when the connection between the chip 1 and the chip 2 is normal, the terminal switching circuit 10 switches so as to input / output a signal from the terminal 20 based on the control signal of the nonvolatile memory 18. On the other hand, when the assembly failure occurs in the terminal 20 and the connection of the spare terminal 21 is normal, the terminal switching circuit 10 inputs and outputs signals from the spare terminal 21 based on the control signal of the nonvolatile memory 18. Switch.

  Although illustration is omitted, it goes without saying that a spare terminal used in the case of poor assembly of terminals may be provided for connection between the internal circuit 8 of the chip 2 and the carrier substrate 3. Switching to the spare terminal is performed by the terminal switching circuit 10.

  As described above, since the terminals can be switched by the terminal switching circuit even in the connection between the chips based on the control signal held in the nonvolatile memory, the fixing (“H” or The change of “L”) can be made unnecessary. Further, when an assembly failure occurs in the terminal, the signal is input / output by switching to the spare terminal, so that the assembly failure of the wiring in the assembly process between the chips can be eliminated.

  In the above embodiment, the semiconductor device in which two chips are stacked has been described as an example. However, the assembly failure relief circuit of the present invention can be applied to a semiconductor device in which three or more chips are stacked. Needless to say, an effect can be expected.

  In the above embodiment, for convenience of explanation, an example in which one spare terminal is provided in each chip of the semiconductor device has been described. However, a plurality of spare terminals are provided at a predetermined ratio with respect to a large number of terminals on the chip. It is preferable. At this time, the predetermined ratio may be determined in consideration of the assembly failure occurrence rate of the semiconductor device and the cost associated with the provision of the spare terminal.

  In the semiconductor device according to the present invention, when an assembly failure between the internal circuit and the land is found, the connection between the internal circuit and the land is switched from the terminal to the spare terminal, thereby reducing the assembly failure in the wiring between the internal circuit and the carrier substrate. The present invention relates to a semiconductor device in which a chip and a carrier substrate are stacked, and has an effect that can be remedied and can be utilized without invalidating a chip connected to a wiring that is poorly assembled. It is useful as a semiconductor device that can be used as a product even if a defect occurs in the wiring connected to the chip in the assembly process of the semiconductor device.

It is a figure which shows the structure of the semiconductor device in Example 1 of this invention. It is a figure which shows the structure of the semiconductor device in Example 2 of this invention. It is a figure which shows the structure of the semiconductor device in Example 3 of this invention. It is a figure which shows the structure of the conventional semiconductor device.

Explanation of symbols

1, 2 Chip 3 Carrier substrate 4 Wiring pattern 5 Wire 9, 10 Terminal switching circuit 11, 14 Control external terminal 12, 15, 20 Terminal 13, 16, 21 Spare terminal 17, 18 Non-volatile memory 19 Control terminal

Claims (4)

A semiconductor device in which the internal circuit is connected to a land on a carrier substrate on which the chip is stacked, via a terminal on a chip on which the internal circuit is mounted,
A spare terminal on the chip connected to the land;
Terminal switching means for switching the connection between the internal circuit and the land from the terminal to the spare terminal;
An external terminal for externally controlling the terminal switching means;
Semiconductor device including A semiconductor device in which the internal circuit is connected to a land on a carrier substrate on which the chip is stacked, via a terminal on a chip on which the internal circuit is mounted,
A spare terminal on the chip connected to the land;
Terminal switching means for switching the connection between the internal circuit and the land from the terminal to the spare terminal;
A non-volatile memory for holding a control signal for controlling the terminal switching means;
Semiconductor device including A plurality of chips on which an internal circuit is mounted are connected to each other via a first terminal on the chip, and at least one of the internal circuits is stacked on the chip via a second terminal on the chip. In a semiconductor device connected to a land on a carrier substrate,
Spare terminals on the chip for connecting the chips to each other;
Terminal switching means for switching the connection between the chips from the first terminal to the spare terminal;
An external terminal for externally controlling the terminal switching means;
A semiconductor device including: A plurality of chips on which an internal circuit is mounted are connected to each other via a first terminal on the chip, and at least one of the internal circuits is stacked on the chip via a second terminal on the chip. In a semiconductor device connected to a land on a carrier substrate,
Spare terminals on the chip for connecting the chips to each other;
Terminal switching means for switching the connection between the chips from the first terminal to the spare terminal;
A non-volatile memory for holding a control signal for controlling the terminal switching means;
A semiconductor device including:

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