KR20060091362A - Pad configuration circuit in semiconductor device using bonding pad - Google Patents

Abstract

A pad arrangement circuit of a semiconductor device using a bonding pad is disclosed. The pad arrangement circuit of the present invention includes a plurality of bonding pads bonded to a power supply voltage or a ground voltage according to a package type to generate a pad type determination signal, and a plurality of input / output buffers and a plurality of input / output buffers provided in the semiconductor device according to the pad type determination signal. Optionally connect the regular pad. Unlike the conventional metal option method, the pad arrangement circuit of the semiconductor device using the bonding passes of the present invention does not require a separate metal mask and a metal process using the same, thereby reducing the complexity of the metal mask and the process. have.

Metal Option Masks, Pad Placement, Bonding Pads

Description

Pad placement circuit of semiconductor device using bonding pads {PAD CONFIGURATION CIRCUIT IN SEMICONDUCTOR DEVICE USING BONDING PAD}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a conceptual diagram illustrating a technique of changing a pad arrangement of a semiconductor device using a metal option method.

2 is a schematic block diagram of a pad arrangement circuit of a semiconductor device according to a preferred embodiment of the present invention.

3 is a diagram illustrating a decoder table in the case where there are eight selectable package types.

4 is a detailed circuit diagram of a decoder configured according to the decoder table of FIG. 3.

FIG. 5 is a detailed circuit diagram illustrating an example in which the multiplexer of FIG. 2 is configured by using a plurality of transmission gate arrays.

* Description of the symbols for the main parts of the drawings *

10: internal circuit area 20: buffer area

30: pad area 32, 34, 36, 38: normal pad

40: metal lines 50, 52, 54: bonding pads

60: pad arrangement determination unit 62: decoder

64: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad arrangement circuit for determining a pad configuration of a semiconductor device, and more particularly to a pad configuration circuit for determining a pad configuration of a semiconductor device.

Portable electronic devices such as mobile phones, portable computers, personal digital assistants, etc., should be small and light in nature. Accordingly, in recent portable electronic devices, a multi chip package (MCP) method in which several semiconductor devices are mounted in one package is widely used. For example, microcontroller units and various types of semiconductor memory devices are provided with one MCP.

Since the various semiconductor devices mounted in the MCP are manufactured by different manufacturers, the devices having the same function often have different pad arrangements. For example, in the case of a semiconductor memory device, a plurality of pads allocated to address input, data input / output, command input, and the like have a different arrangement structure for each manufacturer. In general, the manufacturer of the MCP requires the patch of the semiconductor device to be mounted on the MCP according to the design rules of the semiconductor device manufacturers, so that the manufacturer of the semiconductor device according to the customer's requirements I can change it.

As a technique for different pad arrangements in one semiconductor device, a metal option method is generally used. The metal option method is a technology for producing a semiconductor device using a pad arrangement structure selected according to a customer's request by using various types of metal masks having different pad arrangements.

1 is a conceptual diagram illustrating a technique of changing a pad arrangement of a semiconductor device using a metal option method. Referring to FIG. 1, in a semiconductor memory device, a plurality of buffers 22, 24, 26, and 28 for inputting and outputting various signals, such as an address, data, and command, may be included in the semiconductor chip 10. It is formed in the buffer area 20. The plurality of pads 22, 24, 26, and 28 are arranged in the pad region 30 of the semiconductor chip. The plurality of buffers 22, 24, 26, 28 and the plurality of pads 32, 34, 36, 38 allocated thereto are electrically connected to each other by the metal line 40. The metal line 40 is formed using a metal mask that conforms to the pad arrangement structure defined according to the package type.

Such a metal option method is not a problem when the selectable metal option is limited to several. However, when metal options increase, that is, when various pad arrangements are required, the number of metal masks increases and the process becomes complicated, resulting in a process cost increase.

The present invention is to solve the problem of the conventional metal option method, and includes a plurality of bonding pads in the pad layer of the semiconductor device, by selectively connecting each bonding pad to the power supply voltage or ground voltage pad of the semiconductor device It is an object of the present invention to provide a pad arrangement circuit of a semiconductor device using a bonding pad capable of determining an arrangement.

One aspect of the present invention for achieving the above technical problem relates to a pad arrangement circuit of a semiconductor device using a bonding pad. A pad arrangement circuit of a semiconductor device using a bonding pad of the present invention includes: a pad arrangement determination unit configured to selectively interconnect a plurality of input / output buffers and a plurality of general pads provided in a semiconductor device according to an input pad type determination signal; And a plurality of bonding pads bonded to either a power supply voltage or a ground voltage to generate the pad type determination signal.

Preferably, the pad arrangement determination unit includes a decoder that receives the pad type determination signal, decodes and outputs the multiplexer, and a multiplexer that selectively connects a plurality of input / output buffers and a plurality of general pads according to the decoded signal from the decoder. . The multiplexer includes a transmission gate array configured to electrically connect the plurality of general pads and the plurality of input / output buffers selectively with each other according to the decoded signal. The plurality of transmission gate arrays are formed in a buffer region of a semiconductor chip.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the embodiments of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. In understanding the drawings, it should be noted that like parts are intended to be represented by the same reference numerals as much as possible. And detailed description of known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention is omitted.

(Example)

Hereinafter, the pad arrangement circuit of a semiconductor device using the bonding pad of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic block diagram of a pad arrangement circuit of a semiconductor device according to a preferred embodiment of the present invention. Referring to FIG. 2, the pad patch circuit of the present invention includes a plurality of bonding pads 50, 52, and 54 and a pad arrangement determination circuit 60.

Generally, a semiconductor device has a large number of input / output buffers and a corresponding number of general pads, but in the present embodiment, four input / output buffers 22, 24, 26, 28 and The four general pads 32, 34, 36, and 38 are briefly described.

The plurality of bonding pads 50, 52, and 54 are formed in the pad region 30 of the semiconductor chip, and are bonded to the power supply voltage or the ground voltage according to the package type. The plurality of bonding pads 50, 52, and 54 bonded to the power supply voltage or the ground voltage generate the pad type determination signal BPAD [0: 2] when the power is supplied to the semiconductor device. To provide.

In this embodiment, only three bonding pads 50, 52, 54 are described by way of example, but this is variable depending on the number of package types. For example, when three bonding pads 60 are provided, they may be applied to semiconductor devices having up to eight package types.

The pad arrangement determining unit 60 includes a decoder 62 and a multiplexer 64 formed in the buffer region 20 of the semiconductor chip. The decoder 62 receives the pad type decision signal BPAD [0: 2] and provides the decoded signal PKG_TYPE [0: 7] to the multiplexer 64. The multiplexer 64 electrically connects the plurality of input / output buffers 22, 24, 26, 28 and the plurality of general pads 32, 34, 36, 38 according to the decoded signal PKG_TYPE [0: 7]. do.

In the case of eight selectable package types, the decoder table may be configured as shown in FIG. 3. An example of the decoder 62 configured according to the decoder table shown in FIG. 3 is shown in FIG. 4. As shown in FIG. 4, the decoder 62 may be implemented by a combination of a plurality of inverters IV1 to IV3, a plurality of NAND gates ND10 to ND17, and another plurality of inverters IV10 to IV17. Can be. The decoder 62 shown here is merely shown as an example, and it is obvious that various other forms are possible.

FIG. 5 is a detailed circuit diagram illustrating an example of implementing the multiplexer of FIG. 2 into a plurality of transmission gate arrays. As shown in Fig. 5, in the present embodiment, the multiplexer 64 is composed of a transmission gate array and has a structure of eight rows and four columns. The matrix structure of the transmission gate array is determined by the package type of the semiconductor device and the number of general pads.

One end of each column of the transmission gate array is sequentially connected to the general pads 32, 34, 36, 38, and the other end is selectively connected to any one of the plurality of buffers 22, 24, 26, 28 according to the package type. Connected. The four transmission gates constituting each row are controlled by turn-on / turn-off by the decoded signals PKG_TYPE [0: 7] and the signals inverted by the plurality of inverters IV20 to IV27, and one package The pad arrangement structure defined according to the type allows the plurality of general pads 32, 34, 36, and 38 and the plurality of buffers 22, 24, 26, and 28 to be selectively connected to each other.

As described above, in the pad arrangement circuit of the present invention, since the plurality of bonding pads 50, 52, and 54 are simply bonded to the power supply voltage or the ground voltage according to the package type of the semiconductor device, the plurality of general pads 32 are easily provided. Pads 34, 36, 38 can be determined. That is, the number of bonding pads 50, 52, and 54 suitably used is determined according to the package type and the number of general pads 32, 34, 36, and 38, and the decoder 62 and the multiplexer 64 are appropriately determined. Can be controlled.

As described above, the present invention has been described with reference to the embodiments illustrated in the drawings, which are merely exemplary, and various modifications and equivalent other embodiments of the present invention may be made by those skilled in the art to which the present invention pertains. You can see that it is possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the pad arrangement circuit of the semiconductor device using the bonding passes of the present invention as described above, unlike the conventional metal option method, a separate metal mask and a metal process using the same do not require a metal mask and process according to the package type Can reduce the complexity.

Claims (4)

A pad arrangement determiner configured to selectively interconnect a plurality of input / output buffers and a plurality of general pads provided in the semiconductor device according to the input pad type determination signal; And And a plurality of bonding pads bonded to any one of a power supply voltage and a ground voltage to generate the pad type determination signal. The method of claim 1, wherein the pad arrangement determination unit A decoder configured to receive and decode the pad type determination signal; And And a multiplexer for selectively coupling a plurality of input / output buffers and a plurality of general pads in accordance with a signal decoded from a decoder. The method of claim 2, wherein the multiplexer And a transmission gate array configured to electrically connect a plurality of general pads and a plurality of input / output buffers to each other selectively in accordance with the decoded signal. The method of claim 3, wherein the plurality of transmission gate arrays A pad arrangement circuit of a semiconductor device using bonding pads, which is formed in a buffer region of a semiconductor chip.

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