JP3052937B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a self-test function, and more particularly, to a semiconductor device having a reduced chip area by reducing the number of signal wirings inside the device.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices such as IC memories,
There is an increasing demand for reducing the cost per chip or providing high added value, and a multifunctional design is desired. Since the number of banks, the number of refresh cycles, the number of output I / Os, and the like are designed as a product mode by a bonding option or the like, the number of operation modes to be tested increases, and the number of mode signal lines increases accordingly. It tends to increase.

In a semiconductor device which is required to have multiple functions and a reduced chip size, the reduction in the number of signal wirings is important. FIG. 8 is a schematic diagram showing a wiring state of a peripheral region in a conventional semiconductor device. The semiconductor device has a self-test function, a memory cell 20, a mode signal generating circuit 21 for generating a plurality of mode signals corresponding to the operation mode of the semiconductor device, and a semiconductor device in an operation mode corresponding to the generated mode signal. , A test signal generating circuit 22 for generating a plurality of test signals for performing the test, and a mode signal generating circuit 21 and a decoder circuit 24 for decoding each signal sent from the test signal generating circuit 22.

In the conventional semiconductor device, the mode signal generation circuit 21 and the test signal generation circuit 22 determine the mode signals M0 to M2 and the test signals T0 to T2 via the mode signal line 23 and the test signal line 25, respectively. The decoder circuit 24 restores the mode signal and the test signal transmitted via the predetermined area. FIG.
Although the decoder circuit 24 is drawn at only one place for convenience, the decoder circuit 24 actually sets the mode signals M0 to M2.
And the test signals T0 to T2 are distributed and placed at various locations.

[0005]

In the above-mentioned conventional semiconductor device, signal lines other than the critical path, for example, signal lines for transmitting a mode signal determined at the time of power-on and a test signal used only at the time of a test, have a high speed. Is a signal that is not required, the wiring area occupies the same area as the critical path. In other words, contrary to the demand for simplifying the wiring as much as possible and reducing the size of the chip, the signals from the mode signal generating circuit 21 and the test signal generating circuit 22 are each 3 bits, that is, 6 bits in total, and a total of 6 signal lines Through the peripheral area of the memory cell 20.

In view of the above, the present invention provides a semiconductor device capable of reducing the chip area by reducing the number of signal lines for transmitting a mode signal and a test signal, and which can be expected to reduce the cost associated therewith. The purpose is to provide.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention comprises: a mode signal generating circuit for generating a plurality of mode signals corresponding to operation modes of the semiconductor device; A test signal generating circuit for generating a plurality of test signals for performing a test of the semiconductor device in an operation mode corresponding to the operation mode, wherein the mode signal and the test signal are respectively transmitted to a predetermined area via a plurality of signal lines. In the semiconductor device for transmission, an encoder circuit is provided, which encodes the mode signal and the test signal and supplies the encoded signal to the signal line as an encoded signal whose number of bits is smaller than the sum of the number of bits of both the mode signal and the test signal. And

In general, as the memory capacity of a semiconductor device increases, the number of signal lines increases, and it takes a long time to enter a prepared screening mode when performing a screening test for commercialization. It also leads to impairing cost. However, in the semiconductor device of the present invention, by encoding the mode signal and the test signal by the encoder circuit, the number of signals to be transmitted can be reduced to reduce the number of signal lines, and accordingly, the chip area can be reduced. .

Here, it is preferable that the encoder circuit encodes by combining a plurality of the mode signals and the test signals with each other. In this case, the encoder circuit can be realized from a simple circuit.

Further, the mode signal includes first to third mode signals, the test signal includes first to third test signals, respectively, and the encoder circuit receives the second test signal and the third mode signal as inputs. A first NAND gate, a first NOT gate for inverting the output of the first NAND gate, a first NOR gate receiving the output of the first NOT gate and the third test signal, and the first NOR
The second NO that inverts the output of the gate to generate an encode signal
A first logic circuit including a T gate, a second NAND gate receiving the second test signal and the first mode signal,
A third NOT gate for inverting the output of the second NAND gate, a second NOR gate receiving the output of the third NOT gate and the first test signal, and the second NOR
Fourth N which inverts the output of the gate to generate an encode signal
A second logic circuit comprising an OT gate;
A third NOR gate to which a test signal is input, a fifth NOT gate to invert the second mode signal, and the fifth NO
A fourth NOR gate which receives the output of the T gate and the output of the third NOR gate, a fifth NOR gate which receives the first and second test signals, and a sixth which inverts the first mode signal. A NOT gate, a sixth NOR gate receiving an output of the sixth NOT gate and an output of the fifth NOR gate, a seventh NOR gate receiving the first to third test signals, A third NA having an output of a seventh NOR gate and the third mode signal as inputs;
An ND gate, a seventh NOT gate for inverting the output of the third NAND gate, a fourth NAND gate receiving the third test signal and the third mode signal, and the fourth NA
An eighth NOT gate for inverting the output of the ND gate, an eighth NOR gate to which each output of the fourth and sixth NOR gates and the seventh and eighth NOT gates is input, and And a third logic circuit composed of a ninth NOT gate for inverting the output of the NOR gate of (1) to generate an encode signal.

In this case, the encoder circuit can be composed of a relatively simple logic circuit combining a NAND gate, a NOT gate, and a NOR gate.

Preferably, the encoder circuit generates a first signal having a smaller number of bits of the mode signal based on the plurality of mode signals, and generates a first signal based on the plurality of test signals. A smaller number of second signals are generated, and the first and second signals are used as the encode signals. In this case, the encoder circuit can be realized from a simple circuit.

More preferably, the mode signals are first to first.
A third mode signal, wherein the test signal comprises first to third test signals, respectively, and wherein the encoder circuit comprises: a first NOR gate which receives the first and third mode signals;
A first NOT gate that inverts the output of the NOR gate to produce an encode signal; a second NOR gate that receives the second and third mode signals as input; and a second NOT that inverts the output of the second NOR gate to produce an encode signal. A first logic circuit comprising a gate, a third NOR gate to which the first and third test signals are input, a third NOT gate to invert the output of the third NOR gate to generate an encode signal, and the second and the third test signals. (3) a fourth NOR gate to which a test signal is inputted, and a second logic circuit comprising a fourth NOT gate which inverts the output of the fourth NOR gate to produce an encode signal.

In this case, the encoder circuit can be constituted by a relatively simple logic circuit combining the NOT gate and the NOR gate.

[0015]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a schematic diagram showing a wiring state in a peripheral region of a semiconductor device according to the first embodiment of the present invention.

The semiconductor device has a self test function, and has a memory cell 10, a mode signal generating circuit 11 for generating a plurality of mode signals corresponding to the operation modes of the semiconductor device,
The semiconductor device includes a test signal generation circuit 12 for generating a plurality of test signals for testing a semiconductor device in an operation mode corresponding to the generated mode signal, an encoder circuit 16 and a decoder circuit 14. The decoder circuit 14 is a circuit that decodes an encoded signal supplied from the encoder circuit 16 and is used for read / write bus control. The mode signal and the test signal increase with an increase in the operation mode and the type of test, respectively. In the present embodiment, the mode signal generation circuit 11 outputs three mode signals M.
0, M1, and M2 are generated, and the test signal generation circuit 1
Two to three test signals T0, T1, T2 are generated.

The semiconductor device further includes a mode signal generating circuit 1
1 and a mode signal line 13 and a test signal line 15 for transmitting the mode signals M0 to M2 and the test signals T0 to T2, which are non-critical path signals generated by the test signal generation circuit 12, to the encoder circuit 16. ing. Mode signal generation circuit 11, test signal generation circuit 12
And the encoder circuit 16 are arranged adjacent to each other,
Or it is made into one block.

The encoder circuit 16 converts the mode signals M0 to M2 generated by the mode signal generation circuit 11 and the test signals T0 to T2 generated by the test signal generation circuit 12 into a total of 6-bit signals to form a binary signal. The data is encoded into bits and transmitted as encoded signals S0 to S3 to a predetermined area via four encoded signal lines 17.

In FIG. 1, for convenience, the decoder circuit 14 is shown only at one place. However, in practice, the decoder circuits 14 are dispersedly arranged at various places to which the encode signals S0 to S3 are transmitted. Between the encoder circuit 16 and the decoder circuits 14 at various locations, an encode signal line 17 passing through the peripheral area of the memory cell 10 is wired.

Various tests in various test modes switched using a plurality of mode signals and test signals include:
In commercialization, it is indispensable for failure analysis and high reliability pursuit. Usually, the test mode is distinguished from the normal mode (normal operation), and is performed by a test mode entry method using an address key.

As described above, in the semiconductor device of this embodiment, the signals M0 to M2 and T0 to T
The encoding signal lines 17 are reduced to four by binarizing and encoding the two combination patterns.

FIG. 2 shows an encoding table of a combination pattern of a test signal and a mode signal in the embodiment. In the encoding table, no more than two mode signals M0 to M2 are selected at the same time, and no more than two test signals T0 to T2 are selected at the same time. During normal operation (no test), test signals T0 to T0
It is assumed that T2 is not selected. For example, the mode signal M0 is an operation mode when four I / Os (Input Outputs) are used, the mode signal M1 is an operation mode when eight I / Os are used, and the mode signal M2 is 16 I / Os. The operation modes for the respective cases are shown below. Further, for example, the test signal T0 is a signal for executing a test mode (so-called paratest) for switching the I / O mode, the test signal T1 is a signal for an output system test, and the test signal T2 is a read data in the memory. Signals for executing a comparison test with write data are shown.

In FIG. 2, the normal operation in which all of the test signals T0, T1, and T2 are at the low level, the test signal T0 is at the high level, the test signal T1 is at the high level, and the test signal T2 is at the high level Mode signal M
0 to M2 correspond to each other.

When the test signal is low when the mode signal M0 is high, the combination signal is E0. When the test signal is low when the mode signal M1 is high, the combination signal is E1 and the mode signal M2 is high. If the test signal is at the low level at the level, the combination signal becomes E2. If the test signal T0 is at the high level when the mode signal M0 is at the high level, the combination signal is E3,
If the test signal T0 is at the high level when the mode signal M1 is at the high level, the combination signal is E4, and the mode signal M2
Is high, the combination signal becomes E5 if the test signal T0 is high. If the test signal T1 is at a high level when the mode signal M0 is at a high level, the combination signal is E6. If the test signal T1 is at a high level when the mode signal M1 is at a high level, the combination signal is E7.
If the test signal T1 is at the high level when the mode signal M2 is at the high level, the combination signal becomes E8. When the mode signal M0 is at a high level and the test signal T2 is at a high level, the combination signal is E9. When the mode signal M1 is at a high level, the test signal T2 is at a high level and the combination signal is E10 and the mode signal M2 is at a high level. When the test signal T2 is at the high level when the signal is at the high level, the combination signal is E1
Becomes 1.

FIG. 3 shows a truth table in which E0 to E11 shown in FIG. 2 correspond to the encode signals S0 to S3.
In the truth table, when the combination of the encode signals S3 to S0 is "0000", the combination signal is E0, and when the combination of the encode signals S3 to S0 is "0001", the combination signal is E1 and the encode signal S3. When the combination of S0 to S0 is "0010", the combination signal is E2, and when the combination of the encode signals S3 to S0 is "0011", the combination signal is E3 and the combination of the encode signals S3 to S0 is "0100". ", The combination signal is E4.
The combination of the encode signals S3 to S0 is "010".
In the case of 1 ", the combination signal is E5 and the encode signal S3
When the combination of S0 to S0 is "0110", the combination signal is E6, and the combination of the encode signals S3 to S0 is "0110".
In the case of 11 ″, the combination signal is E7 and the encode signal S
When the combination of 3 to S0 is "1000", the combination signal is E8. Further, when the combination of the encode signals S3 to S0 is "1001", the combination signal is E9, and when the combination of the encode signals S3 to S0 is "1010", the combination signal is E10, and the encode signals S3 to S0.
Is "1011", the combination signal is E1
It becomes 1.

FIG. 4 shows a slightly modified arrangement of the combination signals E0 to E11 in FIG. 3 so that a logic circuit outputting the encode signals S3 to S0 can be easily manufactured. Specifically, in FIG. 3, the combination signals arranged in the order of E0 to E11 are shown in FIG. 4, and in FIG. 4, E0, E1, E2, E7,
E5, E4, E3, E6, E8, E9, E11, E10
The circuit can be simplified if the logic of the encoding is constructed according to this table to form a logic circuit.

FIG. 5 is a diagram formed based on FIGS. 2 and 4.
FIG. 5A shows a logic circuit for obtaining the encode signals S0 to S3, and FIG. 7A shows a logic circuit L for generating the encode signal S3.
C1 and (b) show a logic circuit LC2 that generates the encode signal S2, (c) shows a logic circuit LC3 that generates the encode signal S1, and (d) shows a logic circuit LC4 that generates the encode signal S0. The encoder circuit 16 in the present embodiment is configured by combining the logic circuits LC1 to LC4.

As shown in FIG. 5A, the logic circuit LC1
Are 2-input NAND gates 30, NOT gates 31, 3
It has three and two input NOR gates 32. 2-input NA
The test signal T1 and the mode signal M2 are input to each input terminal of the ND gate 30, respectively. The logical outputs of both inputs are inverted via the NOT gate 31, and the two-input NO
The signal is input to one input terminal of the R gate 32. 2 inputs N
The test signal T2 is input to the other input terminal of the OR gate 32, and its output is inverted via the NOT gate 33 and output as an encode signal S3.

As shown in FIG. 5B, the logic circuit LC2
Is a two-input NAND gate 34, an N7OT gate 35,
37, and a two-input NOR gate 36. 2 inputs N
The test signal T1 and the mode signal M0 are input to the respective input terminals of the AND gate 34, and the logical outputs of both inputs are inverted via the NOT gate 35, and the two-input NO
The signal is input to one input terminal of the R gate 36. 2 inputs N
The test signal T0 is input to the other input terminal of the OR gate 36, and its output is inverted via the NOT gate 37 and output as the encode signal S2.

As shown in FIG. 5C, the logic circuit LC3
Are two-input NOR gates 38, 40, 41, 43, 4
7, a NOT gate 39, 42, 46, 48, 50, a three-input NOR gate 44, a two-input NAND gate 45, and a four-input NOR gate 49 are provided.

A test signal T1 and a test signal T2 are input to respective input terminals of a two-input NOR gate 38, and a logical output of both inputs is input to one input terminal of a two-input NOR gate 40. The mode signal M1 is inverted and input to the other input terminal of the two-input NOR gate 40 via the NOT gate 39, and the logical outputs of both inputs are
It is input to one of the input terminals of a 4-input NOR gate 49.

A test signal T0 and a test signal T1 are input to respective input terminals of a two-input NOR gate 41, and a logical output of both inputs is input to one input terminal of a two-input NOR gate 43. The mode signal M0 is inverted and input to the other input terminal of the two-input NOR gate 43 via the NOT gate 42, and the logical outputs of both inputs are
It is input to one of the input terminals of a 4-input NOR gate 49.

Test signals T0 to T2 are input to respective input terminals of a three-input NOR gate 44, and a logical output of each input is input to one input terminal of a two-input NAND gate 45. The mode signal M2 is input to the other input terminal of the two-input NAND gate 45, and the logical outputs of both inputs are inverted via the NOT gate 46 to form a four-input NOR.
The signal is input to one of the input terminals of the gate 49.

A test signal T2 and a mode signal M2 are input to each input terminal of the two-input NAND gate 47, respectively.
The logical outputs of both inputs are inverted via a NOT gate 48 and input to one of the input terminals of a four-input NOR gate 49. The four-input NOR gate 49 outputs a logical output based on each output from the two-input NOR gates 40 and 43 and the NOT gates 46 and 48 via the NOT gate 50 as an encode signal S1.

As shown in FIG. 5D, the logic circuit LC4
Are two-input NOR gates 51, NOT gates 52, 5
5 and 2 input NOR gates 53 and 54 are provided. Each input terminal of the two-input NOR gate 51 has a test signal T1,
T2 are input, and the logical output of both inputs is 2 inputs N
The signal is input to one input terminal of the OR gate 53. A mode signal M0 is input to the other input terminal of the two-input NOR gate 53.
Is inverted by a NOT gate 52 and input, and a two-input NO
The R gate 53 outputs the logical output of both inputs to a two-input NOR
The signal is output to one input terminal of the gate 54. 2-input NOR
The mode signal M1 is input to the other input terminal of the gate 54, and the two-input NOR gate 54 outputs the logical outputs of both inputs as the encode signal S0 via the NOT gate 55.

In the semiconductor device of the present invention, the encoder circuit 16 can compress a signal, which conventionally required 6 bits, to 4 bits and wire the periphery of the chip as four encode signal lines 17. Also, the encoded signals S0 to S3 encoded by the encoder circuit 16 are supplied to the decoder circuit 1
4 and is used for controlling read / write bus switching and the like.

Next, a second embodiment of the present invention will be described. In the first embodiment, the number of signal lines is reduced by binarizing all combinations of the mode signals M0 to M2 and the test signals T0 to T2. However, in the present embodiment, the mode signals M0 to M2 are Test signals T0 to T2
Are individually encoded, and the encoded signals MS0, M
The number of signal lines is reduced by generating S0 and the encode signals TS0 and TS1.

FIG. 6 is a table showing combinations when the test signal and the mode signal are individually encoded in this embodiment. FIG. 6A shows the case where the mode signals M0 to M3 are used as the basis. b) shows the case based on the test signals T0 to T3, respectively.

In FIG. 6A, the mode signal M0 is shown when both the encode signals MS1 and MS0 are "0", and when the encode signal MS1 is "0" and the encode signal MS0 is "0".
When S0 is "1", the mode signal M1 is shown, the encode signal MS1 is "1", and the encode signal MS0 is "0".
Indicates the mode signal M2 and the encode signal MS1
When both MS0 and MS0 are "1", the mode signal M3 is indicated.

FIG. 6B shows the test signal T0 when both the encode signals TS1 and TS0 are "0", and when the encode signal TS1 is "0" and the encode signal TS0 is "0".
When S0 is "1", it indicates the test signal T1, the encode signal TS1 is "1", and the encode signal TS0 is "0".
Shows the test signal T2 and the encode signal TS1
The test signal T3 is shown when both of the test signals TS0 and TS0 are "1".

FIG. 7 is a logic circuit diagram showing a circuit example of the encoder circuit 16 constructed based on the table of FIG.
Is a logic circuit L that generates the encode signals MS0 and MS1.
C5 and (b) indicate logic circuits LC6 that generate the encode signals TS0 and TS1, respectively.

As shown in FIG. 7A, the logic circuit LC5
Are two-input NOR gates 60 and 61 and NOT gate 6
2, 63. The mode signals M1 and M3 are input to the respective input terminals of the two-input NOR gate 60, and the logical outputs of both inputs are inverted by the NOT gate 62 and output as the encode signal MS0. Mode signals M2 and M3 are input to each input terminal of a two-input NOR gate 61, respectively.
The signal is inverted at 3 and output as an encoded signal MS1.

As shown in FIG. 7B, the logic circuit LC6
Are 2-input NOR gates 64 and 65 and NOT gate 6
6, 67. Test signals T1 and T3 are input to the respective input terminals of the two-input NOR gate 64, and the logical outputs of both inputs are inverted by the NOT gate 66 and output as the encode signal TS0. Test signals T2 and T3 are input to the respective input terminals of the two-input NOR gate 65, and the logical output of both inputs is output to the NOT gate 6
6 and output as an encoded signal TS1.

As described above, in this embodiment, four bits of the mode signals M0 to M3 and four bits of the test signals T0 to T3 are used.
In the case of a semiconductor device having a total of 8 bit signals, the mode signals M0 to M3 may be encoded to encode signals MS0 and MS1, and the test signals T0 to T3 may be encoded to encode signals TS0 and TS1. it can.
As a result, the number of signal lines routed around the chip can be reduced from eight to four, so that the chip area can be reduced.
Cost reduction accompanying this can also be expected.

As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor device of the present invention is not limited to the configuration of the above-described embodiment, but is based on the configuration of the above-described embodiment. Semiconductor devices with various modifications and changes are also included in the scope of the present invention.

[0046]

As described above, according to the semiconductor device of the present invention, the chip area can be reduced by reducing the number of signal lines for transmitting a mode signal and a test signal.
Cost reduction accompanying this can also be expected.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a wiring state of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows an encoding table of a combination pattern in the first embodiment.

FIG. 3 shows an encoding table in which the combination signals shown in FIG. 2 are arranged in order.

FIG. 4 shows an encoding table in which the arrangement of combination signals is changed based on FIGS. 2 and 3;

FIGS. 5A and 5B show a logic circuit configured based on FIGS. 2 and 4, wherein FIG. 5A shows an encode signal S3, FIG. 5B shows an encode signal S2, FIG. 5C shows an encode signal S1, and FIG.
Denotes a logic circuit for generating the encode signal S0.

FIGS. 6A and 6B are tables showing combinations of test signals and mode signals according to the second embodiment of the present invention, wherein FIG. 6A shows a case where mode signals M0 to M3 are used as a base, and FIG. Each case based on T3 is shown.

FIGS. 7A and 7B are logic circuit diagrams illustrating a circuit example of an encoder circuit. FIG. 7A illustrates a logic circuit that generates encode signals MS0 and MS1, and FIG. 7B illustrates a logic circuit that generates encode signals TS0 and TS1.

FIG. 8 is a schematic diagram showing a wiring state of a peripheral region in a conventional semiconductor device.

[Explanation of symbols]

10: Memory cell 11: Mode signal generation circuit 12: Test signal generation circuit 13: Mode signal line 14: Decoder circuit 15: Test signal line 16: Encoder circuit 17: Encode signal line 30, 34, 45: 2-input NAND gate 31 , 33, 35, 37, 39, 42, 46, 48: N
OT gate 32, 36, 38, 40, 41, 43, 47, 51: 2
Input NOR gate 44: 3-input NOR gate 49: 4-input NOR gate 50, 52, 55, 62, 63, 66, 67: NOT gate 53, 54, 60, 63, 64, 65: 2-input NOR gate E0 to E11 : Combination signal LC1 to LC6: Logic circuit M0 to M3: Mode signal MS1, MS0: Encode signal S0 to S3: Encode signal T0 to T3: Test signal TS1, TS0: Encode signal

Claims (5)

(57) [Claims] 1. A mode signal generating circuit for generating a plurality of mode signals corresponding to an operation mode of a semiconductor device, and a plurality of test signals for testing the semiconductor device in an operation mode corresponding to the generated mode signal And a test signal generating circuit that generates the test signal and transmits the mode signal and the test signal to a predetermined region via a plurality of signal lines, respectively. A semiconductor device, comprising: an encoder circuit that supplies an encode signal smaller than the sum of the number of bits of both the mode signal and the test signal to the signal line. 2. The semiconductor device according to claim 1, wherein said encoder circuit encodes by combining a plurality of said mode signals and test signals. 3. The method according to claim 1, wherein the mode signal comprises first to third mode signals, and the test signal comprises first to third test signals. The encoder circuit receives the second test signal and the third mode signal as inputs. The first NAND gate, the first N
A first NOT gate that inverts the output of the AND gate, a first NOR gate that receives the output of the first NOT gate and the third test signal, and a second NOT gate that inverts the output of the first NOR gate and generates an encode signal A first logic circuit comprising: a second NAND gate receiving the second test signal and the first mode signal; a third NOT gate for inverting an output of the second NAND gate; an output of the third NOT gate; A second logic circuit including a second NOR gate receiving a signal, a fourth NOT gate inverting the output of the second NOR gate to generate an encode signal, and receiving the second and third test signals as inputs. A third NOR gate, a fifth NOT gate for inverting the second mode signal, an output of the fifth NOT gate, Fourth NOR gate which receives the output of 3NOR gate, said first
And a fifth NOR gate receiving the second test signal as an input,
A sixth NOT gate for inverting the first mode signal, a sixth NOR gate to which the output of the sixth NOT gate and the output of the fifth NOR gate are input, and the first to third test signals. A seventh NOR gate which receives an input, a third NAND gate which receives the output of the seventh NOR gate and the third mode signal, a seventh NOT gate which inverts the output of the third NAND gate, and the third A fourth NAND gate to which the test signal and the third mode signal are input, and an eighth N for inverting the output of the fourth NAND gate
An OT gate, an eighth NOR gate to which respective outputs of the fourth and sixth NOR gates, and the seventh and eighth NOT gates are input, and an output obtained by inverting and encoding the output of the eighth NOR gate 3. The semiconductor device according to claim 2, further comprising: a third logic circuit including a ninth NOT gate serving as a signal. 4. The encoder circuit generates a first signal that is smaller than the number of bits of the mode signal based on the plurality of mode signals, and generates a first number of bits of the test signal based on the plurality of test signals. 2. The semiconductor device according to claim 1, wherein a smaller number of second signals are generated, and the first and second signals are used as the encode signals. 5. The method according to claim 1, wherein the mode signal includes first to third mode signals, the test signal includes first to third test signals, and the encoder circuit receives the first and third mode signals as inputs. A first NOR gate, a first NOT gate that inverts the output of the first NOR gate and generates an encode signal,
A first logic circuit including a second NOR gate receiving the second and third mode signals as input, a second NOT gate inverting the output of the second NOR gate to generate an encode signal, and the first and third tests A third NOR gate to which a signal is input, a third NOT gate to invert the output of the third NOR gate to generate an encode signal, a fourth NOR gate to which the second and third test signals are input, and the fourth NOR gate. 5. The semiconductor device according to claim 4, further comprising: a second logic circuit comprising a fourth NOT gate, which inverts an output of the NOR gate to generate an encode signal.