JP3099739B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a multi-bit semiconductor memory device having a test function.

[0002]

2. Description of the Related Art A multi-bit semiconductor memory device has an I / O
Because the number of pins (input / output pins) is large and the number of driver pins and comparator pins provided in the tester is limited when measuring with a memory tester, the number of simultaneous measurements is greatly reduced. Become.

In order to solve this problem, an adapter called an I / O common board has been proposed as a conventional technique. For example, FIG. 15 shows an example of an I / O common board used for testing a semiconductor memory device having 16 bits of I / O as shown in FIG. With this I / O common board, the number of simultaneous measurements is quadrupled.

First, the semiconductor memory device shown in FIG. 12 will be described. In this semiconductor memory device, since the I / O has 16 bits, 16 output buffers Dout0 to Dout0 are provided.
Dout15, 16 input buffers Din0 to Din
15 and 16 pairs of internal I / O buses RW0 to RW15, and 16 pairs of internal I / O buses RW0 to RW15
/ × 8 / × 16 output switching circuit 4 or × 4 / × 8
By switching the output buffer or input buffer connected by the / × 16 input switching circuit 5, the I / O can be changed to a semiconductor memory device having a 4-bit configuration, an 8-bit configuration, or a 16-bit configuration.

Normally, in order to shorten the design / development period and to facilitate management, a semiconductor memory device having a plurality of bits is often designed on the same chip.

Further, referring to FIG. 12, this semiconductor memory device has three configurations (I / O is 4 bits, 8 bits).
Bit, 16 bits) can be changed by selecting whether or not to bond at the time of assembly. The decoder 1 has output signals B × 16, B ×
8 and address signals Y ₀ , Y ₁ , test mode signal TC
In response to the MP, a × 4 / × 8 / × 16 output switching circuit 4, a × 4 / × 8 / × 16 input switching circuit 5, and a test circuit 3 are controlled.

[0007] × 4 / × 8 / × 16 switching circuits 4, 5,
Since one test circuit 3 is provided for every four I / Os, a total of four test circuits are provided.

Next, the operation of the conventional semiconductor memory device will be described.

The bonding option circuit 2 is shown in FIG.
And a mode signal B × 1
Only the signal terminal PAD 6 is bonded to GND (ground potential). The signal φ ₀ is a power-on signal in which the one-shot pulse becomes “H” level only when the power is turned on. Therefore, in this case, the mode signal B × 16 becomes “H” and B × 8 becomes “L”, and a 16-bit configuration is obtained.

FIG. 14 shows a circuit configuration of the decoder circuit 1. When the mode signal B × 16 is at the “H” level, the selection signals S _{0 to} S ₃ all become “H”.

× 4 / × 8 / × 16 output switching circuit 4
Has a configuration as shown in FIG.
× 16 is “H”, the selection signals S _{0 to} S ₃ output from the decoder circuit 1 are all “H”, and the test mode signal TCMP is “L” at normal times, so that the transfer gates 300, 301, 312, 313, 322, 323,
334 and 335 are turned on, and 16 pairs of internal I / O
The buses RW0 to RW15 are respectively provided with output buffers Dout.
0 to Dout15 and output to I / O1 to I / O16.

Regarding the output buffer circuit, I / O1, I / O
Dout0 corresponding to / O5, I / O9, I / 013,
FIG. 5A shows Dout4, Dout8, and Dout12.
And other output buffer circuits (for example, Dout1 etc.)
Is shown in FIG. 5 (b).

At the time of writing, in the case of a 16-bit configuration (mode signal B × 16 is “H”), similarly, in the × 4 / × 8 / × 16 input switching circuit 5 shown in FIG. 600, 601, 612, 613, 6
22, 623, 634, and 635 are turned on, and 16 pairs of internal I / O buses RW0 to RW15
in0 to Din15.

FIG. 7 shows an example of the configuration of the input buffer circuit. Referring to FIG. 7, Pch transistor 71 and Nch
With the transistor 72, the signal φw becomes “H” and Nc
When the h transistor 73 is turned on, the I / On terminal I / O
The inverter operates as an inverter that receives the input signal of n and inverts and outputs the inverted signal. The inverted signal is latched by the flip-flop including the inverters 76 and 77 via the transfer gate 75, the normal output is DINnT, and the inverted output is DINn.
nN.

Next, in the I / O compression test mode in which the test mode signal TCMP for controlling the I / O compression test mode is set to "H", the .times.4 / .times.8 / .times.16 shown in FIG.
In the output switching circuit 4, the transfer gate 30
Only 0 and 301 are on, transfer gates 310 to 3
55 is off, the MOS transistors 350 to 371 are on, and the internal I / O buses RW0, RW4, RW8, RW15
Are output buffers Dout0, Dout4, Do, respectively.
ut8 and Dout12, and the inputs OUTnN and OUTnT of the other output buffers become “L”. That is, for example, when TCMP = "H", the output of NAND2 becomes "H", the Nch transistors 350 and 351 are turned on, and OUT1N and OUT1T become "L".

In the test circuit 3 shown in FIG.
The four internal I / O buses RW0 to RW3 are compared, and if all match, the determination signal TFAILB0 is set to "H",
If at least one is different, the determination signal TFALB0 becomes "L".

The internal I / O buses RW4 to RW7, RW8 to
The same applies to RW11, RW12 to RW15.

Therefore, if the output buffers Dout0, Dout4, Dout8, and Dout12 shown in FIG. 5A match each other, the data is output,
If they do not match, the impedance becomes high. That is,
Referring to FIG. 5A, determination signal TFALBn is set to "H".
In this case, when the signal φOE (output enable signal) is “H”, the OUTnT signal is inverted by the NAND gate 50 and supplied to the gate of the Nch transistor 54 via the inverter 51 as a non-inversion signal, and the OUTnN signal is also at the logical level. Is supplied to the gate of the Nch transistor 55,
When the OUTnT signal is “H” / “L”, I / On becomes “H” / “L” and the determination signal TFALB0 becomes “L”.
In this case, the gate potentials of the Nch transistors 54 and 55 are set to "L" level, and both of them are turned off (high impedance state).

In the other output buffers shown in FIG. 5B, since both OUTnN and OUTnT are "L", both the transistors 56 and 57 are turned off.
High impedance.

At the time of writing, × 4 / × 8 / × 1 shown in FIG.
In the 6-input switching circuit 5, the test mode signal TC
Since MP is “H”, the transfer gate 600,
601, 610, 611, 620, 621, 630, 6
31 is turned on, and data is simultaneously written from the input buffer Din0 to the four internal I / O buses RW0 to RW3.

Similarly, input buffers Din4, Din
8 and Din12, respectively, the internal I / O bus RW4
RW7 to RW8 to RW11 and RW12 to RW15.

As described above, the test mode signal TC
When MP is “H” (active), 16 I / O is
Reading and writing are performed by compressing to 4 I / O.

FIG. 1 shows an adapter called an I / O common board for efficiently measuring the semiconductor memory device.
This will be described with reference to FIG.

I / O of four semiconductor memory devices M0-M3
Each of the pins is wired-OR connected, and this is connected to the comparator pin of the memory tester.

At this time, in the I / O degeneration test mode (16
I / O pins I / O1, I / O5, I / O9, and I / O13, which are output when the I / O is compressed to 4 I / O, are connected to each other so as not to be wired-ORed.

The power supply terminals (pins) Vcc of the four semiconductor memory devices M0 to M3 can be turned on / off by control signals SW0 to SW3, respectively. The I / O common board thus quadruples the number of simultaneous measurements.

Next, testing of a semiconductor memory device using the I / O common board will be described.

Normally, the control signals SW0 to SW3 are turned on, the power supply terminals of the four semiconductor memories M0 to M3 are connected to a power supply, and all the semiconductor memories are enabled.

The semiconductor memory devices M0 to M3 are connected to I / O
An entry is made to the O-degeneration test mode, and a test is performed simultaneously with four 4 I / O semiconductor memory devices (referred to as "parallel test").

However, in this I / O compression test mode, since 4-bit memory cells are simultaneously tested with the same data (the same data is written to 4 I / O), for example, interference between adjacent memory cells is performed. Cannot be performed using a test pattern (such as a “physical test pattern”). In particular, in a shared sense amplifier type semiconductor memory device that is frequently used to reduce the area of the sense amplifier, memory cells to be tested at the same time often have an adjacent relationship.

Therefore, when testing with such a physical test pattern, the I / O degeneration test mode is reset and a test is performed as a normal 16 I / O semiconductor memory device.

At this time, the control signals SW0 to SW3 are sequentially transmitted.
By setting [SW0 ON only] → [SW1 ON] → [SW2 ON] → [SW3 ON], the semiconductor memory devices M0 → M1 → M2 → M3 are tested one by one in order ( "Serial test"). As described above, conventionally, the semiconductor memory device is tested by using the I / O common board and selectively using the parallel test and the serial test depending on the test pattern.

[0033]

In the conventional semiconductor memory device described above, when a serial test is performed using an I / O common board, it is necessary to switch the semiconductor memory device to be tested by control signals SW0 to SW3. For this reason, the switching time is a useless test time. Further, the test program is complicated because a parallel test and a serial test are mixed.

In the conventional semiconductor memory device, twelve I / O pins that are not output in the I / O degeneration test mode are wired-OR connected for a serial test. Reflected waves are likely to occur and the load becomes heavy, making the I / O common board very difficult.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of increasing the number of simultaneously measured multi-bit semiconductor memory devices and improving test efficiency. Is to do.

[0036]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a multi-bit semiconductor memory.
In a storage device, an internal I / O bus and a data output buffer
Output switching circuit that switches connection with input of circuit
And the output of the data input buffer circuit and the internal I / O bus.
An input switching circuit for switching the connection between the scan, Bondi
To specify the bit configuration from the signaling option circuit
Input signal, address signal, and test mode signal
And decodes these signals to produce the output switching circuit.
And switching in the input switching circuit.
It is characterized with a decoder circuit for outputting a selection signal for controlling the <br/> contain.

Further, the present invention is based on the test mode signal.
A plurality of the internal I / O buses, and
Comprising a test circuit for outputting the data output buffer, before
When the test mode signal is active,
In some cases, the data output buffer with the selected bit configuration
The input of the amplifier connects the internal I / O bus and the output switching circuit.
Other data output buffers connected through and not selected
Is inactivated, and the test circuit has a plurality of internal
The data of the I / O bus is compared and the comparison result is selected.
Data output to one of the data output buffers
If they match, the output of the data output buffer
The data is output from the
Other data that is not selected.
The output of each output buffer is in a high impedance state.
Is, on the other hand, at the time of data writing has been said selected de
Data input to the data input buffer circuit
Data is written to all internal I / O buses in the
It is characterized by being inserted .

The semiconductor memory device of the present invention includes a circuit for changing a bit configuration by a test mode signal. In addition, since a circuit for changing the bit configuration is usually provided by a bonding option or the like as described above, it is only necessary to add a test mode signal, and there is almost no increase in chip area.

[0039]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

Referring to FIG. 1, the read data is 1
6 internal I / O buses RW0 to RW15 are input and × 4
The bit configuration is switched by the / × 8 / × 16 output switching circuit 4, and the write data output from the output buffers Dout0 to Dout15 to the outside is input buffer Di.
Input is performed through n0 to Din15, the bit configuration is switched by a × 4 / × 8 / × 16 input switching circuit 5, and output to the internal I / O buses RW0 to RW15.

In the I / O compression test mode, there is provided a test circuit 3 for comparing the internal I / O buses RW0 to RW15 and outputting to the output buffers Dout0, Dout4, Dout8 and Dout12.

The output switching circuit 4 and the input switching circuit 5 are controlled by the decoder circuit 1.

The decoder circuit 1 receives the mode signals B × 8 and B × 16, the address signals Y 0 and Y 1, and the test signal T × 4 (× 4 test mode) from the bonding option circuit 2, and outputs these signals. It decodes and outputs selection signals S0 to S3 for controlling the output switching circuit 4 and the input switching circuit 5. FIG. 2A shows a decoder circuit 1.
FIG. 2B shows an example of a circuit configuration of the decoder circuit 1.

The case where the semiconductor memory device according to the embodiment of the present invention shown in FIG. 1 is applied to an I / O common board as shown in FIG. 15 will be described below.

In the normal parallel test, an I / O compression test mode (signal TCMP is "H") test is performed. Therefore, in the decoder circuit 1 of FIG. × 16 is set to “H”, the × 4 test mode signal T × 4 is set to “L”, all the selection signals S _{0 to} S ₃ are set to “H”, the mode signal S × 8 is set to “L”, and S × 16 is set to “L”. H "
Becomes

Therefore, at the time of reading, in the output switching circuit 4 shown in FIG.
0, 301 are on, 310-335 are off, and MOS
Since the transistors 350 to 371 are turned on, FIG.
(A) Output buffers Dout0, Dout4, Dout
Inputs of t8 and Dout12 are connected to the internal I / O bus, and output buffers Dout1 to 3 and Dout of FIG.
The inputs of t5 to 7, Dout9 to Dout, and Dout13 to 15 become "L" for both OUTnT and OUTnN.

In the test circuit 3 shown in FIG. 4, the internal I / O buses RW0 to RW3, RW4 to RW
7, the data of RW8 to RW11 and the data of RW12 to RW15 are compared. If they match, the determination signal TFAILn is set to “H”, and if they do not match, “L” is set. , Dut12.

Therefore, when the compared data match (TFAILn is "H"), I / O1, I / O
The data is output from O5, I / O9, and I / O13, and when they do not match, the state is set to a high impedance state, while the other I / O2-4, I / O6-8, I / O10
12 and I / Os 14 to 16 all enter a high impedance state.

The four I / O1, I / O5, and I / O5
O9 and I / O13 are checked by a comparator of the memory tester to determine a defect.

At the time of writing, I / O1, I / O5, I / O5
By inputting data to / O9 and I / O13, the transfer gates 600, 601, 610, 611, 620, 62 in the input switching circuit 5 shown in FIG.
Since 1, 1, 630 and 631 are on, data is written to all internal I / O buses RW0 to RW15.

Next, when the semiconductor memory device is tested using the physical test pattern that has been conventionally used in the serial test, entry is made to the × 4 test mode (the test mode signal T × 4 is set to “H”). And test it,
Testing can be performed in a parallel manner.

Referring to FIG. 2B, in test circuit 1, since test signal T × 4 is at “H”, both mode signals S × 8 and S × 16 are at “L”. The selection signals S _{0 to} S ₃ are signals obtained by decoding the address signals Y ₀ and Y ₁ and are as shown in a truth table of FIG.

In the output switching circuit 4 shown in FIG. 3, when the I / O compression test mode signal TCMP is "L", for example, when the address signal Y0 is "H" and Y1 is "L", only the selection signal S1 is output. Since "H", S0, S2, and S3 become "L", only the transfer gates 310 and 311 are turned on, and the internal I / O bus RW1 and the output buffers OUT0 and R0.
W5 and OUT4, RW9 and OUT8, RW13 and OUT
12 is connected and the MOS transistors 350 to 371 are all turned on, so that the input OUT of another output buffer is
1-3, OUT5-7, OUT9-11, OUT13-
15 becomes "L".

For this reason, I / O1, I / O5, I / O
9, the data is output from the I / O 13 and the others become high impedance.

As described above, by selecting and outputting internal buses from I / O1, I / O5, I / O9, and I / O13 in accordance with the address signals Y ₀ and Y ₁ , respectively, a 4-bit semiconductor memory is provided. Operate as a device.

[0056] During writing also, similarly, in the input switching circuit shown in FIG. 6, I / O compression test mode signal is "L", the address signal Y ₀ is "H", Y ₁ is the time of "L" is only the selection signal S ₁ is _{"H", S 0, S} 2, S 3 goes to "L", the transfer gates 610 and 611 are turned on, I / O1, I / O5 , I / O9, I / The data written from O13 is the internal I / ORW1, R
W5, RW9, and RW13 are written and operate as a 4-bit semiconductor memory device.

Therefore, the memory tester is provided with I / O1, I / O1,
Only the four bits / O5, I / O9, and I / O13 need to be determined, and the test can be performed in parallel.

As described above, in the embodiment of the present invention, the control signal SW0 which is conventionally performed during the serial test is used.
Since the operation of switching the semiconductor memory device to be tested by SW3 is not required, the time can be shortened accordingly.

The four semiconductor memory devices are controlled by control signals SW0 to SW0.
Switching time by SW3 is about 1 second, since there are about 10 physical patterns in one-step selection, about 10 seconds, and there are three steps of normal preliminary selection, normal-temperature selection, and high-temperature selection. In, the test time can be reduced by about 30 seconds.

As a second embodiment of the present invention, FIGS.
FIG. 10 shows a configuration example of the output switching circuit 4.

The first embodiment differs from the first embodiment in a × 4 test mode (test signal T × 4 is set to “H”) and an I / O compression test mode (test signal TCM).
P is set to “H”), the data output is performed by I
Although only / O1, I / O5, I / O9, and I / O13 are present, data is output from all I / Os.

For example, in the × 4 test mode (T × 4 is “H”), the decoder circuit 1 shown in FIG.
When the address signal Y ₀ is “H” and Y ₁ is “L”, the selection signal S ₁ is “H” and S ₀ , S ₂ , and S ₃ are “L”.
T from FIG 9 (a) ₀₀ is "L", from T _10, T FIG 9 (b)
₁₁ are both "H", T ₂₀ from FIG. 10 (a) "L", T ₂₂ is "H", also T _30, T ₃₁ from FIG. 10 (b) "L", T
_Since " ₃₃ " is "H", the transfer gates 810, 811, 812, 813, 822, 82 in FIG.
3, 824 and 825 are turned on.

Therefore, the data I / O1 is RW1, I / O1
O2 outputs data of RW1, I / O3 outputs data of RW2, and I / O4 outputs data of RW3.

I / O5 to I / O6 similarly output data.

To test this semiconductor memory device, an I / O common board as shown in FIG. 11 is used. I /
The O pins are not connected by a wired OR connection, but simply connected as a 4-bit semiconductor memory device, and the remaining I / O pins are connected to a load circuit.

The test is performed in the same manner as described above.
Performed in I / O compression test mode, physical pattern is × 4
Perform in test mode.

In the second embodiment of the present invention, even in the test mode, since data is output from all I / O pins, the test related to output noise has been conventionally performed by a serial test. On the other hand, it can be performed by a parallel test.

Therefore, since the test program is only a parallel test, the test program is similar to a normal semiconductor memory device test program of a 4-bit configuration, and the program is easy.

Furthermore, since there is no wired OR connection in the I / O common board, the risk of reflected waves and the like is reduced, which facilitates the operation.

[0070]

As described above, according to the present invention,
An output switching circuit and an input switching circuit for switching the bit configuration of the semiconductor memory device in accordance with a test mode signal, so that the I / O common board can perform a test in a parallel manner, particularly when testing a physical pattern; As a result, it is not necessary to switch the semiconductor memory device to be tested by the control signal which has been conventionally performed at the time of the serial test, and this time can be reduced.

Further, according to the present invention, since the serial test is not required, the wired-OR connection of the I / O pin is not required, and the influence of the reflected wave or the like which makes the test board difficult to produce is reduced. It works.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIGS. 2A and 2B are diagrams for explaining a decoder circuit according to the first embodiment of the present invention, wherein FIG.
(B) is a circuit diagram.

FIG. 3 is a diagram illustrating a configuration of an output switching circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a test circuit according to the first embodiment of the present invention.

FIG. 5A shows output buffers Dout0, 4, 8, 1;
2 is a diagram illustrating a circuit configuration of FIG. (B) Output buffer D
out1-3, Dout5-7, Dout9-11, D
It is a figure which shows the circuit structure of out13-15.

FIG. 6 is a diagram illustrating a configuration of an input switching circuit according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of input buffers Din0 to Din15 according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of an output switching circuit according to a second embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of an output switching circuit according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of an output switching circuit according to a second embodiment of the present invention.

FIG. 11 is a wiring diagram of a test board used in a second embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 13 is a diagram showing a configuration of a bonding option circuit shown in FIG. 9;

FIG. 14 is a diagram illustrating a configuration of a decoder circuit illustrated in FIG. 9;

FIG. 15 is a wiring diagram of a conventional I / O common board.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Decoder circuit 2 Bonding option circuit 3 Test circuit 4 Output switching circuit 5 Input switching circuit 300-335, 600-635, 800-835 Transfer gate 350-371, 850-871 MOS transistor

Claims (5)

(57) [Claims] In a semiconductor memory device having a multi-bit structure, a connection between an internal I / O bus and an input of a data output buffer circuit is provided.
An output switching circuit for switching connection, an output of a data input buffer circuit, and the internal I / O bus.
An input switching circuit for switching the connection of an address , an address signal, a test mode signal, and a bonding
A mode signal that specifies the bit configuration from the option circuit and
And decode these signals to switch the output.
Switching in the input circuit and the input switching circuit.
A decoder circuit for outputting a selection signal to be controlled ,
The semiconductor memory device which comprises a. 2. A method according to claim 1 , further comprising the steps of:
Compare the internal I / O buses and compare the
A test circuit for outputting to the test mode.
Select when reading data when signal is active
The input of the data output buffer having the
Unit I / O bus and the output switching circuit.
Input of other data output buffers not selected
And the test circuit is configured to store data on the plurality of internal I / O buses.
And compare the comparison result with the selected data output buffer.
Output to one and if the compared data match
Outputs the data from the output of the data output buffer.
If they do not match, the device goes into a high impedance state.
And the output of the other unselected data output buffer is
Both are in a high impedance state, and when writing data, the selected data is input.
A data input circuit for inputting data to the input buffer circuit;
Write the same data to the plurality of internal I / O buses.
2. The semiconductor memory device according to claim 1, wherein 3. The device according to claim 2, wherein the data is based on a second test mode signal.
The coder provides a data output buffer with the selected bit configuration.
Internal I / O bus from the output of the
Select a scan, at the time of reading, in the output switching circuit, wherein
Of the plurality of internal I / O buses, the address signal
And the internal I / O bus selected by the decoder
Is connected to the input of the data output buffer and other data
The input of the output buffer is inactivated, and at the time of writing, the input switching circuit selects
Input from the data input buffer having the
The written data is read by the address signal.
Write to the internal I / O bus selected by the coder,
2. The semiconductor memory device according to claim 1, wherein: 4. An output switching circuit according to claim 1 , wherein
Between the input of the data output buffer and the plurality of internal I / O buses.
In the meantime, the selection signal from the decoder circuit and the bit structure
And / or a mode signal defining the
On / off control by a control signal generated based on the
Characterized by having a controlled transfer gate
The semiconductor memory device according to claim 1. 5. An input switching circuit comprising:
Between the output of the data input buffer and the plurality of internal I / O buses.
Between the selection signal from the decoder circuit and the bit configuration
And / or said test mode
On / off control by control signal generated based on the signal
A transfer gate provided with a transfer gate
The semiconductor memory device according to claim 1.