JP2004326453A - Semiconductor integrated circuit design method and semiconductor integrated circuit design program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly design a semiconductor integrated circuit by dispensing with repeated readjustments when designing the semiconductor integrated circuit by use of a standard cell. <P>SOLUTION: Cell layout (processing 11), buffer insertion/layout (processing 12), wiring (processing 13) and delay calculation (processing 14) are successively carried out, and clock readjustment for optimizing a clock characteristic (readjustment of drive ability of a clock buffer (processing 151)) is carried out based on the delay calculation result. In this readjustment, a desired one is selected from two or more kinds of preliminarily prepared clock buffers differed in the characteristic with the same foot print and having a wiring prohibition area buried therein, and substituted by the inserted/laid-out clock buffer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, by using a plurality of types of clock buffer cells having the same footprint and different characteristics (driving ability and intra-cell delay), only the replacement of the clock buffer cells after wiring is performed, and re-adjustment is not required. The present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit design program that allow a semiconductor integrated circuit to be quickly designed.
[0002]
[Prior art]
FIG. 4 shows a flow of a semiconductor integrated circuit design process using a CAD tool according to the related art. As shown in the figure, assuming that the netlist has been obtained in advance, the cell is first placed at a certain position on the chip (step 41). Next, a buffer is inserted (added) / placed in the clock net by the clock net synthesis (process 42). As a supplementary explanation, in the initial net before the placement / wiring is performed, the clock signal is connected to a large number of flip-flops (FFs). This refers to inserting (adding) / arranging a buffer in the clock net so that the delay (delay) is minimized.
[0003]
Thereafter, after the wiring is performed, the back calculation of the RC (wiring resistance / wiring capacitance) from the actual wiring, that is, the delay calculation in consideration of the RC (wiring resistance / wiring capacitance) is performed (processing 43, 44). ). Based on the result of the delay calculation, the clock is readjusted to optimize the clock characteristics (the drive capability of the clock buffer is readjusted (process 451)) (process 45).
[0004]
However, at the time of the readjustment, in many cases, the cell size becomes larger than the original size or the terminal position of the cell changes, so that relocation to prevent the cells from overlapping (overlapping), The reconnection of the unconnected portion is performed by the change of the terminal position accompanying the cell change (steps 452 and 453). After that, delay calculation is again performed in consideration of RC (wiring resistance / wiring capacitance), and the result of the delay calculation is determined as pass / fail (processes 46 and 47). If the desired result is not obtained in this pass / fail determination, readjustment is performed again (steps 47 and 45).
[0005]
Incidentally, in Patent Literature 1, when data is transferred between a plurality of card boards mounted on a motherboard, the phase variation of a clock signal for latching data is reduced.
[0006]
[Patent Document 1]
JP 2001-53731 A
[Problems to be solved by the invention]
However, in the case of the prior art shown in FIG. 4, if the driving capability of the clock buffer cell is different, the cell size and terminal position are often different accordingly. That is, re-adjustment often requires rearrangement and re-wiring. Depending on the rearrangement / rewiring of the cell, the wiring path may also be changed. However, this wiring path change often results in a desired result in the pass / fail judgment of the delay calculation result after readjustment. However, it is unavoidable that this increases the design period.
[0008]
An object of the present invention is to provide a semiconductor integrated circuit design method and a semiconductor integrated circuit design program that can use a standard cell to design a semiconductor integrated circuit so that re-adjustment is not required repeatedly. To provide.
[0009]
[Means for Solving the Problems]
A semiconductor integrated circuit designing method according to the present invention uses a standard cell, and when a semiconductor integrated circuit is designed, a cell arrangement step of placing the standard cell at a certain position on a chip, and a clock buffer in a clock net by clock net synthesis. A buffer insertion / placement step of inserting / placement, a wiring step, a delay calculation step of performing a delay calculation in consideration of the wiring resistance and the wiring capacity from the actual wiring, and a delay calculation result by the delay calculation step. A plurality of clock buffers having the same footprint, different characteristics, different wiring characteristics, and embedded wiring prohibited areas are selected from a plurality of clock buffers prepared in advance, and inserted / placed. And a buffer replacement step for replacing the clock buffer.
[0010]
As described above, based on the delay calculation result, a desired clock buffer is prepared from a plurality of types of clock buffers in which the footprints are the same, the characteristics are different, and the wiring prohibited area is embedded. Since it is selected and replaced with the clock buffer that has already been inserted / placed, it is not necessary to repeat re-adjustment, so that the semiconductor integrated circuit can be quickly designed.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
First, FIG. 1 shows a flow of a semiconductor integrated circuit design process using a CAD tool according to an embodiment of the present invention. As shown in the figure, assuming that a netlist has been obtained in advance, a cell arrangement for placing a standard cell at a certain position on a chip is performed (process 11). Next, a buffer is inserted (added) / placed in the clock net by clock net synthesis (process 12).
[0012]
Thereafter, after the wiring is performed, a back calculation is performed on the RC (wiring resistance / wiring capacitance) from the actual wiring, that is, a delay calculation is performed in consideration of the RC (wiring resistance / wiring capacitance) (processes 13 and 14). ). Based on the result of the delay calculation, the clock is readjusted to optimize the clock characteristics (the drive capacity of the clock buffer is readjusted (process 151)) (process 15).
[0013]
Therefore, it cannot be denied that the overall process is apparently similar to the above-described semiconductor integrated circuit design processing flow according to the related art. However, a feature of the present invention is a clock readjustment for optimizing the clock characteristics. The readjustment method is clearly distinguishable from the readjustment method according to the prior art.
[0014]
That is, in the present invention, a plurality of types of clock buffers having the same footprint, different characteristics (driving ability and delay time in a cell), and in which a wiring prohibited area is embedded are prepared in advance. This is because a desired one of these clock buffers is selected based on the result of the delay calculation, and is replaced with the already inserted / placed clock buffer. Indeed, this replacement eliminates the need for re-adjustment, which has been required conventionally, and thus allows not only quick design of a semiconductor integrated circuit but also simplification of skew adjustment between clock signals. Is what it is.
[0015]
Now, specific examples of a plurality of types of clock buffer cells prepared in advance will be described with reference to FIGS. 2A to 2C. In this case, FIG. 2A shows only one clock buffer (displayed as a triangular figure) 21 between the input terminal A and the output terminal X, and thus shows a basic one-stage configuration. FIG. 2B shows a case in which three clock buffers 21 are cascaded. The drive capability is the same as that shown in FIG. 2A, but the delay time is set to three times. Generally, the delay time is set to be longer as the number of cascade connection stages increases.
[0016]
FIG. 2C shows a case where two clock buffers 21 are connected in parallel. Although the delay time is the same as that shown in FIG. 2A, the drive capability as a buffer is set to be twice as large. Generally, as the number of parallel connection stages increases, the drive capability is set to be large. However, it is apparent that various clock buffer configurations other than those shown in FIGS. 2A to 2C are conceivable.
[0017]
As described above, the clock buffer according to the present invention is required to have the same footprint. However, if the footprint is the same, the characteristics can be changed only by replacing cells. It is because it is.
[0018]
Here, if the footprint is supplementarily described, the footprint is defined as information on the position, shape, and layer of a cell frame and terminals in a standard cell. In the standard cell, automatic placement and wiring are performed by a CAD tool, and the footprint is information necessary at that time. Incidentally, the cell frame is the outer peripheral frame of the cell, which is usually the outermost peripheral of the metal layer, and the well and the like often protrude from this frame. A figure in the cell when the cells are connected to each other is called a terminal, and the terminal shape is the shape of the figure (for example, the input terminal A in FIGS. 2A to 2C). And output terminal X). Further, the terminal layer is a metal layer used as a terminal.
[0019]
Continuing to explain the wiring prohibited area, FIG. 3A shows a pattern of a metal layer of a buffer (cell). The upwardly-sloping hatched portion indicates a metal 2 pattern corresponding to a cell frame or a terminal figure, and the upwardly-sloping hatched portion indicates a metal 1 pattern. Generally, footprints (information on cell frames and terminal figures) are used in the placement and wiring of standard cells. However, this footprint alone short-circuits the metal 1 pattern when connecting (wiring) to the output terminal X. There is no denying that there is a possibility. Therefore, as shown in FIG. 3B, a wiring prohibited area of metal 1 is inserted / set on the entire surface of the cell so that metal 1 is not used for connection (wiring) to output terminal X.
[0020]
As described above, the semiconductor integrated circuit designing method according to the present invention has been described. However, the contents can be easily considered as a semiconductor integrated circuit designing program.
[0021]
As described above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof. Needless to say, there is.
[0022]
【The invention's effect】
When designing a semiconductor integrated circuit using standard cells, the semiconductor integrated circuit can be quickly designed without the need for re-adjustment.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a semiconductor integrated circuit design processing flow according to an example of the present invention.
FIG. 2 is a diagram showing a specific example of a clock buffer cell according to the present invention.
FIG. 3 is a diagram for explaining a wiring prohibited area according to the present invention.
FIG. 4 is a diagram showing a flow of a semiconductor integrated circuit design process according to the related art.
[Explanation of symbols]
21 ... Clock buffer

Claims (4)

A semiconductor integrated circuit design method using a standard cell,
A cell placement step of placing the standard cell at a certain position on the chip;
A buffer insertion / placement step of inserting / placement of a clock buffer in a clock net by clock net synthesis;
Performing wiring;
A delay calculation step of calculating a delay in consideration of wiring resistance and wiring capacitance from actual wiring,
Based on the delay calculation result of the delay calculation step, a desired one is prepared from a plurality of types of clock buffers prepared in advance, which have the same footprint, different characteristics, and embedded wiring prohibited areas. And a buffer replacement step of replacing the selected and inserted / placed clock buffer. The method for designing a semiconductor integrated circuit according to claim 1,
A method of designing a semiconductor integrated circuit in which skew adjustment between clock signals after wiring is performed by clock buffer replacement in the buffer replacement step. A semiconductor integrated circuit design program used when a semiconductor integrated circuit is designed using standard cells,
A cell placement step of placing the standard cell at a certain position on the chip;
A buffer insertion / placement step of inserting / placement of a clock buffer in a clock net by clock net synthesis;
Performing wiring;
A delay calculation step of calculating a delay in consideration of wiring resistance and wiring capacitance from actual wiring,
Based on the delay calculation result of the delay calculation step, a desired one is prepared from a plurality of types of clock buffers prepared in advance, which have the same footprint, different characteristics, and embedded wiring prohibited areas. A buffer replacement step of replacing a selected and inserted / placed clock buffer. 4. The semiconductor integrated circuit design program according to claim 3, wherein
A semiconductor integrated circuit design program for performing skew adjustment between clock signals after wiring by clock buffer replacement in the buffer replacement step.

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