JP2005129749A - Semiconductor device provided with macro cell for signal distribution - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that power is uselessly consumed in a dummy cell and a driving circuit since conventionally the dummy cell is connected at a part where the using number of signals is small and an equal load structure is attained, in order to suppress a signal arrival time difference between distributed signals in the case of distributing the signals by using a macro cell. <P>SOLUTION: In order to match with the signal propagation time of the macro cell in which the number of output terminals is the maximum number, the driving circuit and a load adjusting circuit are constituted and the plurality of macro cells in which the number of the output terminals is different are prepared. Since the macro cell in which the number of the output terminals is not the maximum number can be constituted of fewer driving circuits than that of the macro cells in which the number of the output terminals is the maximum number, power consumption is reduced. Also, since there is no need of using the dummy cell used in a conventional technique, the power consumption of the entire semiconductor device is reduced. Even after the connection of wiring is completed by the macro cell in which the number of the output terminals is different, it can be switched to the macro cell in which the number of the output terminals is smaller. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a macro cell used for signal distribution, and more particularly to a technique for reducing power consumption of a macro cell without changing a skew, which is a signal arrival time difference between distributed signals.

  When a signal is distributed to many places of use, such as a clock signal, the macro cell used for each stage of the distribution path is made the same type, and the skew is reduced by adjusting the macro cell mounting position and making the wiring between the macro cells equal. The tree structure is widely known.

  Patent Document 1 discloses a semiconductor integrated circuit that can cope with a multiphase clock, reduce clock skew between circuits, and reduce power consumption by using this H-tree structure.

  In addition, the clock signal generator has an H-tree structure at the upper level close to the clock signal generator, and a structure determined by clock tree synthesis at other parts than the upper level, thereby reducing clock skew and reducing the circuit size and power consumption. A distribution circuit is shown in US Pat.

  Further, Patent Document 3 discloses a semiconductor integrated circuit in which power supply noise is reduced without increasing the skew by adjusting the clock buffer at each stage of the clock distribution path.

Japanese Patent Laid-Open No. 2003-152082

JP 2003-78014 A JP 2000-29562 A

  In the above prior art, it is necessary to connect a dummy cell to maintain an equal load structure even when a signal distributed to reduce skew is used, and there is a problem that power is wasted in the dummy cell. there were.

  An object of the present invention is to suppress a signal arrival time difference between distributed signals and reduce power consumption.

  A plurality of macrocells having different numbers of output terminals are prepared by configuring a drive circuit and a load adjustment circuit so as to match the signal propagation time of the macrocell having the maximum number of output terminals. Since the macro cell whose number of output terminals is not the maximum number can be configured with fewer drive circuits than the macro cell whose number of output terminals is the maximum number, power consumption can be reduced. In addition, since it is not necessary to use the dummy cell used in the prior art, the power consumption of the entire semiconductor device can be reduced.

  Even for macrocells with different numbers of output terminals, the number of output terminals can be adjusted even after the wiring connection to the macrocell is completed by determining the mounting position of the macrocell by aligning the positions and sizes of existing terminals. It is possible to switch to a macro cell with few.

  According to the present invention, since unused output terminals and drive circuits can be reduced, power consumption can be reduced. Further, since the macro cell shape is unified, the macro cell can be replaced after the wiring shape is determined, and it is not necessary to change the wiring shape of the signal to be distributed even if there is a design change, so that the development period can be shortened.

  FIG. 1 (a) shows a macro cell having the maximum number of output terminals. The macro cell in FIG. 1 (a) inputs a signal from an input terminal 111a, distributes the signal to output terminals 121a, 122a, 123a, and 124a and outputs it. In addition, since the structure from the input terminal 111a to the output terminal is the same between the output terminals 121a, 122a, 123a and 124a, the signal propagation time from the input terminal to the output terminal is equal between the output terminals 121a, 122a, 123a and 124a. . By performing signal distribution using this macro cell, the signal arrival time difference can be reduced.

  FIG. 1B shows a low power consumption structure macro cell which is an embodiment of the present invention. This is an example in which the output terminals 123a and 124a and their drive circuit 103 are deleted from the macrocell of FIG. 1A to reduce the number of output terminals. At this time, the load adjustment circuit 102 is added so that the signal propagation time from the input terminal 111b to the output terminals 121b and 122b matches the signal propagation time of the macro cell 100 where the number of output terminals is the maximum. As a result, even when signal distribution is performed using a mixture of the macro cell 100 having the maximum number of output terminals and the low power consumption structure macro cell 101, the difference in signal arrival time can be reduced.

  The load adjustment circuit 102 is a circuit added to match the signal propagation time with the macro cell 100 having the maximum number of output terminals, and a drive circuit or a capacitive load can also be used.

  In the low power consumption structure macro cell 101, since the drive circuit 103 is deleted from the macro cell 100 having the maximum number of output terminals, the power consumption can be reduced. Furthermore, since the dummy cells necessary for maintaining the equal load structure in the conventional technique are not necessary in the low power consumption structure macro cell 101, the power consumption of the entire semiconductor device can be reduced.

  FIG. 2 shows an application example of the present invention using FIG. 1 (a) and FIG. 1 (b). When there is a signal use place in a wide range, the range is divided at the signal distribution area boundary 200 and a macro cell is placed in the area to supply a signal to the use place. In the signal distribution area 201 where the number of signals used is large, distribution is performed using the macro cell 100 having the maximum number of output terminals. In the signal distribution area 202 where the number of signals used is small, distribution is performed using the low power consumption structure macro cell 101. Thereby, power consumption can be reduced without increasing the signal arrival time difference between the distributed signals.

  FIG. 3 shows an example of power consumption reduction according to the present invention. In the prior art, as shown in FIG. 3A, a signal is supplied to the signal use location 300 using the macro cell 100 having the maximum number of output terminals. For this reason, when the number of signals used is small, it is necessary to connect the dummy cells 301 and maintain the equal load structure. In the present invention, as shown in FIG. 3B, a signal is supplied only to the signal use location 300 using the low power consumption structure macro cell 101. As a result, the drive circuit 103 and the dummy cell 301 are not required, and power consumption can be reduced.

  FIG. 4 (a) shows an example of the shape of the macro cell 100 having the maximum number of output terminals, and FIG. 4 (b) shows an example of the shape of the low power consumption structure macro cell 101. The shape of the low power consumption structure macro cell 101 shown in FIG. 4B is determined in accordance with the shape of the macro cell 100 having the maximum number of output terminals. In other words, the input terminals 111a and 111b, the output terminals 121a and 121b, and the terminal positions of 122a and 122b that exist in both are made equal, and the macrocells are also made in the same shape. As a result, even after the mounting position of the components to be mounted on the semiconductor device is determined and the wiring shape between the components is determined, the macro cell 100 that has the maximum number of output terminals without changing the wiring shape and low consumption The power structure macrocell 101 can be replaced.

  In the embodiment of the present invention, an inverting logic circuit is used as a drive circuit. However, the present invention can be implemented even when a non-inverting logic circuit or a logical operation circuit such as logical product or logical sum is used.

(a) is a macro cell with the maximum number of output terminals. (b) is a macro cell showing a first embodiment of the present invention. The figure which shows the example of application of this invention. (a) is a figure showing an example of signal distribution using a macro cell with the maximum number of output terminals. (b) is a figure which shows the example of the signal distribution using a low power consumption structure macrocell. (a) is an example of a macro cell shape that maximizes the number of output terminals. (b) is a macro cell shape example of a low power consumption structure macro cell.

Explanation of symbols

100: Macro cell with the maximum number of output terminals,
101 ... Low power consumption structure macro cell,
102 ... Load adjustment circuit,
103 ... unused drive circuit (logic circuit),
104 ... Drive circuit (logic circuit),
111a ... the macro cell input terminal with the maximum number of output terminals,
111b… Low power consumption structure macro cell input pin,
121a ... Macro cell output terminal 1 with the maximum number of output terminals,
121b… Low power consumption structure macro cell output pin 1,
122a ... Macro cell output terminal 2 with the maximum number of output terminals,
122b… Low power consumption structure macro cell output terminal 2,
123a ... the macro cell output terminal 3 with the maximum number of output terminals,
124a ... Macro cell output terminal 4 with the maximum number of output terminals,
200 ... signal distribution area boundary,
201 ... Signal distribution area with many signals used,
202 ... signal distribution area with a small number of signals used,
300… Signal usage point,
301 ... A dummy cell.

Claims (6)

In a semiconductor device having a macro cell for distributing an input signal to a plurality of output terminals,
A first output comprising a plurality of input terminals for inputting the input signal and a plurality of logic circuits for distributing the input signals to a predetermined number of outputs, and outputting a signal output via the logic circuit A first macrocell including a terminal;
Each including at least one second macrocell having a second output terminal obtained by removing a predetermined number of output terminals from the first output terminal;
2. The semiconductor device according to claim 1, wherein the second macro cell has a cell structure in which logic circuits respectively connected to the predetermined number of output terminals are removed. In a semiconductor device having a macro cell for distributing an input signal to a plurality of output terminals,
A first output terminal including a plurality of input terminals for inputting the input signal and a plurality of logic circuits for distributing the input signals to a predetermined number of outputs, and outputting a signal output via the logic circuit; 1 macro cell,
Each including at least one second macrocell having a second output terminal obtained by removing a predetermined number of output terminals from the first output terminal;
The second macro cell removes the logic circuit connected to each of the predetermined number of output terminals, and replaces the connected logic circuit to which the input terminal of the removed logic circuit is connected with a load adjustment circuit. A semiconductor device having a cell structure.   3. The semiconductor device according to claim 2, wherein the load adjustment circuit includes a logic circuit constituting the first or second macro cell.   The semiconductor device according to claim 2, wherein the load adjusting circuit uses a capacitive load.   The semiconductor device according to claim 1, wherein the logic circuit includes a drive circuit having a desired output load.   3. The semiconductor device according to claim 1, wherein a layout shape of each of the first macro cell and the second macro cell is the same as each other and an arrangement shape of output terminals. 4.

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