JP2007022355A - Control unit for automobile - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control unit for an automobile capable of reducing the probability of improper wake up factor due to noise, and improving power-saving effect. <P>SOLUTION: In an outside wake up signal which is made to be an edge effective signal, when level change is detected, if predetermined timing which is 1 or more after detection timing of the level change on the time series is used as post edge level detection timing, the level of an input signal at the post edge level detection timing is detected (post edge level detecting means 21). Only when change edge is detected and the level of the input signal detected by a post edge level detecting means 23 is a second level, a wake up command signal for waking up a main control portion 3 is outputted (a wake up command signal output means 22). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an automobile control unit, and more particularly to an automobile control unit in which an operation mode can be switched between a normal operation mode and a sleep mode that consumes less power than the normal operation mode.

JP 2002-411141 A JP 2003-318924 A

  In order to control various devices (controlled elements) mounted on the vehicle, the vehicle is mounted with an ECU (control unit) having a CPU as a main control unit. The ECU shifts to the sleep mode under certain conditions, for example, when the vehicle is in a parked state or when there is no switch operation (Patent Documents 1 and 2). Specifically, the sleep mode is a standby mode in which the oscillator that constitutes the ECU is stopped, a slow clock mode that operates with a low-frequency oscillator different from the normal operation, or an intermittent mode in which the CPU is intermittently operated at regular intervals. It means that it is in the low current consumption mode. In particular, as in the keyless entry method, when the user who owns the portable device detects wirelessly that the user has approached the vehicle via the portable device and wants to automatically control operations such as door lock release and engine start, this control is performed. The controlling ECU must always continue to operate even when parking or when the engine is stopped. Especially when the parking time is extended for a long time, if the ECU is continuously operated in the normal operation mode, the battery voltage is lowered and the vehicle cannot be started. Therefore, the sleep control of the ECU has recently become important from the viewpoint of battery protection. It is increasing. Wake-up from sleep mode can be triggered by interrupt processing when an external program start command or input is received (hereinafter referred to as external factor wake-up), and periodically by internal timer control. There are two types of cases where sleep and wakeup are repeated (hereinafter referred to as internal factor wakeup). The latter is used for the purpose of saving power by intermittently generating a signal reception standby period from a user's portable device through a sleep period, as in a keyless entry system, for example.

  During sleep / wake-up control by internal factor wake-up, if a wake-up signal based on, for example, a user pressing a switch is received from the outside during the sleep period, the ECU must wake up immediately. The processing is often performed using a dedicated wakeup detection circuit to which the wakeup signal is directly input. In this case, when the wake-up detection circuit detects even one signal state defined in the content for instructing the wake-up, this is accepted as a normal wake-up signal regardless of the level duration of the signal. It was.

  However, in the above configuration, even if the signal state has an extremely short level duration due to factors such as noise, the wakeup is not originally intended as long as it matches the content of the wakeup command. First, the ECU performs a wake-up operation. As a result, in a situation where noise or the like frequently occurs, there is a problem that the ECU frequently wakes up and power consumption increases.

  The subject of this invention is providing the control unit for motor vehicles which can reduce the generation | occurrence | production probability of the illegal wake-up factor by noise, and can improve a power-saving effect more by extension.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, an automobile control unit of the present invention has a main control unit that controls electrical operation of a controlled element on the automobile, and the operation mode of the main control unit is a normal operation mode. An automotive control unit that is switchable between a sleep mode, which consumes less power than the normal operation mode,
Edge valid signal for waking up the main control unit from the sleep mode to the normal mode, one of the binary signal levels as the first level and the other as the second level, from the first level to the second level An external wakeup signal receiving terminal that uses the changing edge as a wakeup factor,
Edge detection means for determining the second edge of the external wakeup signal as a wakeup effective level, and detecting the change edge of the input signal to the receiving terminal;
When a level change is detected by the edge detection means, one or more predetermined timings chronologically after the level change detection timing are used as the post edge level detection timing. Post-edge level detection means for detecting the level of the input signal;
A wake-up command signal for wake-up of the main control unit is output only when the change edge is detected by the edge detection means and the level of the input signal detected by the post-edge level detection means is the second level. And a wake-up command signal output means.

  The first configuration of the present invention is based on the premise that the external wake-up signal is used as an edge valid signal and is received by a dedicated receiving terminal. In this case, even a short pulse-like noise does not change the situation in which a signal level change edge that causes a wake-up occurs, and may cause a false wake-up. However, in the case of a regular edge valid signal, stable signal processing is to maintain the second level holding state for a while after the edge is formed by energizing the signal from the first level to the second level. It is common sense in realizing.

  Therefore, in the first configuration of the present invention, when a signal edge (level change) is detected by the edge detection means, the signal level persistence state is monitored even after the edge detection. Specifically, one or more predetermined timings chronologically after the level change detection timing are defined as post edge level detection timing, and the level of the input signal at the post edge level detection timing is the second level. A wakeup command signal for waking up the main control unit is output only when the level is set. With this method, in signal edge formation due to noise or the like, since the duration of the signal level after edge detection is generally short, if the post-edge level detection timing is appropriately determined, the signal level at the timing is first. Returning to the level, it can be easily identified that it is not a regular signal edge. In other words, the noise filtering function can be realized by monitoring the signal level sustain state even after edge detection, the probability of occurrence of an illegal wakeup factor can be reduced, and the power saving effect can be further enhanced.

  In the first configuration of the present invention, there can be provided an internal sleep control means for periodically switching the operation of the main control unit between the sleep mode and the normal mode by a timer in a state where the external wakeup signal is not received. . In this case, the wakeup command signal can be used as an activation signal for interrupt wakeup processing when an external wakeup signal is received during the sleep period defined by the internal sleep control means. As a result, the appropriate sleep interval by the internal sleep control means is not disturbed by the influence of noise or the like, and it is possible to effectively prevent the problem that the wakeup is repeated at a cycle shorter than the intended interval.

  The edge detection means periodically samples the level of the external wakeup signal, and stores and holds the sampling result immediately after the sampled signal level changes from the first level to the second level as detection information of the changed edge An edge detection storage unit can be provided. Further, the post edge level detection means stores the sampling result of the external wake-up signal at the post edge level detection timing as a post edge level detection timing as a post edge level detection timing after a change edge is detected. A post edge level detection storage unit to be held can be provided. The wakeup command signal output means outputs a wakeup command signal as a level signal when the level storage contents of the change edge detection storage unit and the post edge level detection storage unit match at the second level. Can be configured.

  To determine whether it is noise or a regular external wakeup signal, a timer measurement using a signal edge as a trigger is possible, but providing timer hardware increases costs and uses a software timer. This leads to an increase in processing load on the main control unit. Therefore, as described above, by combining the detection of the change edge and the signal level detection at the post-edge level detection timing after a certain period of time, a complicated timer hardware or a software timer with a heavy processing load is not used. In both cases, it is possible to determine whether or not the signal is a regular external wakeup signal.

  In this case, a sampling clock signal generation circuit that defines the sampling cycle of the external wakeup signal is provided, and a clock pulse that is a certain number of times after the reference pulse is used with the clock pulse related to detection of a change edge of the sampling clock signal as a reference pulse. The pulse can be used as a post-edge level sampling pulse. When the signal level changes to the second level when the first level is detected up to a certain pulse and the signal level changes to the second level in the subsequent pulse according to the sampling pulse generated at a fixed period. Is a reference pulse related to change edge detection. In the above method, at least two times of a reference pulse and a pulse after a certain number of times from the reference pulse (in order to improve accuracy, each of the plurality of pulses after the reference pulse may be subjected to level detection. The signal level is detected and stored in the change edge detection storage unit and the post edge level detection storage unit. When these stored levels match at the second level, it is determined as a regular external wakeup signal. Simple level sampling and comparison according to the sampling pulse can reliably determine whether or not the signal is a regular external wakeup signal. In this case, if the clock pulse immediately after the reference pulse is used as a post-edge level sampling pulse, the logic of the sampling circuit is further simplified, and a regular external wakeup signal is detected after the change edge is actually detected. The delay until the determination is made is exactly one pulse period, so the delay from the user operation to the wake-up is hardly noticeable.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram of an ECU 1 that forms a control unit for an automobile according to the present invention. The ECU 1 includes a microprocessor (microcomputer) in which a CPU 3, a ROM 5, a RAM 4, and an input / output unit (I / O port) 2 are connected by a bus. In the present embodiment, the ECU 1 is configured as a body system ECU that controls the body system of the automobile, and FIG. 2 shows a schematic architecture thereof. The software installed on the hardware control entity composed of a microprocessor is a platform and an application for realizing a body function that operates on the platform. In addition, in order to distinguish a some application, it attached | subjected and shown with the symbol of 1-n. The platform is for giving a common operating environment to each application even when the base hardware is different. In addition to the basic software (OS) for the application, the platform is linked with the application and hardware. Although it is configured to include an interface program and the like, it is a well-known part conceptually and will not be described in detail.

The application realizes a body function that is a function related to operation of each part of the vehicle by the vehicle user. Specifically, the body system functions include control associated with opening / closing of a door, control associated with opening / closing of a window, control associated with turning on / off a light switch, control of a wireless door lock mechanism employed in a keyless entry system, etc.・ ・ Etc. Specific examples include the following:
-Driver door, passenger door, rear right seat door, rear left seat door, roof lock / unlock, power window operation, etc.
・ Power supply operation for air conditioners, car audio systems, car navigation systems, etc.
-Switch lighting control for room lamp, cockpit lamp, headlight, small lamp, hazard lamp, tail lamp, etc.

  Returning to FIG. 1, each application 1, 2,... Is stored in the ROM 5, and is executed by the CPU 3 on a work area corresponding to each application in the RAM 4. The ECU 1 controls the operation of the above-described various body-related control target devices (controlled elements) by executing each application while referring to external switches, sensors, and other input signals as necessary. However, the ECU 1 shifts to the sleep mode when a certain condition is satisfied, for example, when the vehicle is in a parking state or when there is no switch operation. Specifically, the transition to the sleep mode is performed when the entire ECU 1 is in a low power consumption mode (in this embodiment, the CPU is in a standby state for the start of the next operation). (Main control unit) The operation is shifted to the standby mode in which the operation of the main clock signal output circuit 8 that outputs the operation clock signal of 3 is stopped, and the platform portion of FIG. (Installed in the ROM 5 in FIG. 1).

  The ECU 1 is connected to another hardware control entity (for example, another ECU) via a network bus, and starts operation when a reset instruction or a wake-up factor is determined by communication via the network bus. 3 shows a state in which a plurality of applications 1, 2,... N are sequentially activated by a scheduler formed as a part of the platform function. The sleep management / control software (FIG. 1: in the ROM 5) acquires sleep control information for directly or indirectly specifying the start time and end time of the requested sleep period that differs for each application software. As shown in the upper part of FIG. 6, each application is programmed to set a timer for a requested sleep period and periodically repeat sleep and wakeup. For example, when the keyless entry method is adopted, a radio signal from the user portable device is received and input as “input of switch / sensor, etc.” in FIG. 1, and the door lock control application corresponding to the keyless entry method receives the received signal. The operation control of the ECU 1 is performed so that the standby period is the normal mode period and is repeated alternately with the sleep period.

  As shown in FIG. 1, the above-described timer is executed by each application in software during wakeup, and the next time to wake up before entering sleep is set in the sleep timer of the sleep control circuit 7. When entering the sleep mode, the sleep control circuit 7 sends a sleep signal to the main clock signal generation circuit 8 that provides the operation clock signal of the CPU 3 and stops its operation. On the other hand, when the sleep timer expires, a wakeup signal is output to the CPU 3 to shift to a wakeup process. This process is referred to as an internal wakeup process in this specification, and the wakeup signal that the sleep control circuit 7 outputs to the CPU 3 for this purpose is referred to as an internal wakeup signal. The timer measurement during the sleep is performed using a clock pulse from the sub clock signal generation circuit 6 that is operated separately from the main clock signal generation circuit 8 and continues to operate during the sleep.

  On the other hand, some or all of the applications may receive an interrupt processing command triggered by an external operation signal (light lighting, door lock release command, etc.) regardless of the sleep cycle described above. As wake up from time to time. This process is referred to as an external wake-up process in this specification. A wake-up signal that causes the interrupt processing command is input to a dedicated wake-up terminal 110 provided in the ECU (control unit) 1 via the dedicated wake-up bus shown in FIG. This wakeup signal is referred to as an external wakeup signal in this specification.

  In the vehicle control unit 1 of FIG. 1, an external wake-up signal that wakes up the CPU (control unit) 3 in the external wake-up process is an edge valid signal as shown in FIG. Specifically, one of the binary signal levels is a first level (Lo is assumed in this embodiment), and the other is a second level (Hi is assumed in this embodiment), from the first level to the second level. Is used as a wake-up factor. That is, the change edge of the input signal to the receiving terminal is detected in such a manner that the second level of the external wakeup signal is determined as the wakeup effective level (edge detection means).

  Further, when a level change corresponding to the signal edge is detected by the edge detection means, one or more predetermined timings after the level change detection timing t1 are set to the post-edge level detection timing t2. The input signal level of the external wakeup signal at the post edge level detection timing t2 is detected (post edge level detection means). Then, only when the change edge is detected and the signal level at the post-edge level detection timing t2 is the second level (Hi), the wake-up command signal for waking up the CPU (main control unit) 3 Is output (wake-up command signal output means) so that the ECU 1 wakes up.

  As described above, assuming that the external wake-up signal is an edge valid signal and this is received by a dedicated receiving terminal, even when short-time pulse noise is input as shown in the lower right of FIG. There is no change in the situation in which a signal level change edge that causes wake-up occurs. Therefore, when only determining whether or not a signal edge has been detected, an edge due to noise is also identified as a wakeup factor, which can be a factor of erroneous wakeup. If it is a valid edge valid signal, the signal is activated from the first level to the second level, and after the edge is formed, the second level holding state is maintained for a while, thereby realizing stable signal processing. It is common sense in doing. However, with the simple signal edge detection method as described above, such a post-edge level holding state cannot be identified at all.

  Therefore, in the system of this embodiment shown in FIG. 6, even after the edge (level change) of the signal received by the wake-up terminal is detected, the post-edge level sustaining state is monitored. Since the wake-up command signal is output only when the level at the post-edge level detection timing determined after a certain period from the edge detection timing is the second level (Hi), an illegal wake-up factor is generated due to noise. The probability can be reduced and the power saving effect can be enhanced.

  As described above, the sleep control circuit 7 in FIG. 1 is an internal switch that periodically switches the operation of the CPU (main control unit) 3 between a sleep mode and a normal mode by a timer in a state where an external wakeup signal is not received. It constitutes a sleep control means. The wake-up command signal is used as a start signal for interrupt wake-up processing when an external wake-up signal is received during the sleep period defined by the internal sleep control means.

  The edge detection means periodically samples the level of the external wakeup signal, and changes the sampling result immediately after the sampled signal level changes from the first level (Lo) to the second level (Hi). And a change edge detection storage unit that stores and holds the detection information. Further, the post edge level detection means stores the sampling result of the external wake-up signal at the post edge level detection timing as a post edge level detection timing as a post edge level detection timing after a change edge is detected. A post edge level detection storage unit is provided. The wakeup command signal output means converts the wakeup command signal into a level signal when the level storage contents of the change edge detection storage unit and the post edge level detection storage unit match at the second level (Hi). Output.

  Hereinafter, it will be described in more detail with what hardware configuration the above functions are realized. As shown in FIG. 4, an external sleep signal control circuit 20 that integrates the storage unit and the output function of the wakeup command signal is incorporated in the logic IC that forms the input / output unit 2 of FIG. The external sleep signal control circuit 20 performs a function of converting an external wakeup signal input as an edge valid signal into a level signal. The external sleep signal control circuit 20 receives a signal input via a wakeup terminal and changes its signal level to the above-described method. And a wakeup command signal output unit 22 that outputs a wakeup command signal in the form of a level signal based on the output result of the sampling unit 21. The contents of this level signal are stored in the interrupt request register 124 in a form that designates a port used for wakeup processing interrupt activation. When an interrupt process related to wakeup is activated, a clear signal for clearing latch contents of later-described D flip-flop circuits 23, 24, and 26 (FIG. 5A) included in the sampling unit 21 and the wakeup command signal output unit 23. Is input from the interrupt control register 123 to each of the D flip-flop circuits 23, 24, and 26.

  The ECU 1 also has a sampling clock signal generation circuit that defines the sampling period of the external wake-up signal (in this embodiment, the sub-clock signal generation circuit 6 already described is also used: hereinafter, the same reference numerals are used. A sampling clock signal generation circuit 6). As shown in FIG. 6, a clock pulse related to detection of a change edge of the sampling clock signal (sub clock signal) is used as a reference pulse P, and a clock pulse after a certain number of times after the reference pulse is a sampling pulse at a post edge level. Used as S. The first level (Lo) is detected up to a certain pulse according to the sampling pulse generated at a constant period, and when the signal level changes to the second level (Hi) in the next pulse P, the second level The pulse when the signal level changes to (Hi) is the reference pulse P related to change edge detection. Then, the signal level is detected at least twice in the reference pulse P and a pulse after a predetermined number of times from the reference pulse P, and stored in the change edge detection storage unit and the post edge level detection storage unit, respectively. When the stored levels match at the second level (Hi), it is determined as a regular external wakeup signal.

  The main clock signal generation circuit 8 that generates the operation clock signal of the CPU 3 that forms the main control unit can be configured to stop operating in the sleep mode. Thereby, the dark current at the time of sleep is further reduced, and the power saving effect is enhanced. The sampling clock signal generation circuit 6 is provided separately from the main clock signal generation circuit 8 and is configured to continue operation even in the sleep mode. Even when the operation of the main clock signal generation circuit 8 in the sleep mode is stopped, a clock signal used for sampling of the wakeup signal can be generated, and illegal wakeup can be monitored without problems. The pulse period of the sampling clock signal is preferably set longer than the pulse period of the main clock signal in order to enhance the filtering effect on instantaneous noise (in this embodiment, the frequency of the main clock signal is 4 MHz or 8 MHz, The frequency of the sampling clock signal (sub clock signal) is 25 kHz). Further, if the sampling clock signal generation circuit 6 is constituted by a CR oscillation circuit that does not use an inductor, it is easy to cope with a one-chip configuration when the control system is constituted by an ECU microcomputer. FIG. 5C shows an example in which such a CR oscillation circuit is configured using a Schmitt trigger inverter.

  The external sleep signal control circuit 20 in FIG. 4 can be embodied by a hardware configuration as shown in FIG. 5A. That is, the change edge detection storage unit is configured by the first D flip-flop circuit 24, and the post edge level detection storage unit is configured by the second D flip-flop circuit 23 cascade-connected to the previous stage side of the first D flip-flop circuit 24. Constitute. The sampling clock signal generation circuit 6 is configured to provide a common sampling clock signal for synchronously controlling the first D flip-flop circuit 24 and the second D flip-flop circuit 23. Then, a main AND operation circuit 25 that calculates the logical product of the output of the first D flip-flop circuit 24 and the output of the second D flip-flop circuit 23 is provided. The first D flip-flop circuit 24, the second D flip-flop circuit 23, and the main AND operation circuit 25 constitute the sampling unit 21.

  In the above configuration, the two D flip-flop circuits 23 and 24 connected in cascade sample the external wake-up signal in a pipelined manner in accordance with the pulse period of the sampling clock signal, so that the first D flip-flop circuit is sampled. The output of 24 and the output of the second D flip-flop circuit 23 hold the signal level sampling result by two clock pulses that are continuously input (a plurality of cascaded D flip-flop circuits are (Note that the signal level that precedes in time series is kept closer to the rear side). Therefore, by calculating these logical products in the main logical product operation circuit 25 (which naturally becomes an affirmative output when the two inputs are inputs corresponding to the second level), the output is externally waked up. It can be used directly for signal authenticity determination. Since the main part is composed of two D flip-flop circuits and one AND operation circuit, it is simple and inexpensive, and it is easy to make a one-chip ECU microcomputer.

  Although the output of the main AND circuit 25 can be used as it is as a wakeup command signal, the following configuration is adopted in FIG. 5A in order to further enhance the noise filtering effect. That is, a three-state type in which the wakeup command signal output unit (means) 22 is cascade-connected to the rear stage side of the first D flip-flop circuit 24 and the output of the main AND operation circuit 25 is input as its own output enable signal. The third D flip-flop circuit 26, and an auxiliary AND operation circuit 27 that calculates the logical product of the output of the third D flip-flop circuit 26 and the output of the main AND operation circuit 25. To do. The sampling clock circuit supplies a sampling clock signal (for synchronization control) to the third D flip-flop circuit 26, and uses the level output of the auxiliary AND operation circuit 27 as a wake-up command signal.

  According to the above configuration, the third D flip-flop circuit 26 is a three-state type that uses the output of the main AND operation circuit 25 as an enable signal, and when the output of the main AND operation circuit 25 is negative (that is, two inputs). At least one of them corresponds to the first level), the input from the third D flip-flop circuit 26 to the auxiliary AND operation circuit 27 becomes high impedance, and finally from the auxiliary AND operation circuit 27. The probability of noise leaking into the output wakeup command signal can be greatly reduced.

  As shown in FIG. 5B, the input to the main AND circuit 25 is such that the output B of the first D flip-flop circuit 24 is delayed by one clock cycle with respect to the output A of the second D flip-flop circuit 23. In this case, if the noise width is approximately equal to or smaller than the pulse width of the sampling clock, the two inputs of the main AND circuit 25 are, for example, the first D flip-flop when the second level is Hi (dominant). The rising edge of the input B from the circuit 24 coincides with the falling edge of the input A from the second D flip-flop circuit 23. In this case, ideally, there should be no period in which the main AND circuit 25 is affirmative, but since a certain transition period TP is required for the inversion of the output of the flip-flop circuit, in the middle of the transition period TP Although the output of the main AND operation circuit 25 is instantaneous, there is a possibility that it is inverted to a positive level. In the case where the input inversion from the first D flip-flop circuit 24 to the main AND operation circuit 25 and the input inversion from the second D flip-flop circuit 23 occur based on the same clock pulse edge. It is desirable to provide a wakeup invalidating means for invalidating the instantaneous positive output of the main AND operation circuit 25 accompanying the overlap of the transition periods TP so that it does not participate in the activation of the wakeup process.

  The third D flip-flop circuit 26 and the auxiliary AND operation circuit 27 already described with reference to FIG. 5A also realize the function of the wakeup invalidating means. That is, even if the output of the main AND circuit 25 may instantaneously affirm under the above circumstances, the output of the third D flip-flop circuit 26 is high impedance except during the period in which the output affirmation occurs. On the other hand, the inverted output level from the first D flip-flop circuit 24 is reflected on the output of the third D flip-flop circuit 26 with a delay of one pulse period, resulting in an auxiliary AND operation circuit. The output of 27 (that is, the wakeup command signal) cannot be affirmed. That is, the instantaneous positive output of the main AND operation circuit 25 due to noise is invalidated without being involved in the wake-up process activation.

The block diagram which shows the structure of ECU which concerns on the control unit for motor vehicles of this invention. FIG. 2 is a schematic diagram showing an architecture of the system of FIG. 1. The figure which shows typically the concept of the execution cycle of the some application by a scheduler. The block diagram which shows the structure of the input-output part of ECU of FIG. 1 in detail. The circuit diagram which shows the structural example of an external sleep signal control circuit. Explanatory drawing which shows the influence on the wakeup command signal output by noise. The circuit diagram which shows an example of RC oscillation circuit. Explanatory drawing by 1st of the control unit for motor vehicles of this invention. Action | operation explanatory drawing of a comparative example.

Explanation of symbols

1 ECU (Automotive control unit)
3 CPU (Main Control Unit)
6 Sub clock signal generation circuit (sampling clock signal generation circuit)
8 Main clock signal generation circuit 23 Second D flip-flop circuit (post edge level detection storage unit)
24 1st D flip-flop circuit (change edge detection storage unit)
25 Main AND operation circuit 26 3rd D flip-flop circuit 27 Auxiliary AND operation circuit 110 Reception terminal 120 Wake-up port

Claims (8)

A main control unit that controls the electrical operation of a controlled element on the vehicle, and the operation mode of the main control unit is between a normal operation mode and a sleep mode that consumes less power than the normal operation mode; A control unit for an automobile that is switchable,
An edge valid signal for waking up the main control unit from the sleep mode to the normal mode, wherein one of the binary signal levels is a first level, the other is a second level, An external wakeup signal receiving terminal that uses the transition edge to the second level as a wakeup factor;
Edge detecting means for determining the second level of the external wakeup signal as a wakeup effective level and detecting the change edge of the input signal to the receiving terminal;
When the level change is detected by the edge detection means, the post edge level detection timing is set to one or more predetermined timings chronologically after the level change detection timing as the post edge level detection timing. Post edge level detection means for detecting the level of the input signal in
Wakeup for causing the main control unit to wake up only when the edge detection means detects the change edge and the level of the input signal detected by the post edge level detection means is the second level. A wakeup command signal output means for outputting a command signal;
An automobile control unit comprising: In a state where the external wake-up signal is not received, it has internal sleep control means for periodically switching the operation of the main control unit between the sleep mode and the normal mode by a timer, and the wake-up command signal is 2. The vehicle control unit according to claim 1, wherein the control unit is used as a start signal for an interrupt wakeup process when the external wakeup signal is received during a sleep period defined by the internal sleep control means. The edge detection means periodically samples the level of the external wakeup signal, and uses the sampling result immediately after the sampled signal level changes from the first level to the second level as detection information of the changed edge. A change edge detection storage unit for storing and holding,
The post edge level detection means uses the sampling result of the external wakeup signal at the post edge level detection timing as the post edge level detection timing at a timing after a predetermined time after the detection of the change edge. As a post edge level detection storage unit
The wakeup command signal output means outputs the wakeup command signal when the level storage contents of the change edge detection storage unit and the post edge level detection storage unit match at the second level. The control unit for motor vehicles according to claim 1 or 2. A sampling clock signal generation circuit that defines a sampling period of the external wakeup signal is provided, and a clock pulse that is a certain number of times after the reference pulse with the clock pulse related to detection of the change edge of the sampling clock signal as a reference pulse 3. The vehicle control unit according to claim 2, wherein a pulse is used as the post-edge level sampling pulse. 5. The automobile control unit according to claim 4, wherein a clock pulse immediately after the reference pulse is used as the post-edge level sampling pulse. The main clock signal generation circuit that generates the operation clock signal of the CPU that forms the main control unit stops operating in the sleep mode, and the sampling clock signal generation circuit is separate from the main clock signal generation circuit. The automobile control unit according to claim 4, wherein the automobile control unit is provided and continues to operate even in the sleep mode. A first D flip-flop circuit forming the change edge detection storage unit;
A second D flip-flop circuit that forms the post edge level detection storage unit cascade-connected to the previous stage side of the first D flip-flop circuit;
The sampling clock signal generation circuit provides a common sampling clock signal for synchronously controlling the first D flip-flop circuit and the second D flip-flop circuit,
7. The main logical product operation circuit for calculating a logical product of the output of the first D flip-flop circuit and the output of the second D flip-flop circuit is provided. Car control unit. The wake-up command signal output means is cascade-connected to the rear stage side of the first D flip-flop circuit, and a three-state third D flip-flop in which the output of the main AND operation circuit is input as its own output enable signal And an auxiliary AND operation circuit that calculates a logical product of the output of the third D flip-flop circuit and the output of the AND operation circuit,
8. The sampling clock circuit, which supplies the sampling clock signal to the third D flip-flop circuit, uses the level output of the auxiliary AND operation circuit as the wake-up command signal. Car control unit.

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