JP2007019582A - High frequency power amplifier and radio communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency power amplifier circuit with less temperature dependence on output power in a region wherein the output power is low in a radio communication system for detecting the output power to apply feedback control to the high frequency power amplifier circuit. <P>SOLUTION: The radio communication system wherein a gain of the high frequency power amplifier circuit (210) is controlled by feeding back of a detection output of an output power detection circuit for detecting a level of the output power of the high frequency power amplifier circuit (210), is provided with a precharge circuit (222) for generating and giving a current (Ipre) for complementing deficient sensitivity of the output power detection circuit (221) in the region wherein the output power is low. Further, the precharge circuit is configured such that an output current has the temperature dependence with respect to a change in ambient temperature. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique that is effective when applied to an electronic component (power module) that is used in a radio communication apparatus such as a cellular phone and that amplifies and outputs a high-frequency transmission signal, and particularly for output power. The present invention relates to a technique that is effective when used in a circuit that compensates an output of an output power detection circuit necessary for feedback control.

  In general, a high-frequency power amplifier circuit that amplifies a transmission signal after modulation is provided at an output portion of a transmission system circuit in a wireless communication device (mobile communication device) such as a cellular phone. In conventional wireless communication devices, in order to control the gain of the high-frequency power amplifier circuit according to the transmission request level from the control circuit such as the baseband circuit or the microprocessor, the output power of the high-frequency power amplifier circuit is detected and fed back. It is done. Conventionally, the output power is generally detected using a coupler, a detection circuit, or the like.

  In the conventional output power detection method of a high frequency power amplifier circuit using a coupler, a diode is required to detect the detection output in addition to the size of the coupler itself. Since many semiconductor integrated circuits and electronic parts are used, it has been difficult to reduce the size of the module. Further, when a coupler is used, there is a problem that power loss is relatively large.

  Furthermore, in recent mobile phones, in addition to a method called GSM (Global System for Mobile Communication) using a frequency of 880 to 915 MHz, for example, a DCS (Digital Cellular System) using a frequency of 1710 to 1785 MHz is used. Dual-band mobile phones that can handle various types of signals have been proposed. In the high-frequency power amplification module used in such a cellular phone, an output power amplifier is also provided for each band. Therefore, a coupler and a detection circuit for detecting the output power are also required for each band. Therefore, it becomes difficult to further downsize the module.

  Among the characteristics required for the output power detection circuit of the high frequency power amplifier circuit in the radio communication system, the following five points are particularly important characteristics. First, it is small, second is high sensitivity, third is low insertion loss, fourth is less susceptible to changes in the usage environment such as power supply voltage fluctuations and temperature changes, and fifth, This is because an abnormal current flows through the power amplifier circuit due to a mismatch between the actual output state of the power amplifier circuit and the output control by feedback control, and the power amplifier circuit is not destroyed thereby. The detection method using the conventional coupler almost satisfies the requirements for the second, fourth, and fifth characteristics, but the first miniaturization and the third low insertion loss are sufficient. Did not meet the demands.

Therefore, the present applicant, as a detection method of the output power of the high frequency power amplifier circuit that does not use a coupler, output power through the capacitive element from the middle of the impedance matching circuit connected to the subsequent stage of the final amplifier stage of the high frequency power amplifier circuit. The invention was made to take out the AC component of this and detect it with the output power detection circuit, and filed earlier (Patent Document 1).
JP 2004-328555 A JP 2003-188653 A

  The output power detection circuit according to the prior invention is advantageous in terms of downsizing and low insertion loss compared to a detection method using a coupler, but in a low power region where the output power is low, the detection sensitivity is low and a sufficient detection voltage is provided. Since it is not obtained, feedback is not applied and desired power control cannot be performed. Specifically, the feedback control loop that compares the output level instruction signal Vramp and the detection output of the output power detection circuit and controls the gain of the high frequency power amplifier circuit according to the potential difference is like an open loop in the low power region. Will work. As a result, there is a problem that the output power Pout suddenly rises during the ramp-up operation for raising the output power at the start of transmission, and desired power control cannot be performed.

  Therefore, an invention has been made in which a circuit (sensitivity increasing circuit) for supplying a current that compensates for the lack of sensitivity of the output power detection circuit is provided in the low power region where the detection sensitivity is low, and has been filed earlier (Japanese Patent Application No. 2004-158589). ). However, in the invention according to this prior application, since the current that compensates for the lack of sensitivity of the output power detection circuit does not vary according to the change in the ambient temperature, the output power control characteristic of the high-frequency power amplifier circuit is the temperature as shown in FIG. It has dependency.

  As a result, as shown by a broken line in FIG. 9, the deviation of the output power Pout when the temperature is low (−20 ° C.), that is, the change ΔPout from the output power Pout at the standard value (25 ° C.) is from the target range. It became clear that there was a problem of losing. In FIG. 9, the solid line indicates the deviation of the output power Pout when the temperature is high (85 ° C.), and the alternate long and short dash line indicates the target range.

  On the other hand, as an invention related to the present invention, there has been proposed one that generates a bias voltage that compensates for the temperature dependence of the gain and drain current of an amplifying element (Patent Document 2). However, this prior invention clearly differs from the present invention in that it does not include a circuit for improving the sensitivity of the output power detection circuit in the low power region.

  An object of the present invention is to provide a high frequency power amplifier in which a temperature dependence of output power control characteristics is low in a region where output power is low in a wireless communication system that performs feedback control of a high frequency power amplifier circuit by detecting a level of output power. There is.

Another object of the present invention is a radio communication system that performs feedback control of a high frequency power amplifier circuit by detecting the level of output power, and can perform desired output power control by a control loop even in a region where output power is low. It is to provide a power amplifier.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, in a wireless communication system that controls the gain of a high-frequency power amplifier circuit by feeding back the detection output of the output power detection circuit that detects the level of output power of the high-frequency power amplifier circuit, the output power detection circuit in a region where the output power is low A precharge circuit (sensitivity increasing circuit) is provided that generates and gives a current that compensates for the lack of sensitivity of the (output detection circuit). At the same time, the precharge circuit is configured such that when the ambient temperature changes, the current output from the precharge circuit varies according to the temperature change.

  According to the above means, the apparent detection sensitivity of the output power detection circuit is improved in the region where the output power is low due to the current from the precharge circuit, so that the detection output of the output power detection circuit is small and the feedback control loop Operates like an open loop, and the output power can be prevented from becoming higher than necessary. At the same time, the temperature dependency of the output of the detection circuit is corrected by making the output current of the precharge circuit temperature dependent, so that the output power control characteristics are affected by changes in ambient temperature even in the region where the output power of the high frequency power amplifier circuit is low It can be prevented from fluctuating.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, in a wireless communication system that detects the level of output power and performs feedback control of a high-frequency power amplifier circuit, a high-frequency power amplifier having low temperature dependence of output power control characteristics even in a region where output power is low. Can be realized.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a high-frequency power amplifier to which the present invention is applied. The high-frequency power amplifier of this embodiment is configured as a module by a plurality of semiconductor integrated circuits and discrete electronic components such as resistors and capacitors. In the present specification, a plurality of semiconductor chips and electronic components are mounted on an insulating substrate having printed wiring on the surface or inside, and the components are coupled to each other by the printed wiring or bonding wires so as to play a predetermined role. That is, a high-frequency power amplifier circuit configured to be handled as one electronic device is referred to as a high-frequency power amplifier (power module).

  The power module 200 of this embodiment includes a high frequency power amplification unit 210 including amplification elements 211, 212, and 213 that amplify an input high frequency signal Pin, and an RF detection unit 220 that detects the level of output power of the high frequency power amplification unit 210. And a bias controller 230 that applies a bias to the amplifying element of the high-frequency power amplifier 210 and controls its gain. In the present specification, the high frequency power amplifier 210 may be referred to as a high frequency power amplifier circuit.

  The RF detection unit 220 includes an AC detection circuit 221, a circuit for supplying a current for improving detection sensitivity of the AC detection circuit 221 (referred to as a precharge circuit in this specification) 222, and an output of the AC detection circuit 221. Is an output power detection circuit including a detection voltage calculation circuit 223 that extracts only an AC component of output power as a detection voltage by calculation.

  The bias control unit 230 includes an error amplifier (APC circuit) 231 and a bias circuit 232. The error amplifier 231 compares the detection voltage Vdet output from the detection voltage calculation circuit 220 with the output power level instruction signal Vramp supplied from an external baseband circuit, and outputs a control voltage Vapc according to the potential difference. To do. The bias circuit 232 applies a bias voltage to the amplification elements at each stage of the high-frequency power amplification unit 210 according to the output voltage Vapc of the error amplifier 231.

  FIG. 2 shows a more specific embodiment of the high-frequency power amplifier of FIG. Although not particularly limited, in this embodiment, FETs (field effect transistors) are used as the amplifying elements 211, 212, and 213 of the high-frequency power amplifying unit 210. Of these, the amplifying elements 212 and 213 in the subsequent stages are used as the preceding stages. The gate terminals are connected to the drain terminals of the amplifying elements 211 and 212, so that a three-stage amplifying circuit is formed as a whole.

  In addition, the gate terminals of the bias transistors Qb1, Qb2, and Qb3 are connected to the gate terminals of the amplification elements 211, 212, and 213 at the respective stages via the resistors Rb1, Rb2, and Rb3, respectively, thereby constituting current mirror circuits. ing. Bias currents Ib1, Ib2, and Ib3 supplied from the bias circuit 232 are passed through these transistors Qb1, Qb2, and Qb3, and converted into voltages.

  By applying this voltage to the amplifying elements 211, 212, and 213 as gate bias voltages Vb1, Vb2, and Vb3, an idle current proportional to the bias currents Ib1, Ib2, and Ib3 is applied to the amplifying elements 211, 212, and 213, respectively. It is supposed to be washed away. The ratio of the bias current to the idle current is determined by the size ratio between the bias transistors Qb1, Qb2, Qb3 and the amplifying elements 211, 212, 213.

  As the amplifying elements 211 to 213, MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors) called LDMOS (Laterally Diffused MOSFETs) in which electrodes are diffused laterally on the chip are used. Further, the detection transistor Q1 and the voltage conversion transistor Q4 of the AC detection circuit 221 are also configured by LDMOS having the same structure as the amplification transistors 211 to 213. Thereby, even if the characteristics of the amplifying transistors 211 to 213 vary due to manufacturing variations, the transistors Q1 and Q4 vary in the same manner, so that the accuracy of the detection voltage Vdet can be improved.

  The power supply voltage Vdd is applied to the drain terminals of the amplification elements 211, 212, and 213 at the respective stages via inductors L1, L2, and L3, respectively. An impedance matching circuit 241 and a DC cut capacitive element C1 are provided between the gate terminal of the first stage amplification element 211 and the input terminal In, and the high frequency signal Pin is supplied to the gate of the amplification element 211 via these circuits and elements. Input to the terminal.

  An impedance matching circuit 242 and a direct current cut capacitive element C2 are connected between the drain terminal of the first stage amplifying element 211 and the gate terminal of the second stage amplifying element 212. Further, an impedance matching circuit 243 and a DC cut capacitive element C3 are connected between the drain terminal of the second stage amplifying element 212 and the gate terminal of the last stage amplifying element 213.

  The drain terminal of the final stage amplifying element 213 is connected to the output terminal OUT via the impedance matching circuit 244 and the capacitive element C4, and the signal Pout obtained by cutting the DC component of the high-frequency input signal Pin and amplifying the AC component is obtained. Output. Inductors constituting the impedance matching circuits 241 to 244 can be formed by bonding wires connected between pads of a semiconductor chip or microstrip lines formed on a module substrate.

  The AC detection circuit 221 of this embodiment includes a capacitor Ci having one terminal connected to a microcoupler MCP provided in parallel with the output line between the drain terminal of the amplification element 213 at the final stage and the impedance matching circuit 244. Have. The AC detection circuit 221 includes a transistor Q1, which is an N-channel MOSFET with the other terminal of the capacitor Ci connected to the gate, a transistor Q2, which is a P-channel MOSFET connected in series with the transistor Q1, and the transistor Q2. It has a transistor Q3 which is a P-channel MOSFET connected in a current mirror, and a current-voltage conversion transistor Q4 which is an N-channel MOSFET connected in series with the transistor Q3. Further, the AC detection circuit 221 includes a constant current source CC1 and a transistor Q5, and has a bias generation circuit that applies a gate bias voltage to the transistor Q1.

  Transistor Q5 is configured such that its gate terminal and drain terminal are coupled to act as a diode. The potential of the node N1 is determined by the resistor R1 and the current Ibias flowing through the transistor Q5, and is applied as a bias voltage to the gate terminal of the output detection transistor Q1. In this embodiment, a voltage value close to the threshold voltage of Q1 is set as the value of the bias voltage so that the output detection transistor Q1 can perform a class B amplification operation. Thereby, a current that is proportional to the AC waveform input through the capacitor Ci and half-wave rectified is supplied to the transistor Q1, and the drain current of Q1 has a DC component proportional to the amplitude of the input AC signal. To be included.

  The drain current Id of the transistor Q1 is transferred to the Q3 side by the current mirror circuit of Q2 and Q3, and is converted into a voltage by the diode-connected transistor Q4. Here, the transistors Q1 and Q4 and Q2 and Q3 are set to have a predetermined size ratio. Thereby, for example, when the characteristics (particularly the threshold voltage) of the transistors Q1 and Q2 vary due to manufacturing variations, the characteristics of the transistors Q4 and Q3 paired therewith also vary in the same way. As a result, the influence due to the characteristic variation is offset, and an output detection voltage that is not affected by the transistor variation appears at the drain terminal of the transistor Q4.

  The detection voltage calculation circuit 223 includes a buffer circuit BFF1 for impedance conversion of the voltage converted by the transistor Q4, a buffer circuit FF2 for impedance conversion of a bias voltage generated by the constant current source CC1 and the transistor Q5, and a buffer circuit BFF1. A subtracting circuit SUB that outputs a voltage obtained by subtracting the output of BFF2 from the output. As a result, the output of the subtraction circuit SUB becomes a detection voltage Vdet proportional to the AC component of pure output power not including the DC component (bias voltage) applied by the bias generation circuit (CC1, Q5). A voltage follower is used for the buffer circuits BFF1 and BFF2.

  FIG. 3 shows a specific circuit example of the precharge circuit 222 that increases the detection sensitivity of the AC detection circuit 221. In this embodiment, the circuit for generating the current of the precharge circuit 222 and the circuit for generating the current in the bias circuit 231 are partially shared, and therefore, a circuit example of the bias circuit 232 is also illustrated. I will explain.

  The bias circuit 232 of this embodiment includes a differential amplifier AMP0 that receives a voltage obtained by dividing the output control voltage Vapc supplied from the error amplifier 250 by resistors R11 and R12 at a non-inverting input terminal, a power supply voltage Vdd, and a ground point. And a transistor Q10 and a resistor R10 connected in series. Also, the bias circuit 232 is provided with a transistor Q11 that receives the same gate voltage as the transistor Q10 at the gate and flows a current proportional to the drain current of Q10. The potential V0 of the connection node between the transistor Q10 and the resistor R10 is fed back to the inverting input terminal of the differential amplifier AMP0, so that a current I1A that makes V0 coincide with the input voltage Vapc · R11 / (R11 + R12) It is sent to Q10. Thus, the current I1A becomes a current that linearly changes according to the input voltage Vapc.

  Further, by forming the gate widths of the transistors Q10 and Q11 to have a predetermined size ratio, a current I1 proportional to I1A flows through Q11. The transistor Q11 is connected to a diode-connected transistor Q12, and a current I1B obtained by subtracting a bypass current I3 flowing from the current I1A into the constant current generating circuit 222A is supplied to Q12. This current I1B is transferred to Q12 and Q13 constituting a current mirror, and further flows to Q14 connected in series with Q13.

  Transistors Q15 to Q19 connected in common to the gate are connected to Q14, and Q14 and Q15 to Q19 constitute current mirrors, respectively, so that a current proportional to the size ratio flows. Of Q15 to Q19, Q15 to Q17 are transistors that generate bias currents Ib1, Ib2, and Ib3 supplied to the bias transistors Qb1, Qb2, and Qb3 of the high-frequency power amplifier 210. Q18 and Q19 are transistors that generate currents IA and IB supplied to the precharge circuit 222. In this embodiment, IA = IB.

  On the other hand, the precharge circuit 222 includes a constant current generation circuit 222A that generates a current I2 (= constant) having a predetermined magnitude based on the reference voltage Vref, a temperature compensation circuit 222B that generates a temperature compensation current, and the bias. The current combining circuit 222C generates a precharge current Ipre for increasing sensitivity flowing into the drain of the transistor Q4 based on the currents IA and IB generated by the circuit 232.

  Among them, the constant current generation circuit 222A includes a differential amplifier AMP1 in which a reference voltage Vref that is generated by a circuit such as a bandgap reference circuit and has no power dependency and temperature dependency is applied to a non-inverting input terminal, and a power supply A transistor Q20 and a resistor R20 are connected in series between the voltage Vdd and the ground. The constant current generating circuit 222A is provided with a transistor Q21 that receives the same gate voltage as that of the transistor Q20 at the gate and flows a current proportional to the drain current of Q20. The potential V1 at the connection node between the transistor Q20 and the resistor R20 is fed back to the inverting input terminal of the differential amplifier AMP1, so that a current I2A that causes V1 to coincide with the input voltage Vref flows through the transistor Q20.

  Further, by forming the gate widths of the transistors Q20 and Q21 to have a predetermined size ratio, a current I2B proportional to I2A is caused to flow through Q21. The transistor Q21 is connected to a diode-connected transistor Q22, and a current I2 proportional to the current I2B flows through Q22 that forms a current mirror with Q22. The current I2 is configured to draw a part of the drain current I1 of the transistor Q11 of the bias circuit 232.

  The temperature compensation circuit 222B includes a differential amplifier AMP2 to which the reference voltage Vref is applied to the non-inverting input terminal, a transistor Q24, a resistor R21, and a diode D1 connected in series between the power supply voltage Vdd and the ground point. The potential V2 at the connection node between the transistor Q24 and the resistor R21 is fed back to the inverting input terminal of the differential amplifier AMP2, so that a current ITA that causes V2 to match the input voltage Vref flows through the transistor Q24.

  Here, assuming that the forward voltage of the diode D1 is Vf and the resistance value of the resistor R21 is r, it is expressed by ITA = (Vref−Vf) / r. Since the forward voltage Vf of the diode D1 has a negative temperature characteristic, as shown in FIG. 4B, the current ITA changes in proportion to the temperature Ta. Further, the temperature compensation circuit 222B is provided with a transistor Q25 that receives the same gate voltage as the transistor Q24 at its gate and flows a current IT proportional to the drain current ITA of Q24. The drain terminal of the transistor Q25 is connected to the drain terminal of the transistor Q23 of the constant current generating circuit 222A. As a result, a current (IT + I3) obtained by adding the output current IT of the temperature compensation circuit 222B and the current I3 from the transistor Q11 of the bias circuit 232 flows to the transistor Q23 of the constant current generation circuit 222A. As a result, the current I3 drawn from the transistor Q11 is I3 = I2-IT.

  By the way, the output current IT of the temperature compensation circuit 222B is a current proportional to the temperature Ta as shown in FIG. 4B, and the current I2 drawn by the constant current generation circuit 222A is as shown in FIG. Constant current regardless of temperature. As a result, the current I3 drawn from the transistor Q11 of the bias circuit 232 changes so as to decrease as the temperature increases, as shown in FIG. That is, the current I1B flowing through the transistors Q12 and Q13 increases as the temperature increases.

  On the other hand, when the temperature compensation circuit 222B is not provided, the currents Ib1 to Ib3, IA, and IB output from the bias circuit 232 increase as the temperature decreases as indicated by the broken line in FIG. As shown, the higher the temperature, the less. Therefore, when the current I3 is changed as shown in FIG. 4C, the output currents Ib1 to Ib3, IA, and IB of the bias circuit 232 have the control voltage Vapc along substantially the same characteristic line regardless of the temperature. Changes in proportion to

  In the current synthesis circuit 222C, the drains are connected to the transistors Q32 and Q32, which are connected in common to the so-called diode-connected transistors Q31 and Q31 in which the source terminal is connected to the ground and the gate and the drain are coupled to form a current mirror circuit. And a diode-connected transistor Q33. The current synthesis circuit 222C is connected in common to the gate of the transistor Q33, which is connected in common to the transistor Q33 and forms a current mirror circuit, and is connected to diode-connected transistors Q35 and Q35 in which the drains are connected to each other. A transistor Q36 is formed. Furthermore, the current synthesis circuit 222C includes a transistor Q37 that is a diode-connected P-channel MOSFET connected in series with the transistor Q36, and a transistor Q38 that is a P-channel MOSFET that is connected in common to the transistor Q37 and forms a current mirror circuit. Have

  Then, the reference current Iref having no power supply dependency and temperature dependency is generated in the transistor Q31, the current IA generated by the bias circuit 232 is generated in the drain of the transistor Q32, and the bias circuit 232 is further generated in the drain of the transistor Q34. The current IB is flown respectively. Transistors Q31 to Q36 are formed to have the same element size, and Q37 and Q38 have the same element size. As a result, a current of IA-Iref flows through the transistor Q33 when Iref <IA, and no current flows when Iref> IA. Further, a current of IB- (IA-Iref) flows through the transistor Q35.

  Here, as described above, since IA = IB, a current of Iref (= constant) flows through the transistor Q35 when Iref <IB, and a current IB flows when Iref> IB. Is done. This current is transferred to the transistor Q36, and further transferred to Q38 by the transistors Q37 and Q38 constituting the current mirror, and output as a precharge current Ipre for increasing sensitivity. As a result, as shown by the solid line in FIG. 5, the precharge current Ipre for increasing the sensitivity gradually increases with Ipre = IB (= IA) until IA and IB reach Iref. When it becomes Iref or more, a current of Ipre = Iref (= constant) flows.

  When the precharge current Ipre as described above flows into the drain of the transistor Q4 in the AC detection circuit 221 in FIG. 2, the drain voltage of Q4 increases accordingly, so that the voltage is supplied to Q3 according to the input through the capacitive element Ci. Even if a small amount of current flows, the detection sensitivity of the AC detection circuit 221 increases in a region where the output power is low. As a result, the detection voltage Vdet output from the AC detection circuit 221 and supplied to the error amplifier 231 is raised, and the controllability of the output power Pout in the region where the output level instruction signal Vramp is low is improved. In addition, since the temperature compensation circuit 222B is provided in the precharge circuit 222 of this embodiment, and the currents IA and IB supplied to the current synthesis circuit 222C change with respect to the temperature change, the precharge circuit for increasing the sensitivity is output. The charge current Ipre is also a temperature-dependent current.

  As a result, in this embodiment, as shown in FIG. 6, the temperature variation of the characteristics of the output power Pout with respect to the output level instruction signal Vramp can be reduced. Further, as a result, as shown in FIG. 8, the deviation of the output power Pout can be kept within the target range. In FIG. 6, (B) shows the scale of the horizontal axis of the graph of (A) with a wider scale.

  In FIG. 8, the solid line shows a change ΔPout from the output power Pout at the standard value (25 ° C.) when the temperature Ta is the maximum value (85 ° C.) of the allowable fluctuation range, and is a broken line. Shows a change ΔPout from the output power Pout at the standard value when the temperature Ta is the minimum value (−20 ° C.) of the allowable fluctuation range by simulation.

  In the GSM standard, the deviation ΔPout of the output power Pout is defined as ± 6 dB when the output power is in the range of 5 dBm to 11 dBm, and ± 4 dB when the output power is in the range of 11 dBm to 35 dBm. In FIG. 8, what is indicated by a one-dot chain line is a restriction line indicating a target range determined by the present inventors in consideration of the GSM standard and the user's request. From FIG. 8, it can be seen that the deviation ΔPout of the output power Pout can be substantially within the target range by applying this embodiment.

  In the embodiment of FIG. 3, the bias currents Ib1 to Ib1 supplied to the high-frequency power amplifier circuit 210 are changed simultaneously with the currents IA and IB supplied to the current synthesis circuit 222C of the precharge circuit 222 according to the ambient temperature. The bias circuit 232 is configured so that Ib3 also changes according to the ambient temperature. As described above, the bias currents Ib <b> 1 to Ib <b> 3 also have temperature dependency, so that the gain can be suppressed from changing due to the temperature dependency of the amplification elements 211 to 213.

  Originally, in the system having a control loop that feeds back the detection output of the output power detection circuit and controls the gain of the high-frequency power amplification circuit as in this embodiment, if the sensitivity of the output power detection circuit is good, the bias transistors Qb1 to Qb1 Even if the gain of Qb3 varies with temperature, feedback is applied so that the variation is not visible. However, if the sensitivity in the low power region is low as in the output power detection circuit in this embodiment, feedback does not occur in the low power region, and changes in the gains of Qb1 to Qb3 accompanying changes in temperature can be seen.

  On the other hand, the gains of the amplifying elements 211 to 213 can be prevented from changing due to temperature fluctuations by giving the bias currents Ib1 to Ib3 temperature dependency as in the above embodiment. However, in the circuit of FIG. 3, instead of passing the current IT of the transistor Q25 to Q23, the current is supplied to the drain terminal side of Q18 and added to the current of Q18 and supplied to the current synthesis circuit 222C as the current IA. Further, similarly to Q25, another transistor whose gate terminal is connected to the gate terminal of Q24 is provided, and the sum of the current and the current of Q19 is supplied to the current synthesis circuit 222C as the current IB. By doing so, it is possible to prevent the bias currents Ib1 to Ib3 from having temperature dependency.

  The case where the present invention is applied to the power module in which the amplifying elements 211 to 213 of the high frequency power amplifying unit 210 are biased in proportion to the control voltage Vapc by the current mirror method has been described above. The present invention is not limited to such an embodiment, and the power module is configured to apply a voltage by dividing the control voltage Vapc by the resistance divider circuit to the gate terminals or the base terminals of the amplifying elements 211 to 213 to give a bias. Can also be applied, thereby obtaining a similar effect.

  However, even in that case, a variable current generating circuit corresponding to the bias circuit 232 of FIG. 3 for generating currents IA and IB proportional to Vapc is necessary. The variable current generation circuit is a circuit in which the transistors Q15 to Q17 that generate the bias currents Ib1 to Ib3 from the bias circuit 232 of FIG. 3 are omitted. In other words, the current mirror bias type power module that has temperature dependency on the bias current is the most of the variable current generation circuit for the precharge circuit and the bias circuit 232. Elements can be shared, and thereby an increase in circuit scale can be suppressed.

FIG. 10 shows a schematic configuration of a system capable of wireless communication of two communication systems, GSM and DCS, as an example of an effective wireless communication system to which the power module of the embodiment is applied.
In FIG. 10, reference numeral 110 denotes a modulation / demodulation circuit capable of performing GMSK modulation and demodulation in a GSM or DCS system, or an I, Q signal generated based on transmission data (baseband signal) or an I, Q extracted from a received signal. A high-frequency signal processing circuit (baseband circuit) 110 having a circuit for processing a Q signal. The baseband circuit 110 and the low noise amplifiers LNA1, LNA2, and the like that amplify the received signal are formed as a semiconductor integrated circuit (baseband IC) on one semiconductor chip.

  Further, bandpass filters BPF1 and BPF2 for removing harmonic components from the baseband IC and transmission signal, bandpass filters BPF3 and BPF4 for removing unnecessary waves from the received signal, and the like are mounted in one package. RF device). Tx-MIX1 and Tx-MIX2 are mixers for up-converting GSM and DCS transmission signals, and Rx-MIX1 and Rx-MIX2 are mixers for down-converting GSM and DCS reception signals.

  In FIG. 10, reference numeral 200 denotes the power module of the above-described embodiment that amplifies the high-frequency signal supplied from the baseband IC 100, and 300 denotes filters LPF1, LPF2, and GSM signals that remove noise such as harmonics contained in the transmission signal And a duplexer DPX1, DPX2 that synthesizes and separates DCS signals, a transmission / reception changeover switch T / R-SW, and the like.

  As shown in FIG. 10, in this embodiment, a mode selection signal VBAND indicating GSM or DCS is supplied from the baseband IC 110 to the bias circuit 232, and the bias circuit 232 is based on the control signal VBAND. A bias current corresponding to the mode is generated and supplied to one of the power amplifiers 210a and 210b. Further, the output level instruction signal Vramp is supplied from the baseband IC 110 to the error amplifier (APC circuit) 231, and the error amplifier 231 compares the output level instruction signal Vramp with the detection voltage Vdet from the RF detection unit 220 to compare with the bias circuit 232. An output control signal Vapc for is generated and supplied. The bias circuit 232 controls the gains of the power amplifiers 210a and 210b according to the output control signal Vapc, and is controlled so that the output power of the power amplifiers 210a and 210b changes accordingly.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the power amplifying elements of the high-frequency power amplifying unit 210 are connected in three stages, but a two-stage configuration or a four-stage or more configuration may be used.

  In the embodiment, the LDMOS is used as the power amplification elements 211 to 213. However, a MOSFET, a bipolar transistor, a GaAs MESFET, a heterojunction bipolar transistor (HBT), a HEMT ( Other transistors such as High Electron Mobility Transistor) may be used. However, in this case, it is desirable that the detection transistor Q1 and the current-voltage conversion transistor Q2 are also composed of the same elements as the amplification transistors 211 to 213.

  In the above description, when the invention made mainly by the present inventor is applied to a power module constituting a dual-mode wireless communication system capable of transmission / reception by two communication systems, GSM and DCS, which are the fields of use behind it. Explained. The present invention is not limited to this, and wireless communication such as a multi-mode mobile phone or mobile phone capable of transmission / reception by other communication methods or three or more communication methods such as GSM, DCS, and PCS (Personal Communications System). It can be used for a power module constituting a system or a power module for a wireless LAN.

It is a block diagram which shows the Example of the output power detection circuit which concerns on this invention, and the high frequency power amplifier (power module) to which it is applied. FIG. 2 is a circuit configuration diagram showing a more specific example of the high-frequency power amplifier of FIG. 1. FIG. 6 is a circuit diagram showing a specific circuit example of a precharge circuit for increasing the sensitivity of an AC detection circuit in a low power region. 4A to 4C are characteristic diagrams showing the relationship between the internal current and temperature in the precharge circuit of the embodiment, and FIG. 4D is a diagram showing the output control voltage Vapc and the generated currents IA and IB of the precharge circuit. It is a graph which shows the relationship. It is a graph which shows the relationship between the output control voltage Vapc and the precharge electric current Ipre in the precharge circuit of an Example. It is a graph which shows the control characteristic of the output electric power in the high frequency power amplifier to which the precharge circuit of an Example is applied. It is a graph which shows the control characteristic of the output power in the high frequency power amplifier to which the precharge circuit which does not have the conventional temperature compensation circuit is applied. It is a graph which shows the result of having calculated | required the output deviation of the output electric power Pout in the feedback control system with the high frequency power amplifier to which the precharge circuit of an Example was applied by simulation. It is a graph which shows the result of having calculated | required the output deviation of the output electric power Pout in the feedback control system of the high frequency power amplifier examined prior to this invention by simulation. It is a block diagram which shows the schematic structure of the system which can perform radio | wireless communication of two communication systems, GSM and DCS, to which the high frequency power amplifier of this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 RF device 110 Baseband circuit 200 Power module 210, 210a, 210b High frequency power amplification circuit 211, 212, 213 Amplification element (amplification FET)
220 RF detection unit 221 AC detection circuit 222 Precharge circuit 222A Constant current generation circuit 222B Temperature compensation circuit 222C Current synthesis circuit 223 Detection voltage calculation circuit 230 Bias control unit 231 Error amplifier 232 Bias circuit 241 to 244 Impedance matching circuit 300 Front end module

Claims (10)

  A high-frequency power amplifier circuit that amplifies a high-frequency signal according to an output power control voltage; and an output power detection circuit that detects a level of output power of the high-frequency power amplifier circuit, and feeds back a detection output of the output power detection circuit. A high-frequency power amplifier used in a radio communication system for controlling the gain of the high-frequency power amplifier circuit, and generating and flowing a current that compensates for insufficient sensitivity of the output power detection circuit in a region where the output power is low A high-frequency power amplifier comprising a circuit, wherein the precharge circuit generates a current that prevents the output power of the high-frequency power amplifier circuit from fluctuating due to a change in ambient temperature.   When the output power control voltage is lower than a predetermined level, the precharge circuit generates a current corresponding to the output power control voltage and supplies it to the detection unit of the output power detection circuit to improve detection sensitivity. The high-frequency power amplifier according to claim 1, wherein   3. The high frequency signal according to claim 2, further comprising an error amplifying circuit for generating the output power control voltage by comparing a signal indicating an output level supplied from the outside with an output of the output power detection circuit. Power amplifier.   4. The high-frequency power amplifier according to claim 3, wherein the high-frequency power amplifier circuit includes a plurality of amplification transistors, and further includes a bias circuit that applies a bias to the amplification transistor in accordance with the output power control voltage.   The precharge circuit includes a constant current generation circuit that generates an offset current having a predetermined magnitude based on a reference voltage, a compensation current generation circuit that generates a current proportional to an ambient temperature, and the offset current and output power. A variable current generation circuit that generates a current proportional to the output power control voltage when the control voltage is equal to or higher than a predetermined level based on the control voltage, a current generated by the variable current generation circuit, and a reference current 5. The high frequency power amplifier according to claim 4, comprising a current synthesis circuit that synthesizes and outputs a current that changes in accordance with desired characteristics.   A bias transistor connected to the amplifying transistor in a current mirror connection; the bias circuit generates a bias current having temperature dependency and flows the bias transistor; and the temperature dependency of the bias circuit depends on the amplifying transistor. 6. The high frequency power amplifier according to claim 5, wherein temperature dependency of output power is reduced.   The precharge circuit combines a constant current generation circuit that generates an offset current having a predetermined magnitude, a compensation current generation circuit that generates a compensation current proportional to temperature, and a predetermined current and a reference current. And a bias current that is proportional to the output power control voltage based on the offset current, the compensation current, and the output power control voltage, and the predetermined current. The high frequency power amplifier according to claim 6, wherein the high frequency power amplifier is configured to generate a current of   The output power detection circuit includes a first transistor to which an AC signal input from an output unit of the power amplifier circuit via a coupling capacitor is applied to a control terminal, and a second transistor connected in series with the first transistor And a third transistor connected in current mirror with the second transistor, and a current-voltage conversion transistor connected in series with the third transistor, and the current generated by the precharge circuit is the current − The high-frequency power amplifier according to claim 1, wherein the high-frequency power amplifier is configured to flow through a voltage conversion transistor.   A bias generation circuit for providing an operating point to the control terminal of the first transistor, and a difference between a voltage converted by the current-voltage conversion transistor and a voltage applied to the first transistor by the bias generation circuit The high-frequency power amplifier according to claim 8, further comprising: an arithmetic circuit that outputs a voltage as a detection voltage.   10. A high-frequency power amplifier according to claim 3, a baseband circuit that generates a high-frequency signal amplified by the high-frequency power amplifier circuit and a signal indicating the output level and supplies the generated signal to the high-frequency power amplifier A wireless communication device.

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